Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers [ARM] Add Integrator support for glibc outb() and friends [ARM] Move prototype for register_isa_ports to asm/io.h [ARM] Arrange for isa.c to use named initialisers [ARM] 3741/1: remove sa1111.c build warning on non-sa1100 systems [ARM] 3760/1: This patch adds timeouts while working with SSP registers. Such timeouts were en [ARM] 3758/1: Preserve signalling NaNs in conversion [ARM] 3749/3: Correct VFP single/double conversion emulation [ARM] 3748/3: Correct error check in vfp_raise_exceptions
This commit is contained in:
Linus Torvalds
commit
1b8b22f44b
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@ -47,7 +47,8 @@ comma = ,
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# testing for a specific architecture or later rather impossible.
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arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
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arch-$(CONFIG_CPU_32v6K) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
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arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4)
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arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
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arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
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arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
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arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
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@ -618,7 +618,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
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{
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struct sa1111 *sachip;
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unsigned long id;
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unsigned int has_devs, val;
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unsigned int has_devs;
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int i, ret = -ENODEV;
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sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL);
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@ -669,6 +669,9 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
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sa1111_wake(sachip);
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#ifdef CONFIG_ARCH_SA1100
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{
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unsigned int val;
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/*
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* The SDRAM configuration of the SA1110 and the SA1111 must
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* match. This is very important to ensure that SA1111 accesses
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@ -692,6 +695,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq)
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* Enable the SA1110 memory bus request and grant signals.
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*/
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sa1110_mb_enable();
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}
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#endif
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/*
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@ -13,12 +13,11 @@ obj-y := compat.o entry-armv.o entry-common.o irq.o \
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obj-$(CONFIG_APM) += apm.o
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obj-$(CONFIG_ISA_DMA_API) += dma.o
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obj-$(CONFIG_ARCH_ACORN) += ecard.o
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obj-$(CONFIG_FOOTBRIDGE) += isa.o
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obj-$(CONFIG_FIQ) += fiq.o
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obj-$(CONFIG_MODULES) += armksyms.o module.o
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obj-$(CONFIG_ARTHUR) += arthur.o
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obj-$(CONFIG_ISA_DMA) += dma-isa.o
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obj-$(CONFIG_PCI) += bios32.o
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obj-$(CONFIG_PCI) += bios32.o isa.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
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@ -3,21 +3,14 @@
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*
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* Copyright (C) 1999 Phil Blundell
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*
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* ISA shared memory and I/O port support
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*/
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* ISA shared memory and I/O port support, and is required to support
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* iopl, inb, outb and friends in userspace via glibc emulation.
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*/
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/*
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* Nothing about this is actually ARM specific. One day we could move
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* it into kernel/resource.c or some place like that.
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*/
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#include <linux/stddef.h>
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#include <linux/types.h>
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#include <linux/fs.h>
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@ -27,21 +20,49 @@
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static unsigned int isa_membase, isa_portbase, isa_portshift;
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static ctl_table ctl_isa_vars[4] = {
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{BUS_ISA_MEM_BASE, "membase", &isa_membase,
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sizeof(isa_membase), 0444, NULL, &proc_dointvec},
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{BUS_ISA_PORT_BASE, "portbase", &isa_portbase,
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sizeof(isa_portbase), 0444, NULL, &proc_dointvec},
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{BUS_ISA_PORT_SHIFT, "portshift", &isa_portshift,
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sizeof(isa_portshift), 0444, NULL, &proc_dointvec},
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{0}
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{
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.ctl_name = BUS_ISA_MEM_BASE,
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.procname = "membase",
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.data = &isa_membase,
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.maxlen = sizeof(isa_membase),
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.mode = 0444,
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.proc_handler = &proc_dointvec,
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}, {
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.ctl_name = BUS_ISA_PORT_BASE,
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.procname = "portbase",
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.data = &isa_portbase,
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.maxlen = sizeof(isa_portbase),
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.mode = 0444,
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.proc_handler = &proc_dointvec,
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}, {
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.ctl_name = BUS_ISA_PORT_SHIFT,
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.procname = "portshift",
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.data = &isa_portshift,
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.maxlen = sizeof(isa_portshift),
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.mode = 0444,
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.proc_handler = &proc_dointvec,
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}, {0}
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};
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static struct ctl_table_header *isa_sysctl_header;
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static ctl_table ctl_isa[2] = {{CTL_BUS_ISA, "isa", NULL, 0, 0555, ctl_isa_vars},
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{0}};
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static ctl_table ctl_bus[2] = {{CTL_BUS, "bus", NULL, 0, 0555, ctl_isa},
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{0}};
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static ctl_table ctl_isa[2] = {
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{
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.ctl_name = CTL_BUS_ISA,
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.procname = "isa",
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.mode = 0555,
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.child = ctl_isa_vars,
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}, {0}
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};
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static ctl_table ctl_bus[2] = {
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{
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.ctl_name = CTL_BUS,
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.procname = "bus",
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.mode = 0555,
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.child = ctl_isa,
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}, {0}
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};
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void __init
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register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift)
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@ -35,7 +35,6 @@
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extern int setup_arm_irq(int, struct irqaction *);
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extern void pcibios_report_status(u_int status_mask, int warn);
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extern void register_isa_ports(unsigned int, unsigned int, unsigned int);
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static unsigned long
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dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
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@ -600,4 +600,6 @@ void __init pci_v3_postinit(void)
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printk(KERN_ERR "PCI: unable to grab local bus timeout "
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"interrupt: %d\n", ret);
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#endif
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register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
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}
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@ -47,14 +47,15 @@ static struct corgissp_machinfo *ssp_machinfo;
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*/
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unsigned long corgi_ssp_ads7846_putget(ulong data)
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{
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unsigned long ret,flag;
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unsigned long flag;
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u32 ret = 0;
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spin_lock_irqsave(&corgi_ssp_lock, flag);
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if (ssp_machinfo->cs_ads7846 >= 0)
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GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
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ssp_write_word(&corgi_ssp_dev,data);
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ret = ssp_read_word(&corgi_ssp_dev);
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ssp_read_word(&corgi_ssp_dev, &ret);
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if (ssp_machinfo->cs_ads7846 >= 0)
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GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
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@ -88,7 +89,9 @@ void corgi_ssp_ads7846_put(ulong data)
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unsigned long corgi_ssp_ads7846_get(void)
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{
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return ssp_read_word(&corgi_ssp_dev);
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u32 ret = 0;
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ssp_read_word(&corgi_ssp_dev, &ret);
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return ret;
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}
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EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
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@ -104,6 +107,7 @@ EXPORT_SYMBOL(corgi_ssp_ads7846_get);
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unsigned long corgi_ssp_dac_put(ulong data)
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{
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unsigned long flag, sscr1 = SSCR1_SPH;
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u32 tmp;
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spin_lock_irqsave(&corgi_ssp_lock, flag);
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@ -118,7 +122,7 @@ unsigned long corgi_ssp_dac_put(ulong data)
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GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
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ssp_write_word(&corgi_ssp_dev,data);
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/* Read null data back from device to prevent SSP overflow */
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ssp_read_word(&corgi_ssp_dev);
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ssp_read_word(&corgi_ssp_dev, &tmp);
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if (ssp_machinfo->cs_lcdcon >= 0)
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GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
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@ -150,7 +154,7 @@ EXPORT_SYMBOL(corgi_ssp_blduty_set);
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int corgi_ssp_max1111_get(ulong data)
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{
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unsigned long flag;
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int voltage,voltage1,voltage2;
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long voltage = 0, voltage1 = 0, voltage2 = 0;
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spin_lock_irqsave(&corgi_ssp_lock, flag);
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if (ssp_machinfo->cs_max1111 >= 0)
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@ -163,15 +167,15 @@ int corgi_ssp_max1111_get(ulong data)
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/* TB1/RB1 */
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ssp_write_word(&corgi_ssp_dev,data);
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ssp_read_word(&corgi_ssp_dev); /* null read */
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ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
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/* TB12/RB2 */
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ssp_write_word(&corgi_ssp_dev,0);
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voltage1=ssp_read_word(&corgi_ssp_dev);
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ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
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/* TB13/RB3*/
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ssp_write_word(&corgi_ssp_dev,0);
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voltage2=ssp_read_word(&corgi_ssp_dev);
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ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
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ssp_disable(&corgi_ssp_dev);
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ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
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@ -40,6 +40,8 @@
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#define PXA_SSP_PORTS 3
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#define TIMEOUT 100000
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struct ssp_info_ {
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int irq;
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u32 clock;
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@ -92,13 +94,18 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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* The caller is expected to perform the necessary locking.
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*
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* Returns:
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* %-ETIMEDOUT timeout occurred (for future)
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* %-ETIMEDOUT timeout occurred
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* 0 success
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*/
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int ssp_write_word(struct ssp_dev *dev, u32 data)
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{
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while (!(SSSR_P(dev->port) & SSSR_TNF))
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int timeout = TIMEOUT;
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while (!(SSSR_P(dev->port) & SSSR_TNF)) {
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if (!--timeout)
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return -ETIMEDOUT;
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cpu_relax();
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}
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SSDR_P(dev->port) = data;
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@ -117,15 +124,21 @@ int ssp_write_word(struct ssp_dev *dev, u32 data)
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* The caller is expected to perform the necessary locking.
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*
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* Returns:
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* %-ETIMEDOUT timeout occurred (for future)
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* %-ETIMEDOUT timeout occurred
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* 32-bit data success
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*/
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int ssp_read_word(struct ssp_dev *dev)
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int ssp_read_word(struct ssp_dev *dev, u32 *data)
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{
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while (!(SSSR_P(dev->port) & SSSR_RNE))
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cpu_relax();
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int timeout = TIMEOUT;
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|
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return SSDR_P(dev->port);
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while (!(SSSR_P(dev->port) & SSSR_RNE)) {
|
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if (!--timeout)
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return -ETIMEDOUT;
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cpu_relax();
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}
|
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|
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*data = SSDR_P(dev->port);
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return 0;
|
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}
|
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|
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/**
|
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|
|
@ -136,13 +149,21 @@ int ssp_read_word(struct ssp_dev *dev)
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*
|
||||
* The caller is expected to perform the necessary locking.
|
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*/
|
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void ssp_flush(struct ssp_dev *dev)
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int ssp_flush(struct ssp_dev *dev)
|
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{
|
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int timeout = TIMEOUT * 2;
|
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|
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do {
|
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while (SSSR_P(dev->port) & SSSR_RNE) {
|
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if (!--timeout)
|
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return -ETIMEDOUT;
|
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(void) SSDR_P(dev->port);
|
||||
}
|
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if (!--timeout)
|
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return -ETIMEDOUT;
|
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} while (SSSR_P(dev->port) & SSSR_BSY);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
#include <asm/hardware.h>
|
||||
#include <asm/hardware/ssp.h>
|
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|
||||
#define TIMEOUT 100000
|
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|
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static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
||||
{
|
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unsigned int status = Ser4SSSR;
|
||||
|
|
@ -47,18 +49,27 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|||
* The caller is expected to perform the necessary locking.
|
||||
*
|
||||
* Returns:
|
||||
* %-ETIMEDOUT timeout occurred (for future)
|
||||
* %-ETIMEDOUT timeout occurred
|
||||
* 0 success
|
||||
*/
|
||||
int ssp_write_word(u16 data)
|
||||
{
|
||||
while (!(Ser4SSSR & SSSR_TNF))
|
||||
int timeout = TIMEOUT;
|
||||
|
||||
while (!(Ser4SSSR & SSSR_TNF)) {
|
||||
if (!--timeout)
|
||||
return -ETIMEDOUT;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
Ser4SSDR = data;
|
||||
|
||||
while (!(Ser4SSSR & SSSR_BSY))
|
||||
timeout = TIMEOUT;
|
||||
while (!(Ser4SSSR & SSSR_BSY)) {
|
||||
if (!--timeout)
|
||||
return -ETIMEDOUT;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -75,15 +86,22 @@ int ssp_write_word(u16 data)
|
|||
* The caller is expected to perform the necessary locking.
|
||||
*
|
||||
* Returns:
|
||||
* %-ETIMEDOUT timeout occurred (for future)
|
||||
* %-ETIMEDOUT timeout occurred
|
||||
* 16-bit data success
|
||||
*/
|
||||
int ssp_read_word(void)
|
||||
int ssp_read_word(u16 *data)
|
||||
{
|
||||
while (!(Ser4SSSR & SSSR_RNE))
|
||||
cpu_relax();
|
||||
int timeout = TIMEOUT;
|
||||
|
||||
return Ser4SSDR;
|
||||
while (!(Ser4SSSR & SSSR_RNE)) {
|
||||
if (!--timeout)
|
||||
return -ETIMEDOUT;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
*data = (u16)Ser4SSDR;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -93,14 +111,26 @@ int ssp_read_word(void)
|
|||
* is empty.
|
||||
*
|
||||
* The caller is expected to perform the necessary locking.
|
||||
*
|
||||
* Returns:
|
||||
* %-ETIMEDOUT timeout occurred
|
||||
* 0 success
|
||||
*/
|
||||
void ssp_flush(void)
|
||||
int ssp_flush(void)
|
||||
{
|
||||
int timeout = TIMEOUT * 2;
|
||||
|
||||
do {
|
||||
while (Ser4SSSR & SSSR_RNE) {
|
||||
if (!--timeout)
|
||||
return -ETIMEDOUT;
|
||||
(void) Ser4SSDR;
|
||||
}
|
||||
if (!--timeout)
|
||||
return -ETIMEDOUT;
|
||||
} while (Ser4SSSR & SSSR_BSY);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ config CPU_ARM710
|
|||
config CPU_ARM720T
|
||||
bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
|
||||
default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
|
||||
select CPU_32v4
|
||||
select CPU_32v4T
|
||||
select CPU_ABRT_LV4T
|
||||
select CPU_CACHE_V4
|
||||
select CPU_CACHE_VIVT
|
||||
|
|
@ -64,7 +64,7 @@ config CPU_ARM920T
|
|||
bool "Support ARM920T processor"
|
||||
depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
|
||||
default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
|
||||
select CPU_32v4
|
||||
select CPU_32v4T
|
||||
select CPU_ABRT_EV4T
|
||||
select CPU_CACHE_V4WT
|
||||
select CPU_CACHE_VIVT
|
||||
|
|
@ -85,7 +85,7 @@ config CPU_ARM922T
|
|||
bool "Support ARM922T processor" if ARCH_INTEGRATOR
|
||||
depends on ARCH_LH7A40X || ARCH_INTEGRATOR
|
||||
default y if ARCH_LH7A40X
|
||||
select CPU_32v4
|
||||
select CPU_32v4T
|
||||
select CPU_ABRT_EV4T
|
||||
select CPU_CACHE_V4WT
|
||||
select CPU_CACHE_VIVT
|
||||
|
|
@ -104,7 +104,7 @@ config CPU_ARM925T
|
|||
bool "Support ARM925T processor" if ARCH_OMAP1
|
||||
depends on ARCH_OMAP15XX
|
||||
default y if ARCH_OMAP15XX
|
||||
select CPU_32v4
|
||||
select CPU_32v4T
|
||||
select CPU_ABRT_EV4T
|
||||
select CPU_CACHE_V4WT
|
||||
select CPU_CACHE_VIVT
|
||||
|
|
@ -285,6 +285,11 @@ config CPU_32v4
|
|||
select TLS_REG_EMUL if SMP || !MMU
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
|
||||
config CPU_32v4T
|
||||
bool
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
|
||||
config CPU_32v5
|
||||
bool
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
|
|
|
|||
|
|
@ -353,3 +353,11 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
|
|||
* A special flag to tell the normalisation code not to normalise.
|
||||
*/
|
||||
#define VFP_NAN_FLAG 0x100
|
||||
|
||||
/*
|
||||
* A bit pattern used to indicate the initial (unset) value of the
|
||||
* exception mask, in case nothing handles an instruction. This
|
||||
* doesn't include the NAN flag, which get masked out before
|
||||
* we check for an error.
|
||||
*/
|
||||
#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
|
||||
|
|
|
|||
|
|
@ -465,7 +465,7 @@ static u32 vfp_double_fcvts(int sd, int unused, int dm, u32 fpscr)
|
|||
*/
|
||||
if (tm & (VFP_INFINITY|VFP_NAN)) {
|
||||
vsd.exponent = 255;
|
||||
if (tm & VFP_NAN)
|
||||
if (tm == VFP_QNAN)
|
||||
vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN;
|
||||
goto pack_nan;
|
||||
} else if (tm & VFP_ZERO)
|
||||
|
|
@ -1127,7 +1127,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
|
|||
{
|
||||
u32 op = inst & FOP_MASK;
|
||||
u32 exceptions = 0;
|
||||
unsigned int dd = vfp_get_dd(inst);
|
||||
unsigned int dest;
|
||||
unsigned int dn = vfp_get_dn(inst);
|
||||
unsigned int dm = vfp_get_dm(inst);
|
||||
unsigned int vecitr, veclen, vecstride;
|
||||
|
|
@ -1136,11 +1136,21 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
|
|||
veclen = fpscr & FPSCR_LENGTH_MASK;
|
||||
vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
|
||||
|
||||
/*
|
||||
* fcvtds takes an sN register number as destination, not dN.
|
||||
* It also always operates on scalars.
|
||||
*/
|
||||
if ((inst & FEXT_MASK) == FEXT_FCVT) {
|
||||
veclen = 0;
|
||||
dest = vfp_get_sd(inst);
|
||||
} else
|
||||
dest = vfp_get_dd(inst);
|
||||
|
||||
/*
|
||||
* If destination bank is zero, vector length is always '1'.
|
||||
* ARM DDI0100F C5.1.3, C5.3.2.
|
||||
*/
|
||||
if (FREG_BANK(dd) == 0)
|
||||
if (FREG_BANK(dest) == 0)
|
||||
veclen = 0;
|
||||
|
||||
pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
|
||||
|
|
@ -1153,16 +1163,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
|
|||
for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
|
||||
u32 except;
|
||||
|
||||
if (op == FOP_EXT)
|
||||
if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
|
||||
pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT,
|
||||
dest, dn, dm);
|
||||
else if (op == FOP_EXT)
|
||||
pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT,
|
||||
dd, dn, dm);
|
||||
dest, dn, dm);
|
||||
else
|
||||
pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT,
|
||||
dd, dn, FOP_TO_IDX(op), dm);
|
||||
dest, dn, FOP_TO_IDX(op), dm);
|
||||
|
||||
except = fop(dd, dn, dm, fpscr);
|
||||
except = fop(dest, dn, dm, fpscr);
|
||||
pr_debug("VFP: itr%d: exceptions=%08x\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT, except);
|
||||
|
||||
|
|
@ -1180,7 +1194,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
|
|||
* we encounter an exception. We continue.
|
||||
*/
|
||||
|
||||
dd = FREG_BANK(dd) + ((FREG_IDX(dd) + vecstride) & 6);
|
||||
dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);
|
||||
dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);
|
||||
if (FREG_BANK(dm) != 0)
|
||||
dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6);
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
|
|||
|
||||
pr_debug("VFP: raising exceptions %08x\n", exceptions);
|
||||
|
||||
if (exceptions == (u32)-1) {
|
||||
if (exceptions == VFP_EXCEPTION_ERROR) {
|
||||
vfp_panic("unhandled bounce");
|
||||
vfp_raise_sigfpe(0, regs);
|
||||
return;
|
||||
|
|
@ -170,7 +170,7 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_
|
|||
*/
|
||||
static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
|
||||
{
|
||||
u32 exceptions = (u32)-1;
|
||||
u32 exceptions = VFP_EXCEPTION_ERROR;
|
||||
|
||||
pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
|
||||
|
||||
|
|
|
|||
|
|
@ -506,7 +506,7 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr)
|
|||
*/
|
||||
if (tm & (VFP_INFINITY|VFP_NAN)) {
|
||||
vdd.exponent = 2047;
|
||||
if (tm & VFP_NAN)
|
||||
if (tm == VFP_QNAN)
|
||||
vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN;
|
||||
goto pack_nan;
|
||||
} else if (tm & VFP_ZERO)
|
||||
|
|
@ -514,10 +514,6 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr)
|
|||
else
|
||||
vdd.exponent = vsm.exponent + (1023 - 127);
|
||||
|
||||
/*
|
||||
* Technically, if bit 0 of dd is set, this is an invalid
|
||||
* instruction. However, we ignore this for efficiency.
|
||||
*/
|
||||
return vfp_double_normaliseround(dd, &vdd, fpscr, exceptions, "fcvtd");
|
||||
|
||||
pack_nan:
|
||||
|
|
@ -1174,7 +1170,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
|
|||
{
|
||||
u32 op = inst & FOP_MASK;
|
||||
u32 exceptions = 0;
|
||||
unsigned int sd = vfp_get_sd(inst);
|
||||
unsigned int dest;
|
||||
unsigned int sn = vfp_get_sn(inst);
|
||||
unsigned int sm = vfp_get_sm(inst);
|
||||
unsigned int vecitr, veclen, vecstride;
|
||||
|
|
@ -1183,11 +1179,23 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
|
|||
veclen = fpscr & FPSCR_LENGTH_MASK;
|
||||
vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);
|
||||
|
||||
/*
|
||||
* fcvtsd takes a dN register number as destination, not sN.
|
||||
* Technically, if bit 0 of dd is set, this is an invalid
|
||||
* instruction. However, we ignore this for efficiency.
|
||||
* It also only operates on scalars.
|
||||
*/
|
||||
if ((inst & FEXT_MASK) == FEXT_FCVT) {
|
||||
veclen = 0;
|
||||
dest = vfp_get_dd(inst);
|
||||
} else
|
||||
dest = vfp_get_sd(inst);
|
||||
|
||||
/*
|
||||
* If destination bank is zero, vector length is always '1'.
|
||||
* ARM DDI0100F C5.1.3, C5.3.2.
|
||||
*/
|
||||
if (FREG_BANK(sd) == 0)
|
||||
if (FREG_BANK(dest) == 0)
|
||||
veclen = 0;
|
||||
|
||||
pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
|
||||
|
|
@ -1201,15 +1209,18 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
|
|||
s32 m = vfp_get_float(sm);
|
||||
u32 except;
|
||||
|
||||
if (op == FOP_EXT)
|
||||
if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
|
||||
pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
|
||||
else if (op == FOP_EXT)
|
||||
pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT, sd, sn, sm, m);
|
||||
vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
|
||||
else
|
||||
pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT, sd, sn,
|
||||
vecitr >> FPSCR_LENGTH_BIT, dest, sn,
|
||||
FOP_TO_IDX(op), sm, m);
|
||||
|
||||
except = fop(sd, sn, m, fpscr);
|
||||
except = fop(dest, sn, m, fpscr);
|
||||
pr_debug("VFP: itr%d: exceptions=%08x\n",
|
||||
vecitr >> FPSCR_LENGTH_BIT, except);
|
||||
|
||||
|
|
@ -1227,7 +1238,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
|
|||
* we encounter an exception. We continue.
|
||||
*/
|
||||
|
||||
sd = FREG_BANK(sd) + ((FREG_IDX(sd) + vecstride) & 7);
|
||||
dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);
|
||||
sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);
|
||||
if (FREG_BANK(sm) != 0)
|
||||
sm = FREG_BANK(sm) + ((FREG_IDX(sm) + vecstride) & 7);
|
||||
|
|
|
|||
|
|
@ -40,8 +40,8 @@ struct ssp_dev {
|
|||
};
|
||||
|
||||
int ssp_write_word(struct ssp_dev *dev, u32 data);
|
||||
int ssp_read_word(struct ssp_dev *dev);
|
||||
void ssp_flush(struct ssp_dev *dev);
|
||||
int ssp_read_word(struct ssp_dev *dev, u32 *data);
|
||||
int ssp_flush(struct ssp_dev *dev);
|
||||
void ssp_enable(struct ssp_dev *dev);
|
||||
void ssp_disable(struct ssp_dev *dev);
|
||||
void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ struct ssp_state {
|
|||
};
|
||||
|
||||
int ssp_write_word(u16 data);
|
||||
int ssp_read_word(void);
|
||||
void ssp_flush(void);
|
||||
int ssp_read_word(u16 *data);
|
||||
int ssp_flush(void);
|
||||
void ssp_enable(void);
|
||||
void ssp_disable(void);
|
||||
void ssp_save_state(struct ssp_state *ssp);
|
||||
|
|
|
|||
|
|
@ -291,5 +291,12 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
|
|||
*/
|
||||
#define xlate_dev_kmem_ptr(p) p
|
||||
|
||||
/*
|
||||
* Register ISA memory and port locations for glibc iopl/inb/outb
|
||||
* emulation.
|
||||
*/
|
||||
extern void register_isa_ports(unsigned int mmio, unsigned int io,
|
||||
unsigned int io_shift);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_ARM_IO_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue