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MLK-20222-1 soc: Update SCFW API 

Update SCFW API to the following commit:
"
    ("430d1e3646fbe75e339e18abf2330565eac906e0")
    Author: Chuck Cannon <chuck.cannon@nxp.com>
    Date:   Fri Nov 2 15:25:45 2018 -0500

    SCF-105: RN updates.
"

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
pull/10/head
Ranjani Vaidyanathan 2018-11-02 15:51:01 -05:00
parent 9f8cf447d1
commit 1c21a146dc
24 changed files with 3051 additions and 1976 deletions
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4
drivers/soc/imx/sc/main/ipc.c
View File

@ -54,7 +54,7 @@ EXPORT_SYMBOL(sc_pm_set_clock_rate);
/*--------------------------------------------------------------------------*/
/* RPC command/response */
/*--------------------------------------------------------------------------*/
void sc_call_rpc(sc_ipc_t handle, sc_rpc_msg_t *msg, bool no_resp)
void sc_call_rpc(sc_ipc_t handle, sc_rpc_msg_t *msg, sc_bool_t no_resp)
{
struct arm_smccc_res res;
@ -214,7 +214,7 @@ void sc_ipc_read(sc_ipc_t handle, void *data)
*
* This function will block if the outgoing buffer is full.
*/
void sc_ipc_write(sc_ipc_t handle, void *data)
void sc_ipc_write(sc_ipc_t handle, const void *data)
{
uint32_t *base;
uint8_t count = 0;

115
drivers/soc/imx/sc/main/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,8 +9,8 @@
* Header file for the RPC implementation.
*/
#ifndef _SC_RPC_H
#define _SC_RPC_H
#ifndef SC_RPC_H
#define SC_RPC_H
/* Includes */
@ -19,35 +19,69 @@
/* Defines */
#define SC_RPC_VERSION 1
#define SC_RPC_VERSION 1U
#define SC_RPC_MAX_MSG 8
#define SC_RPC_MAX_MSG 8U
#define RPC_VER(MSG) ((MSG)->version)
#define RPC_SIZE(MSG) ((MSG)->size)
#define RPC_SVC(MSG) ((MSG)->svc)
#define RPC_FUNC(MSG) ((MSG)->func)
#define RPC_R8(MSG) ((MSG)->func)
#define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4])
#define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2])
#define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)])
#define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4])
#define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2])
#define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)])
#define RPC_VER(MESG) ((MESG)->version)
#define RPC_SIZE(MESG) ((MESG)->size)
#define RPC_SVC(MESG) ((MESG)->svc)
#define RPC_FUNC(MESG) ((MESG)->func)
#define RPC_R8(MESG) ((MESG)->func)
#define RPC_I32(MESG, IDX) ((MESG)->DATA.i32[(IDX) / 4U])
#define RPC_I16(MESG, IDX) ((MESG)->DATA.i16[(IDX) / 2U])
#define RPC_I8(MESG, IDX) ((MESG)->DATA.i8[(IDX)])
#define RPC_U32(MESG, IDX) ((MESG)->DATA.u32[(IDX) / 4U])
#define RPC_U16(MESG, IDX) ((MESG)->DATA.u16[(IDX) / 2U])
#define RPC_U8(MESG, IDX) ((MESG)->DATA.u8[(IDX)])
#define SC_RPC_SVC_UNKNOWN 0U
#define SC_RPC_SVC_RETURN 1U
#define SC_RPC_SVC_PM 2U
#define SC_RPC_SVC_RM 3U
#define SC_RPC_SVC_TIMER 5U
#define SC_RPC_SVC_PAD 6U
#define SC_RPC_SVC_MISC 7U
#define SC_RPC_SVC_IRQ 8U
#define SC_RPC_SVC_ABORT 9U
#define SC_RPC_ASYNC_STATE_RD_START 0U
#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U
#define SC_RPC_ASYNC_STATE_RD_DONE 2U
#define SC_RPC_ASYNC_STATE_WR_START 3U
#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U
#define SC_RPC_ASYNC_STATE_WR_DONE 5U
#define SC_RPC_MU_GIR_SVC 0x1U
#define SC_RPC_MU_GIR_DBG 0x8U
#define I8(X) ((int8_t) (X))
#define I16(X) ((int16_t) (X))
#define I32(X) ((int32_t) (X))
#define I64(X) ((int64_t) (X))
#define U8(X) ((uint8_t) (X))
#define U16(X) ((uint16_t) (X))
#define U32(X) ((uint32_t) (X))
#define U64(X) ((uint64_t) (X))
#define PTR_I8(X) ((int8_t *) (X))
#define PTR_I16(X) ((int16_t *) (X))
#define PTR_I32(X) ((int32_t *) (X))
#define PTR_I64(X) ((int64_t *) (X))
#define PTR_U8(X) ((uint8_t *) (X))
#define PTR_U16(X) ((uint16_t *) (X))
#define PTR_U32(X) ((uint32_t *) (X))
#define PTR_U64(X) ((uint64_t *) (X))
#define U2B(X) (((X) != 0U) ? SC_TRUE : SC_FALSE)
#define U2B32(X) (((X) != 0UL) ? SC_TRUE : SC_FALSE)
#define B2U8(X) (((X) != SC_FALSE) ? U8(0x01U) : U8(0x00U))
#define B2U16(X) (((X) != SC_FALSE) ? U16(0x01U) : U16(0x00U))
#define B2U32(X) (((X) != SC_FALSE) ? U32(0x01U) : U32(0x00U))
/* Types */
typedef enum sc_rpc_svc_e {
SC_RPC_SVC_UNKNOWN = 0,
SC_RPC_SVC_RETURN = 1,
SC_RPC_SVC_PM = 2,
SC_RPC_SVC_RM = 3,
SC_RPC_SVC_TIMER = 5,
SC_RPC_SVC_PAD = 6,
SC_RPC_SVC_MISC = 7,
SC_RPC_SVC_IRQ = 8,
SC_RPC_SVC_ABORT = 9
} sc_rpc_svc_t;
typedef uint8_t sc_rpc_svc_t;
typedef struct sc_rpc_msg_s {
uint8_t version;
@ -55,23 +89,16 @@ typedef struct sc_rpc_msg_s {
uint8_t svc;
uint8_t func;
union {
int32_t i32[(SC_RPC_MAX_MSG - 1)];
int16_t i16[(SC_RPC_MAX_MSG - 1) * 2];
int8_t i8[(SC_RPC_MAX_MSG - 1) * 4];
uint32_t u32[(SC_RPC_MAX_MSG - 1)];
uint16_t u16[(SC_RPC_MAX_MSG - 1) * 2];
uint8_t u8[(SC_RPC_MAX_MSG - 1) * 4];
int32_t i32[(SC_RPC_MAX_MSG - 1U)];
int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U];
int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U];
uint32_t u32[(SC_RPC_MAX_MSG - 1U)];
uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U];
uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U];
} DATA;
} sc_rpc_msg_t;
typedef enum sc_rpc_async_state_e {
SC_RPC_ASYNC_STATE_RD_START = 0,
SC_RPC_ASYNC_STATE_RD_ACTIVE = 1,
SC_RPC_ASYNC_STATE_RD_DONE = 2,
SC_RPC_ASYNC_STATE_WR_START = 3,
SC_RPC_ASYNC_STATE_WR_ACTIVE = 4,
SC_RPC_ASYNC_STATE_WR_DONE = 5,
} sc_rpc_async_state_t;
typedef uint8_t sc_rpc_async_state_t;
typedef struct sc_rpc_async_msg_s {
sc_rpc_async_state_t state;
@ -90,10 +117,10 @@ typedef struct sc_rpc_async_msg_s {
* @param[in,out] msg handle to a message
* @param[in] no_resp response flag
*
* If \a no_resp is false then this function waits for a response
* If \a no_resp is SC_FALSE then this function waits for a response
* and returns the result in \a msg.
*/
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp);
void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp);
/*!
* This is an internal function to dispath an RPC call that has
@ -121,4 +148,4 @@ void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg);
*/
void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_RPC_H */
#endif /* SC_RPC_H */

32
drivers/soc/imx/sc/svc/irq/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,23 +12,23 @@
* @{
*/
#ifndef _SC_IRQ_RPC_H
#define _SC_IRQ_RPC_H
#ifndef SC_IRQ_RPC_H
#define SC_IRQ_RPC_H
/* Includes */
/* Defines */
/* Types */
/*!
* This type is used to indicate RPC IRQ function calls.
* @name Defines for RPC IRQ function calls
*/
typedef enum irq_func_e {
IRQ_FUNC_UNKNOWN = 0, /* Unknown function */
IRQ_FUNC_ENABLE = 1, /* Index for irq_enable() RPC call */
IRQ_FUNC_STATUS = 2, /* Index for irq_status() RPC call */
} irq_func_t;
/*@{*/
#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */
#define IRQ_FUNC_ENABLE 1U /* Index for irq_enable() RPC call */
#define IRQ_FUNC_STATUS 2U /* Index for irq_status() RPC call */
/*@}*/
/* Types */
/* Functions */
@ -40,14 +40,6 @@ typedef enum irq_func_e {
*/
void irq_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an IRQ RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void irq_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_IRQ_RPC_H */
#endif /* SC_IRQ_RPC_H */
/**@}*/

34
drivers/soc/imx/sc/svc/irq/rpc_clnt.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -28,21 +28,21 @@
/* Local Functions */
sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_irq_group_t group, uint32_t mask, bool enable)
sc_irq_group_t group, uint32_t mask, sc_bool_t enable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_IRQ;
RPC_FUNC(&msg) = (uint8_t)IRQ_FUNC_ENABLE;
RPC_U32(&msg, 0) = mask;
RPC_U16(&msg, 4) = resource;
RPC_U8(&msg, 6) = group;
RPC_U8(&msg, 7) = (uint8_t)enable;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ);
RPC_FUNC(&msg) = U8(IRQ_FUNC_ENABLE);
RPC_U32(&msg, 0U) = U32(mask);
RPC_U16(&msg, 4U) = U16(resource);
RPC_U8(&msg, 6U) = U8(group);
RPC_U8(&msg, 7U) = B2U8(enable);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -55,16 +55,16 @@ sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_IRQ;
RPC_FUNC(&msg) = (uint8_t)IRQ_FUNC_STATUS;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ);
RPC_FUNC(&msg) = U8(IRQ_FUNC_STATUS);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(group);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (status != NULL) {
*status = RPC_U32(&msg, 0);
*status = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);

80
drivers/soc/imx/sc/svc/misc/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,40 +12,54 @@
* @{
*/
#ifndef _SC_MISC_RPC_H
#define _SC_MISC_RPC_H
#ifndef SC_MISC_RPC_H
#define SC_MISC_RPC_H
/* Includes */
/* Defines */
/* Types */
/*!
* This type is used to indicate RPC MISC function calls.
* @name Defines for RPC MISC function calls
*/
typedef enum misc_func_e {
MISC_FUNC_UNKNOWN = 0, /* Unknown function */
MISC_FUNC_SET_CONTROL = 1, /* Index for misc_set_control() RPC call */
MISC_FUNC_GET_CONTROL = 2, /* Index for misc_get_control() RPC call */
MISC_FUNC_SET_MAX_DMA_GROUP = 4, /* Index for misc_set_max_dma_group() RPC call */
MISC_FUNC_SET_DMA_GROUP = 5, /* Index for misc_set_dma_group() RPC call */
MISC_FUNC_SECO_IMAGE_LOAD = 8, /* Index for misc_seco_image_load() RPC call */
MISC_FUNC_SECO_AUTHENTICATE = 9, /* Index for misc_seco_authenticate() RPC call */
MISC_FUNC_DEBUG_OUT = 10, /* Index for misc_debug_out() RPC call */
MISC_FUNC_WAVEFORM_CAPTURE = 6, /* Index for misc_waveform_capture() RPC call */
MISC_FUNC_BUILD_INFO = 15, /* Index for misc_build_info() RPC call */
MISC_FUNC_UNIQUE_ID = 19, /* Index for misc_unique_id() RPC call */
MISC_FUNC_SET_ARI = 3, /* Index for misc_set_ari() RPC call */
MISC_FUNC_BOOT_STATUS = 7, /* Index for misc_boot_status() RPC call */
MISC_FUNC_BOOT_DONE = 14, /* Index for misc_boot_done() RPC call */
MISC_FUNC_OTP_FUSE_READ = 11, /* Index for misc_otp_fuse_read() RPC call */
MISC_FUNC_OTP_FUSE_WRITE = 17, /* Index for misc_otp_fuse_write() RPC call */
MISC_FUNC_SET_TEMP = 12, /* Index for misc_set_temp() RPC call */
MISC_FUNC_GET_TEMP = 13, /* Index for misc_get_temp() RPC call */
MISC_FUNC_GET_BOOT_DEV = 16, /* Index for misc_get_boot_dev() RPC call */
MISC_FUNC_GET_BUTTON_STATUS = 18, /* Index for misc_get_button_status() RPC call */
} misc_func_t;
/*@{*/
#define MISC_FUNC_UNKNOWN 0 /* Unknown function */
#define MISC_FUNC_SET_CONTROL 1U /* Index for misc_set_control() RPC call */
#define MISC_FUNC_GET_CONTROL 2U /* Index for misc_get_control() RPC call */
#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /* Index for misc_set_max_dma_group() RPC call */
#define MISC_FUNC_SET_DMA_GROUP 5U /* Index for misc_set_dma_group() RPC call */
#define MISC_FUNC_SECO_IMAGE_LOAD 8U /* Index for misc_seco_image_load() RPC call */
#define MISC_FUNC_SECO_AUTHENTICATE 9U /* Index for misc_seco_authenticate() RPC call */
#define MISC_FUNC_SECO_FUSE_WRITE 20U /* Index for misc_seco_fuse_write() RPC call */
#define MISC_FUNC_SECO_ENABLE_DEBUG 21U /* Index for misc_seco_enable_debug() RPC call */
#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U /* Index for misc_seco_forward_lifecycle() RPC call */
#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U /* Index for misc_seco_return_lifecycle() RPC call */
#define MISC_FUNC_SECO_BUILD_INFO 24U /* Index for misc_seco_build_info() RPC call */
#define MISC_FUNC_SECO_CHIP_INFO 25U /* Index for misc_seco_chip_info() RPC call */
#define MISC_FUNC_SECO_ATTEST_MODE 27U /* Index for misc_seco_attest_mode() RPC call */
#define MISC_FUNC_SECO_ATTEST 28U /* Index for misc_seco_attest() RPC call */
#define MISC_FUNC_SECO_GET_ATTEST_PKEY 31U /* Index for misc_seco_get_attest_pkey() RPC call */
#define MISC_FUNC_SECO_GET_ATTEST_SIGN 29U /* Index for misc_seco_get_attest_sign() RPC call */
#define MISC_FUNC_SECO_ATTEST_VERIFY 30U /* Index for misc_seco_attest_verify() RPC call */
#define MISC_FUNC_SECO_COMMIT 32U /* Index for misc_seco_commit() RPC call */
#define MISC_FUNC_DEBUG_OUT 10U /* Index for misc_debug_out() RPC call */
#define MISC_FUNC_WAVEFORM_CAPTURE 6U /* Index for misc_waveform_capture() RPC call */
#define MISC_FUNC_BUILD_INFO 15U /* Index for misc_build_info() RPC call */
#define MISC_FUNC_UNIQUE_ID 19U /* Index for misc_unique_id() RPC call */
#define MISC_FUNC_SET_ARI 3U /* Index for misc_set_ari() RPC call */
#define MISC_FUNC_BOOT_STATUS 7U /* Index for misc_boot_status() RPC call */
#define MISC_FUNC_BOOT_DONE 14U /* Index for misc_boot_done() RPC call */
#define MISC_FUNC_OTP_FUSE_READ 11U /* Index for misc_otp_fuse_read() RPC call */
#define MISC_FUNC_OTP_FUSE_WRITE 17U /* Index for misc_otp_fuse_write() RPC call */
#define MISC_FUNC_SET_TEMP 12U /* Index for misc_set_temp() RPC call */
#define MISC_FUNC_GET_TEMP 13U /* Index for misc_get_temp() RPC call */
#define MISC_FUNC_GET_BOOT_DEV 16U /* Index for misc_get_boot_dev() RPC call */
#define MISC_FUNC_GET_BOOT_TYPE 33U /* Index for misc_get_boot_type() RPC call */
#define MISC_FUNC_GET_BUTTON_STATUS 18U /* Index for misc_get_button_status() RPC call */
#define MISC_FUNC_ROMPATCH_CHECKSUM 26U /* Index for misc_rompatch_checksum() RPC call */
/*@}*/
/* Types */
/* Functions */
@ -57,14 +71,6 @@ typedef enum misc_func_e {
*/
void misc_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an MISC RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void misc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_MISC_RPC_H */
#endif /* SC_MISC_RPC_H */
/**@}*/

529
drivers/soc/imx/sc/svc/misc/rpc_clnt.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -34,14 +34,14 @@ sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_CONTROL;
RPC_U32(&msg, 0) = ctrl;
RPC_U32(&msg, 4) = val;
RPC_U16(&msg, 8) = resource;
RPC_SIZE(&msg) = 4;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SET_CONTROL);
RPC_U32(&msg, 0U) = U32(ctrl);
RPC_U32(&msg, 4U) = U32(val);
RPC_U16(&msg, 8U) = U16(resource);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -54,16 +54,16 @@ sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_CONTROL;
RPC_U32(&msg, 0) = ctrl;
RPC_U16(&msg, 4) = resource;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_GET_CONTROL);
RPC_U32(&msg, 0U) = U32(ctrl);
RPC_U16(&msg, 4U) = U16(resource);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (val != NULL) {
*val = RPC_U32(&msg, 0);
*val = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
@ -77,13 +77,13 @@ sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_MAX_DMA_GROUP;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = max;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SET_MAX_DMA_GROUP);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(max);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -96,86 +96,323 @@ sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_DMA_GROUP;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = group;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SET_DMA_GROUP);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(group);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, uint32_t addr_src,
uint32_t addr_dst, uint32_t len, bool fw)
sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
sc_faddr_t addr_dst, uint32_t len,
sc_bool_t fw)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_IMAGE_LOAD;
RPC_U32(&msg, 0) = addr_src;
RPC_U32(&msg, 4) = addr_dst;
RPC_U32(&msg, 8) = len;
RPC_U8(&msg, 12) = (uint8_t)fw;
RPC_SIZE(&msg) = 5;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_IMAGE_LOAD);
RPC_U32(&msg, 0U) = U32(addr_src >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr_src);
RPC_U32(&msg, 8U) = U32(addr_dst >> 32ULL);
RPC_U32(&msg, 12U) = U32(addr_dst);
RPC_U32(&msg, 16U) = U32(len);
RPC_U8(&msg, 20U) = B2U8(fw);
RPC_SIZE(&msg) = 7U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
sc_misc_seco_auth_cmd_t cmd,
uint32_t addr_meta)
sc_misc_seco_auth_cmd_t cmd, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SECO_AUTHENTICATE;
RPC_U32(&msg, 0) = addr_meta;
RPC_U8(&msg, 4) = cmd;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_AUTHENTICATE);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_U8(&msg, 8U) = U8(cmd);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_FUSE_WRITE);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ENABLE_DEBUG);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_FORWARD_LIFECYCLE);
RPC_U32(&msg, 0U) = U32(change);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_RETURN_LIFECYCLE);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_BUILD_INFO);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (version != NULL) {
*version = RPC_U32(&msg, 0U);
}
if (commit != NULL) {
*commit = RPC_U32(&msg, 4U);
}
return;
}
sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
uint16_t *monotonic, uint32_t *uid_l,
uint32_t *uid_h)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_CHIP_INFO);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (uid_l != NULL) {
*uid_l = RPC_U32(&msg, 0U);
}
if (uid_h != NULL) {
*uid_h = RPC_U32(&msg, 4U);
}
if (lc != NULL) {
*lc = RPC_U16(&msg, 8U);
}
if (monotonic != NULL) {
*monotonic = RPC_U16(&msg, 10U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST_MODE);
RPC_U32(&msg, 0U) = U32(mode);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST);
RPC_U32(&msg, 0U) = U32(nonce >> 32ULL);
RPC_U32(&msg, 4U) = U32(nonce);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_ATTEST_PKEY);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_GET_ATTEST_SIGN);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_ATTEST_VERIFY);
RPC_U32(&msg, 0U) = U32(addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SECO_COMMIT);
RPC_U32(&msg, 0U) = *PTR_U32(info);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
*info = RPC_U32(&msg, 0U);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_DEBUG_OUT;
RPC_U8(&msg, 0) = ch;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_DEBUG_OUT);
RPC_U8(&msg, 0U) = U8(ch);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
return;
}
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable)
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_WAVEFORM_CAPTURE;
RPC_U8(&msg, 0) = (uint8_t)enable;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_WAVEFORM_CAPTURE);
RPC_U8(&msg, 0U) = B2U8(enable);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -186,18 +423,18 @@ void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BUILD_INFO;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_BUILD_INFO);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (build != NULL) {
*build = RPC_U32(&msg, 0);
*build = RPC_U32(&msg, 0U);
}
if (commit != NULL) {
*commit = RPC_U32(&msg, 4);
*commit = RPC_U32(&msg, 4U);
}
return;
@ -208,39 +445,39 @@ void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_UNIQUE_ID;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_UNIQUE_ID);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (id_l != NULL) {
*id_l = RPC_U32(&msg, 0);
*id_l = RPC_U32(&msg, 0U);
}
if (id_h != NULL) {
*id_h = RPC_U32(&msg, 4);
*id_h = RPC_U32(&msg, 4U);
}
return;
}
sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rsrc_t resource_mst, uint16_t ari, bool enable)
sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_ARI;
RPC_U16(&msg, 0) = resource;
RPC_U16(&msg, 2) = resource_mst;
RPC_U16(&msg, 4) = ari;
RPC_U8(&msg, 6) = (uint8_t)enable;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SET_ARI);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U16(&msg, 2U) = U16(resource_mst);
RPC_U16(&msg, 4U) = U16(ari);
RPC_U8(&msg, 6U) = B2U8(enable);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -251,12 +488,12 @@ void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BOOT_STATUS;
RPC_U8(&msg, 0) = status;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_STATUS);
RPC_U8(&msg, 0U) = U8(status);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, true);
sc_call_rpc(ipc, &msg, SC_TRUE);
return;
}
@ -267,12 +504,12 @@ sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_BOOT_DONE;
RPC_U16(&msg, 0) = cpu;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_DONE);
RPC_U16(&msg, 0U) = U16(cpu);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -284,15 +521,15 @@ sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_OTP_FUSE_READ;
RPC_U32(&msg, 0) = word;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_READ);
RPC_U32(&msg, 0U) = U32(word);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (val != NULL) {
*val = RPC_U32(&msg, 0);
*val = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
@ -305,13 +542,13 @@ sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_OTP_FUSE_WRITE;
RPC_U32(&msg, 0) = word;
RPC_U32(&msg, 4) = val;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_WRITE);
RPC_U32(&msg, 0U) = U32(word);
RPC_U32(&msg, 4U) = U32(val);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -324,15 +561,15 @@ sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_SET_TEMP;
RPC_U16(&msg, 0) = resource;
RPC_I16(&msg, 2) = celsius;
RPC_U8(&msg, 4) = temp;
RPC_I8(&msg, 5) = tenths;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_SET_TEMP);
RPC_U16(&msg, 0U) = U16(resource);
RPC_I16(&msg, 2U) = I16(celsius);
RPC_U8(&msg, 4U) = U8(temp);
RPC_I8(&msg, 5U) = I8(tenths);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -346,21 +583,21 @@ sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_TEMP;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = temp;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_GET_TEMP);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(temp);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (celsius != NULL) {
*celsius = RPC_I16(&msg, 0);
*celsius = RPC_I16(&msg, 0U);
}
result = RPC_R8(&msg);
if (tenths != NULL) {
*tenths = RPC_I8(&msg, 2);
*tenths = RPC_I8(&msg, 2U);
}
return (sc_err_t)result;
@ -371,35 +608,75 @@ void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_BOOT_DEV;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_DEV);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (dev != NULL) {
*dev = RPC_U16(&msg, 0);
*dev = RPC_U16(&msg, 0U);
}
return;
}
void sc_misc_get_button_status(sc_ipc_t ipc, bool *status)
sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_TYPE);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (type != NULL) {
*type = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_MISC;
RPC_FUNC(&msg) = (uint8_t)MISC_FUNC_GET_BUTTON_STATUS;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BUTTON_STATUS);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (status != NULL) {
*status = RPC_U8(&msg, 0);
*status = U2B(RPC_U8(&msg, 0U));
}
return;
}
sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC);
RPC_FUNC(&msg) = U8(MISC_FUNC_ROMPATCH_CHECKSUM);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
if (checksum != NULL) {
*checksum = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
/**@}*/

60
drivers/soc/imx/sc/svc/pad/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,37 +12,37 @@
* @{
*/
#ifndef _SC_PAD_RPC_H
#define _SC_PAD_RPC_H
#ifndef SC_PAD_RPC_H
#define SC_PAD_RPC_H
/* Includes */
/* Defines */
/* Types */
/*!
* This type is used to indicate RPC PAD function calls.
* @name Defines for RPC PAD function calls
*/
typedef enum pad_func_e {
PAD_FUNC_UNKNOWN = 0, /* Unknown function */
PAD_FUNC_SET_MUX = 1, /* Index for pad_set_mux() RPC call */
PAD_FUNC_GET_MUX = 6, /* Index for pad_get_mux() RPC call */
PAD_FUNC_SET_GP = 2, /* Index for pad_set_gp() RPC call */
PAD_FUNC_GET_GP = 7, /* Index for pad_get_gp() RPC call */
PAD_FUNC_SET_WAKEUP = 4, /* Index for pad_set_wakeup() RPC call */
PAD_FUNC_GET_WAKEUP = 9, /* Index for pad_get_wakeup() RPC call */
PAD_FUNC_SET_ALL = 5, /* Index for pad_set_all() RPC call */
PAD_FUNC_GET_ALL = 10, /* Index for pad_get_all() RPC call */
PAD_FUNC_SET = 15, /* Index for pad_set() RPC call */
PAD_FUNC_GET = 16, /* Index for pad_get() RPC call */
PAD_FUNC_SET_GP_28FDSOI = 11, /* Index for pad_set_gp_28fdsoi() RPC call */
PAD_FUNC_GET_GP_28FDSOI = 12, /* Index for pad_get_gp_28fdsoi() RPC call */
PAD_FUNC_SET_GP_28FDSOI_HSIC = 3, /* Index for pad_set_gp_28fdsoi_hsic() RPC call */
PAD_FUNC_GET_GP_28FDSOI_HSIC = 8, /* Index for pad_get_gp_28fdsoi_hsic() RPC call */
PAD_FUNC_SET_GP_28FDSOI_COMP = 13, /* Index for pad_set_gp_28fdsoi_comp() RPC call */
PAD_FUNC_GET_GP_28FDSOI_COMP = 14, /* Index for pad_get_gp_28fdsoi_comp() RPC call */
} pad_func_t;
/*@{*/
#define PAD_FUNC_UNKNOWN 0 /* Unknown function */
#define PAD_FUNC_SET_MUX 1U /* Index for pad_set_mux() RPC call */
#define PAD_FUNC_GET_MUX 6U /* Index for pad_get_mux() RPC call */
#define PAD_FUNC_SET_GP 2U /* Index for pad_set_gp() RPC call */
#define PAD_FUNC_GET_GP 7U /* Index for pad_get_gp() RPC call */
#define PAD_FUNC_SET_WAKEUP 4U /* Index for pad_set_wakeup() RPC call */
#define PAD_FUNC_GET_WAKEUP 9U /* Index for pad_get_wakeup() RPC call */
#define PAD_FUNC_SET_ALL 5U /* Index for pad_set_all() RPC call */
#define PAD_FUNC_GET_ALL 10U /* Index for pad_get_all() RPC call */
#define PAD_FUNC_SET 15U /* Index for pad_set() RPC call */
#define PAD_FUNC_GET 16U /* Index for pad_get() RPC call */
#define PAD_FUNC_SET_GP_28FDSOI 11U /* Index for pad_set_gp_28fdsoi() RPC call */
#define PAD_FUNC_GET_GP_28FDSOI 12U /* Index for pad_get_gp_28fdsoi() RPC call */
#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /* Index for pad_set_gp_28fdsoi_hsic() RPC call */
#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /* Index for pad_get_gp_28fdsoi_hsic() RPC call */
#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /* Index for pad_set_gp_28fdsoi_comp() RPC call */
#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /* Index for pad_get_gp_28fdsoi_comp() RPC call */
/*@}*/
/* Types */
/* Functions */
@ -54,14 +54,6 @@ typedef enum pad_func_e {
*/
void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an PAD RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_PAD_RPC_H */
#endif /* SC_PAD_RPC_H */
/**@}*/

284
drivers/soc/imx/sc/svc/pad/rpc_clnt.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -34,15 +34,15 @@ sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_MUX;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = mux;
RPC_U8(&msg, 3) = config;
RPC_U8(&msg, 4) = iso;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_MUX);
RPC_U16(&msg, 0U) = U16(pad);
RPC_U8(&msg, 2U) = U8(mux);
RPC_U8(&msg, 3U) = U8(config);
RPC_U8(&msg, 4U) = U8(iso);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -56,24 +56,24 @@ sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_MUX;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_MUX);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mux != NULL) {
*mux = RPC_U8(&msg, 0);
*mux = RPC_U8(&msg, 0U);
}
if (config != NULL) {
*config = RPC_U8(&msg, 1);
*config = RPC_U8(&msg, 1U);
}
if (iso != NULL) {
*iso = RPC_U8(&msg, 2);
*iso = RPC_U8(&msg, 2U);
}
return (sc_err_t)result;
@ -85,13 +85,13 @@ sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP;
RPC_U32(&msg, 0) = ctrl;
RPC_U16(&msg, 4) = pad;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP);
RPC_U32(&msg, 0U) = U32(ctrl);
RPC_U16(&msg, 4U) = U16(pad);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -103,15 +103,15 @@ sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (ctrl != NULL) {
*ctrl = RPC_U32(&msg, 0);
*ctrl = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
@ -124,13 +124,13 @@ sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_WAKEUP;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = wakeup;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_WAKEUP);
RPC_U16(&msg, 0U) = U16(pad);
RPC_U8(&msg, 2U) = U8(wakeup);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -142,16 +142,16 @@ sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_WAKEUP;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_WAKEUP);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (wakeup != NULL) {
*wakeup = RPC_U8(&msg, 0);
*wakeup = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -165,17 +165,17 @@ sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_ALL;
RPC_U32(&msg, 0) = ctrl;
RPC_U16(&msg, 4) = pad;
RPC_U8(&msg, 6) = mux;
RPC_U8(&msg, 7) = config;
RPC_U8(&msg, 8) = iso;
RPC_U8(&msg, 9) = wakeup;
RPC_SIZE(&msg) = 4;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_ALL);
RPC_U32(&msg, 0U) = U32(ctrl);
RPC_U16(&msg, 4U) = U16(pad);
RPC_U8(&msg, 6U) = U8(mux);
RPC_U8(&msg, 7U) = U8(config);
RPC_U8(&msg, 8U) = U8(iso);
RPC_U8(&msg, 9U) = U8(wakeup);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -189,32 +189,32 @@ sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_ALL;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_ALL);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (ctrl != NULL) {
*ctrl = RPC_U32(&msg, 0);
*ctrl = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
if (mux != NULL) {
*mux = RPC_U8(&msg, 4);
*mux = RPC_U8(&msg, 4U);
}
if (config != NULL) {
*config = RPC_U8(&msg, 5);
*config = RPC_U8(&msg, 5U);
}
if (iso != NULL) {
*iso = RPC_U8(&msg, 6);
*iso = RPC_U8(&msg, 6U);
}
if (wakeup != NULL) {
*wakeup = RPC_U8(&msg, 7);
*wakeup = RPC_U8(&msg, 7U);
}
return (sc_err_t)result;
@ -226,13 +226,13 @@ sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET;
RPC_U32(&msg, 0) = val;
RPC_U16(&msg, 4) = pad;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET);
RPC_U32(&msg, 0U) = U32(val);
RPC_U16(&msg, 4U) = U16(pad);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -244,15 +244,15 @@ sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (val != NULL) {
*val = RPC_U32(&msg, 0);
*val = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
@ -266,14 +266,14 @@ sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = dse;
RPC_U8(&msg, 3) = ps;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI);
RPC_U16(&msg, 0U) = U16(pad);
RPC_U8(&msg, 2U) = U8(dse);
RPC_U8(&msg, 3U) = U8(ps);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -287,164 +287,164 @@ sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (dse != NULL) {
*dse = RPC_U8(&msg, 0);
*dse = RPC_U8(&msg, 0U);
}
if (ps != NULL) {
*ps = RPC_U8(&msg, 1);
*ps = RPC_U8(&msg, 1U);
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, bool hys,
sc_pad_28fdsoi_pus_t pus, bool pke,
bool pue)
sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
sc_bool_t pue)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_HSIC;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = dse;
RPC_U8(&msg, 3) = pus;
RPC_U8(&msg, 4) = (uint8_t)hys;
RPC_U8(&msg, 5) = (uint8_t)pke;
RPC_U8(&msg, 6) = (uint8_t)pue;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_HSIC);
RPC_U16(&msg, 0U) = U16(pad);
RPC_U8(&msg, 2U) = U8(dse);
RPC_U8(&msg, 3U) = U8(pus);
RPC_U8(&msg, 4U) = B2U8(hys);
RPC_U8(&msg, 5U) = B2U8(pke);
RPC_U8(&msg, 6U) = B2U8(pue);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse, bool *hys,
sc_pad_28fdsoi_pus_t *pus, bool *pke,
bool *pue)
sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
sc_bool_t *pue)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_HSIC;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_HSIC);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (dse != NULL) {
*dse = RPC_U8(&msg, 0);
*dse = RPC_U8(&msg, 0U);
}
if (pus != NULL) {
*pus = RPC_U8(&msg, 1);
*pus = RPC_U8(&msg, 1U);
}
if (hys != NULL) {
*hys = RPC_U8(&msg, 2);
*hys = U2B(RPC_U8(&msg, 2U));
}
if (pke != NULL) {
*pke = RPC_U8(&msg, 3);
*pke = U2B(RPC_U8(&msg, 3U));
}
if (pue != NULL) {
*pue = RPC_U8(&msg, 4);
*pue = U2B(RPC_U8(&msg, 4U));
}
return (sc_err_t)result;
}
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t compen, bool fastfrz,
uint8_t compen, sc_bool_t fastfrz,
uint8_t rasrcp, uint8_t rasrcn,
bool nasrc_sel, bool psw_ovr)
sc_bool_t nasrc_sel, sc_bool_t psw_ovr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_SET_GP_28FDSOI_COMP;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = compen;
RPC_U8(&msg, 3) = rasrcp;
RPC_U8(&msg, 4) = rasrcn;
RPC_U8(&msg, 5) = (uint8_t)fastfrz;
RPC_U8(&msg, 6) = (uint8_t)nasrc_sel;
RPC_U8(&msg, 7) = (uint8_t)psw_ovr;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_COMP);
RPC_U16(&msg, 0U) = U16(pad);
RPC_U8(&msg, 2U) = U8(compen);
RPC_U8(&msg, 3U) = U8(rasrcp);
RPC_U8(&msg, 4U) = U8(rasrcn);
RPC_U8(&msg, 5U) = B2U8(fastfrz);
RPC_U8(&msg, 6U) = B2U8(nasrc_sel);
RPC_U8(&msg, 7U) = B2U8(psw_ovr);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *compen, bool *fastfrz,
uint8_t *compen, sc_bool_t *fastfrz,
uint8_t *rasrcp, uint8_t *rasrcn,
bool *nasrc_sel, bool *compok,
uint8_t *nasrc, bool *psw_ovr)
sc_bool_t *nasrc_sel, sc_bool_t *compok,
uint8_t *nasrc, sc_bool_t *psw_ovr)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PAD;
RPC_FUNC(&msg) = (uint8_t)PAD_FUNC_GET_GP_28FDSOI_COMP;
RPC_U16(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD);
RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_COMP);
RPC_U16(&msg, 0U) = U16(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (compen != NULL) {
*compen = RPC_U8(&msg, 0);
*compen = RPC_U8(&msg, 0U);
}
if (rasrcp != NULL) {
*rasrcp = RPC_U8(&msg, 1);
*rasrcp = RPC_U8(&msg, 1U);
}
if (rasrcn != NULL) {
*rasrcn = RPC_U8(&msg, 2);
*rasrcn = RPC_U8(&msg, 2U);
}
if (nasrc != NULL) {
*nasrc = RPC_U8(&msg, 3);
*nasrc = RPC_U8(&msg, 3U);
}
if (fastfrz != NULL) {
*fastfrz = RPC_U8(&msg, 4);
*fastfrz = U2B(RPC_U8(&msg, 4U));
}
if (nasrc_sel != NULL) {
*nasrc_sel = RPC_U8(&msg, 5);
*nasrc_sel = U2B(RPC_U8(&msg, 5U));
}
if (compok != NULL) {
*compok = RPC_U8(&msg, 6);
*compok = U2B(RPC_U8(&msg, 6U));
}
if (psw_ovr != NULL) {
*psw_ovr = RPC_U8(&msg, 7);
*psw_ovr = U2B(RPC_U8(&msg, 7U));
}
return (sc_err_t)result;

70
drivers/soc/imx/sc/svc/pm/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,40 +12,44 @@
* @{
*/
#ifndef _SC_PM_RPC_H
#define _SC_PM_RPC_H
#ifndef SC_PM_RPC_H
#define SC_PM_RPC_H
/* Includes */
/* Defines */
/* Types */
/*!
* This type is used to indicate RPC PM function calls.
* @name Defines for RPC PM function calls
*/
typedef enum pm_func_e {
PM_FUNC_UNKNOWN = 0, /* Unknown function */
PM_FUNC_SET_SYS_POWER_MODE = 19, /* Index for pm_set_sys_power_mode() RPC call */
PM_FUNC_SET_PARTITION_POWER_MODE = 1, /* Index for pm_set_partition_power_mode() RPC call */
PM_FUNC_GET_SYS_POWER_MODE = 2, /* Index for pm_get_sys_power_mode() RPC call */
PM_FUNC_SET_RESOURCE_POWER_MODE = 3, /* Index for pm_set_resource_power_mode() RPC call */
PM_FUNC_GET_RESOURCE_POWER_MODE = 4, /* Index for pm_get_resource_power_mode() RPC call */
PM_FUNC_REQ_LOW_POWER_MODE = 16, /* Index for pm_req_low_power_mode() RPC call */
PM_FUNC_SET_CPU_RESUME_ADDR = 17, /* Index for pm_set_cpu_resume_addr() RPC call */
PM_FUNC_REQ_SYS_IF_POWER_MODE = 18, /* Index for pm_req_sys_if_power_mode() RPC call */
PM_FUNC_SET_CLOCK_RATE = 5, /* Index for pm_set_clock_rate() RPC call */
PM_FUNC_GET_CLOCK_RATE = 6, /* Index for pm_get_clock_rate() RPC call */
PM_FUNC_CLOCK_ENABLE = 7, /* Index for pm_clock_enable() RPC call */
PM_FUNC_SET_CLOCK_PARENT = 14, /* Index for pm_set_clock_parent() RPC call */
PM_FUNC_GET_CLOCK_PARENT = 15, /* Index for pm_get_clock_parent() RPC call */
PM_FUNC_RESET = 13, /* Index for pm_reset() RPC call */
PM_FUNC_RESET_REASON = 10, /* Index for pm_reset_reason() RPC call */
PM_FUNC_BOOT = 8, /* Index for pm_boot() RPC call */
PM_FUNC_REBOOT = 9, /* Index for pm_reboot() RPC call */
PM_FUNC_REBOOT_PARTITION = 12, /* Index for pm_reboot_partition() RPC call */
PM_FUNC_CPU_START = 11, /* Index for pm_cpu_start() RPC call */
} pm_func_t;
/*@{*/
#define PM_FUNC_UNKNOWN 0 /* Unknown function */
#define PM_FUNC_SET_SYS_POWER_MODE 19U /* Index for pm_set_sys_power_mode() RPC call */
#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /* Index for pm_set_partition_power_mode() RPC call */
#define PM_FUNC_GET_SYS_POWER_MODE 2U /* Index for pm_get_sys_power_mode() RPC call */
#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /* Index for pm_set_resource_power_mode() RPC call */
#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U /* Index for pm_set_resource_power_mode_all() RPC call */
#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /* Index for pm_get_resource_power_mode() RPC call */
#define PM_FUNC_REQ_LOW_POWER_MODE 16U /* Index for pm_req_low_power_mode() RPC call */
#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /* Index for pm_req_cpu_low_power_mode() RPC call */
#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /* Index for pm_set_cpu_resume_addr() RPC call */
#define PM_FUNC_SET_CPU_RESUME 21U /* Index for pm_set_cpu_resume() RPC call */
#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /* Index for pm_req_sys_if_power_mode() RPC call */
#define PM_FUNC_SET_CLOCK_RATE 5U /* Index for pm_set_clock_rate() RPC call */
#define PM_FUNC_GET_CLOCK_RATE 6U /* Index for pm_get_clock_rate() RPC call */
#define PM_FUNC_CLOCK_ENABLE 7U /* Index for pm_clock_enable() RPC call */
#define PM_FUNC_SET_CLOCK_PARENT 14U /* Index for pm_set_clock_parent() RPC call */
#define PM_FUNC_GET_CLOCK_PARENT 15U /* Index for pm_get_clock_parent() RPC call */
#define PM_FUNC_RESET 13U /* Index for pm_reset() RPC call */
#define PM_FUNC_RESET_REASON 10U /* Index for pm_reset_reason() RPC call */
#define PM_FUNC_BOOT 8U /* Index for pm_boot() RPC call */
#define PM_FUNC_REBOOT 9U /* Index for pm_reboot() RPC call */
#define PM_FUNC_REBOOT_PARTITION 12U /* Index for pm_reboot_partition() RPC call */
#define PM_FUNC_CPU_START 11U /* Index for pm_cpu_start() RPC call */
#define PM_FUNC_CPU_RESET 23U /* Index for pm_cpu_reset() RPC call */
/*@}*/
/* Types */
/* Functions */
@ -57,14 +61,6 @@ typedef enum pm_func_e {
*/
void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an PM RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_PM_RPC_H */
#endif /* SC_PM_RPC_H */
/**@}*/

339
drivers/soc/imx/sc/svc/pm/rpc_clnt.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -33,12 +33,12 @@ sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_SYS_POWER_MODE;
RPC_U8(&msg, 0) = mode;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_SYS_POWER_MODE);
RPC_U8(&msg, 0U) = U8(mode);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -51,13 +51,13 @@ sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_PARTITION_POWER_MODE;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = mode;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_PARTITION_POWER_MODE);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(mode);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -70,16 +70,16 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_SYS_POWER_MODE;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_GET_SYS_POWER_MODE);
RPC_U8(&msg, 0U) = U8(pt);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mode != NULL) {
*mode = RPC_U8(&msg, 0);
*mode = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -92,13 +92,35 @@ sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_RESOURCE_POWER_MODE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = mode;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(mode);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc,
sc_rm_pt_t pt,
sc_pm_power_mode_t mode,
sc_rsrc_t exclude)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE_ALL);
RPC_U16(&msg, 0U) = U16(exclude);
RPC_U8(&msg, 2U) = U8(pt);
RPC_U8(&msg, 3U) = U8(mode);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -111,16 +133,16 @@ sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_RESOURCE_POWER_MODE;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESOURCE_POWER_MODE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mode != NULL) {
*mode = RPC_U8(&msg, 0);
*mode = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -133,13 +155,34 @@ sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_LOW_POWER_MODE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = mode;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_REQ_LOW_POWER_MODE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(mode);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode,
sc_pm_wake_src_t wake_src)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_REQ_CPU_LOW_POWER_MODE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(mode);
RPC_U8(&msg, 3U) = U8(wake_src);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -152,14 +195,35 @@ sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CPU_RESUME_ADDR;
RPC_U32(&msg, 0) = (uint32_t)(address >> 32u);
RPC_U32(&msg, 4) = (uint32_t)address;
RPC_U16(&msg, 8) = resource;
RPC_SIZE(&msg) = 4;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME_ADDR);
RPC_U32(&msg, 0U) = U32(address >> 32ULL);
RPC_U32(&msg, 4U) = U32(address);
RPC_U16(&msg, 8U) = U16(resource);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t isPrimary, sc_faddr_t address)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME);
RPC_U32(&msg, 0U) = U32(address >> 32ULL);
RPC_U32(&msg, 4U) = U32(address);
RPC_U16(&msg, 8U) = U16(resource);
RPC_U8(&msg, 10U) = B2U8(isPrimary);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -174,15 +238,15 @@ sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REQ_SYS_IF_POWER_MODE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = sys_if;
RPC_U8(&msg, 3) = hpm;
RPC_U8(&msg, 4) = lpm;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_REQ_SYS_IF_POWER_MODE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(sys_if);
RPC_U8(&msg, 3U) = U8(hpm);
RPC_U8(&msg, 4U) = U8(lpm);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -195,16 +259,16 @@ sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_RATE;
RPC_U32(&msg, 0) = *rate;
RPC_U16(&msg, 4) = resource;
RPC_U8(&msg, 6) = clk;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_RATE);
RPC_U32(&msg, 0U) = *PTR_U32(rate);
RPC_U16(&msg, 4U) = U16(resource);
RPC_U8(&msg, 6U) = U8(clk);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
*rate = RPC_U32(&msg, 0);
*rate = RPC_U32(&msg, 0U);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
@ -216,16 +280,16 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_RATE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_RATE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(clk);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (rate != NULL) {
*rate = RPC_U32(&msg, 0);
*rate = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
@ -233,21 +297,21 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
}
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, bool enable, bool autog)
sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CLOCK_ENABLE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_U8(&msg, 3) = (uint8_t)enable;
RPC_U8(&msg, 4) = (uint8_t)autog;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_CLOCK_ENABLE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(clk);
RPC_U8(&msg, 3U) = B2U8(enable);
RPC_U8(&msg, 4U) = B2U8(autog);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -260,14 +324,14 @@ sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_SET_CLOCK_PARENT;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_U8(&msg, 3) = parent;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_PARENT);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(clk);
RPC_U8(&msg, 3U) = U8(parent);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -280,17 +344,17 @@ sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_GET_CLOCK_PARENT;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = clk;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_PARENT);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(clk);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (parent != NULL) {
*parent = RPC_U8(&msg, 0);
*parent = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -302,12 +366,12 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET;
RPC_U8(&msg, 0) = type;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_RESET);
RPC_U8(&msg, 0U) = U8(type);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -319,15 +383,15 @@ sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_RESET_REASON;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_RESET_REASON);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (reason != NULL) {
*reason = RPC_U8(&msg, 0);
*reason = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -341,17 +405,17 @@ sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_BOOT;
RPC_U32(&msg, 0) = (uint32_t)(boot_addr >> 32u);
RPC_U32(&msg, 4) = (uint32_t)boot_addr;
RPC_U16(&msg, 8) = resource_cpu;
RPC_U16(&msg, 10) = resource_mu;
RPC_U16(&msg, 12) = resource_dev;
RPC_U8(&msg, 14) = pt;
RPC_SIZE(&msg) = 5;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_BOOT);
RPC_U32(&msg, 0U) = U32(boot_addr >> 32ULL);
RPC_U32(&msg, 4U) = U32(boot_addr);
RPC_U16(&msg, 8U) = U16(resource_cpu);
RPC_U16(&msg, 10U) = U16(resource_mu);
RPC_U16(&msg, 12U) = U16(resource_dev);
RPC_U8(&msg, 14U) = U8(pt);
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -362,12 +426,12 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT;
RPC_U8(&msg, 0) = type;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT);
RPC_U8(&msg, 0U) = U8(type);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, true);
sc_call_rpc(ipc, &msg, SC_TRUE);
return;
}
@ -379,37 +443,54 @@ sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_REBOOT_PARTITION;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = type;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_PARTITION);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(type);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_PM;
RPC_FUNC(&msg) = (uint8_t)PM_FUNC_CPU_START;
RPC_U32(&msg, 0) = (uint32_t)(address >> 32u);
RPC_U32(&msg, 4) = (uint32_t)address;
RPC_U16(&msg, 8) = resource;
RPC_U8(&msg, 10) = (uint8_t)enable;
RPC_SIZE(&msg) = 4;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_CPU_START);
RPC_U32(&msg, 0U) = U32(address >> 32ULL);
RPC_U32(&msg, 4U) = U32(address);
RPC_U16(&msg, 8U) = U16(resource);
RPC_U8(&msg, 10U) = B2U8(enable);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address)
{
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_PM);
RPC_FUNC(&msg) = U8(PM_FUNC_CPU_RESET);
RPC_U32(&msg, 0U) = U32(address >> 32ULL);
RPC_U32(&msg, 4U) = U32(address);
RPC_U16(&msg, 8U) = U16(resource);
RPC_SIZE(&msg) = 4U;
sc_call_rpc(ipc, &msg, SC_TRUE);
return;
}
/**@}*/

91
drivers/soc/imx/sc/svc/rm/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,52 +12,53 @@
* @{
*/
#ifndef _SC_RM_RPC_H
#define _SC_RM_RPC_H
#ifndef SC_RM_RPC_H
#define SC_RM_RPC_H
/* Includes */
/* Defines */
/* Types */
/*!
* This type is used to indicate RPC RM function calls.
* @name Defines for RPC RM function calls
*/
typedef enum rm_func_e {
RM_FUNC_UNKNOWN = 0, /* Unknown function */
RM_FUNC_PARTITION_ALLOC = 1, /* Index for rm_partition_alloc() RPC call */
RM_FUNC_SET_CONFIDENTIAL = 31, /* Index for rm_set_confidential() RPC call */
RM_FUNC_PARTITION_FREE = 2, /* Index for rm_partition_free() RPC call */
RM_FUNC_GET_DID = 26, /* Index for rm_get_did() RPC call */
RM_FUNC_PARTITION_STATIC = 3, /* Index for rm_partition_static() RPC call */
RM_FUNC_PARTITION_LOCK = 4, /* Index for rm_partition_lock() RPC call */
RM_FUNC_GET_PARTITION = 5, /* Index for rm_get_partition() RPC call */
RM_FUNC_SET_PARENT = 6, /* Index for rm_set_parent() RPC call */
RM_FUNC_MOVE_ALL = 7, /* Index for rm_move_all() RPC call */
RM_FUNC_ASSIGN_RESOURCE = 8, /* Index for rm_assign_resource() RPC call */
RM_FUNC_SET_RESOURCE_MOVABLE = 9, /* Index for rm_set_resource_movable() RPC call */
RM_FUNC_SET_SUBSYS_RSRC_MOVABLE = 28, /* Index for rm_set_subsys_rsrc_movable() RPC call */
RM_FUNC_SET_MASTER_ATTRIBUTES = 10, /* Index for rm_set_master_attributes() RPC call */
RM_FUNC_SET_MASTER_SID = 11, /* Index for rm_set_master_sid() RPC call */
RM_FUNC_SET_PERIPHERAL_PERMISSIONS = 12, /* Index for rm_set_peripheral_permissions() RPC call */
RM_FUNC_IS_RESOURCE_OWNED = 13, /* Index for rm_is_resource_owned() RPC call */
RM_FUNC_IS_RESOURCE_MASTER = 14, /* Index for rm_is_resource_master() RPC call */
RM_FUNC_IS_RESOURCE_PERIPHERAL = 15, /* Index for rm_is_resource_peripheral() RPC call */
RM_FUNC_GET_RESOURCE_INFO = 16, /* Index for rm_get_resource_info() RPC call */
RM_FUNC_MEMREG_ALLOC = 17, /* Index for rm_memreg_alloc() RPC call */
RM_FUNC_MEMREG_SPLIT = 29, /* Index for rm_memreg_split() RPC call */
RM_FUNC_MEMREG_FREE = 18, /* Index for rm_memreg_free() RPC call */
RM_FUNC_FIND_MEMREG = 30, /* Index for rm_find_memreg() RPC call */
RM_FUNC_ASSIGN_MEMREG = 19, /* Index for rm_assign_memreg() RPC call */
RM_FUNC_SET_MEMREG_PERMISSIONS = 20, /* Index for rm_set_memreg_permissions() RPC call */
RM_FUNC_IS_MEMREG_OWNED = 21, /* Index for rm_is_memreg_owned() RPC call */
RM_FUNC_GET_MEMREG_INFO = 22, /* Index for rm_get_memreg_info() RPC call */
RM_FUNC_ASSIGN_PAD = 23, /* Index for rm_assign_pad() RPC call */
RM_FUNC_SET_PAD_MOVABLE = 24, /* Index for rm_set_pad_movable() RPC call */
RM_FUNC_IS_PAD_OWNED = 25, /* Index for rm_is_pad_owned() RPC call */
RM_FUNC_DUMP = 27, /* Index for rm_dump() RPC call */
} rm_func_t;
/*@{*/
#define RM_FUNC_UNKNOWN 0 /* Unknown function */
#define RM_FUNC_PARTITION_ALLOC 1U /* Index for rm_partition_alloc() RPC call */
#define RM_FUNC_SET_CONFIDENTIAL 31U /* Index for rm_set_confidential() RPC call */
#define RM_FUNC_PARTITION_FREE 2U /* Index for rm_partition_free() RPC call */
#define RM_FUNC_GET_DID 26U /* Index for rm_get_did() RPC call */
#define RM_FUNC_PARTITION_STATIC 3U /* Index for rm_partition_static() RPC call */
#define RM_FUNC_PARTITION_LOCK 4U /* Index for rm_partition_lock() RPC call */
#define RM_FUNC_GET_PARTITION 5U /* Index for rm_get_partition() RPC call */
#define RM_FUNC_SET_PARENT 6U /* Index for rm_set_parent() RPC call */
#define RM_FUNC_MOVE_ALL 7U /* Index for rm_move_all() RPC call */
#define RM_FUNC_ASSIGN_RESOURCE 8U /* Index for rm_assign_resource() RPC call */
#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /* Index for rm_set_resource_movable() RPC call */
#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /* Index for rm_set_subsys_rsrc_movable() RPC call */
#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /* Index for rm_set_master_attributes() RPC call */
#define RM_FUNC_SET_MASTER_SID 11U /* Index for rm_set_master_sid() RPC call */
#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /* Index for rm_set_peripheral_permissions() RPC call */
#define RM_FUNC_IS_RESOURCE_OWNED 13U /* Index for rm_is_resource_owned() RPC call */
#define RM_FUNC_IS_RESOURCE_MASTER 14U /* Index for rm_is_resource_master() RPC call */
#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /* Index for rm_is_resource_peripheral() RPC call */
#define RM_FUNC_GET_RESOURCE_INFO 16U /* Index for rm_get_resource_info() RPC call */
#define RM_FUNC_MEMREG_ALLOC 17U /* Index for rm_memreg_alloc() RPC call */
#define RM_FUNC_MEMREG_SPLIT 29U /* Index for rm_memreg_split() RPC call */
#define RM_FUNC_MEMREG_FRAG 32U /* Index for rm_memreg_frag() RPC call */
#define RM_FUNC_MEMREG_FREE 18U /* Index for rm_memreg_free() RPC call */
#define RM_FUNC_FIND_MEMREG 30U /* Index for rm_find_memreg() RPC call */
#define RM_FUNC_ASSIGN_MEMREG 19U /* Index for rm_assign_memreg() RPC call */
#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /* Index for rm_set_memreg_permissions() RPC call */
#define RM_FUNC_IS_MEMREG_OWNED 21U /* Index for rm_is_memreg_owned() RPC call */
#define RM_FUNC_GET_MEMREG_INFO 22U /* Index for rm_get_memreg_info() RPC call */
#define RM_FUNC_ASSIGN_PAD 23U /* Index for rm_assign_pad() RPC call */
#define RM_FUNC_SET_PAD_MOVABLE 24U /* Index for rm_set_pad_movable() RPC call */
#define RM_FUNC_IS_PAD_OWNED 25U /* Index for rm_is_pad_owned() RPC call */
#define RM_FUNC_DUMP 27U /* Index for rm_dump() RPC call */
/*@}*/
/* Types */
/* Functions */
@ -69,14 +70,6 @@ typedef enum rm_func_e {
*/
void rm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an RM RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void rm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_RM_RPC_H */
#endif /* SC_RM_RPC_H */
/**@}*/

477
drivers/soc/imx/sc/svc/rm/rpc_clnt.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -26,46 +26,46 @@
/* Local Functions */
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
bool isolated, bool restricted, bool grant,
bool coherent)
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
sc_bool_t isolated, sc_bool_t restricted,
sc_bool_t grant, sc_bool_t coherent)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_ALLOC;
RPC_U8(&msg, 0) = (uint8_t)secure;
RPC_U8(&msg, 1) = (uint8_t)isolated;
RPC_U8(&msg, 2) = (uint8_t)restricted;
RPC_U8(&msg, 3) = (uint8_t)grant;
RPC_U8(&msg, 4) = (uint8_t)coherent;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_ALLOC);
RPC_U8(&msg, 0U) = B2U8(secure);
RPC_U8(&msg, 1U) = B2U8(isolated);
RPC_U8(&msg, 2U) = B2U8(restricted);
RPC_U8(&msg, 3U) = B2U8(grant);
RPC_U8(&msg, 4U) = B2U8(coherent);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (pt != NULL) {
*pt = RPC_U8(&msg, 0);
*pt = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, bool retro)
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_CONFIDENTIAL;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = (uint8_t)retro;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_CONFIDENTIAL);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = B2U8(retro);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -77,12 +77,12 @@ sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_FREE;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_FREE);
RPC_U8(&msg, 0U) = U8(pt);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -94,11 +94,11 @@ sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_DID;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_GET_DID);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_rm_did_t) result;
@ -110,13 +110,13 @@ sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_STATIC;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = did;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_STATIC);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(did);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -128,12 +128,12 @@ sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_PARTITION_LOCK;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_LOCK);
RPC_U8(&msg, 0U) = U8(pt);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -145,15 +145,15 @@ sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_PARTITION;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_GET_PARTITION);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (pt != NULL) {
*pt = RPC_U8(&msg, 0);
*pt = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -165,34 +165,34 @@ sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PARENT;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = pt_parent;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_PARENT);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(pt_parent);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
bool move_rsrc, bool move_pads)
sc_bool_t move_rsrc, sc_bool_t move_pads)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MOVE_ALL;
RPC_U8(&msg, 0) = pt_src;
RPC_U8(&msg, 1) = pt_dst;
RPC_U8(&msg, 2) = (uint8_t)move_rsrc;
RPC_U8(&msg, 3) = (uint8_t)move_pads;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_MOVE_ALL);
RPC_U8(&msg, 0U) = U8(pt_src);
RPC_U8(&msg, 1U) = U8(pt_dst);
RPC_U8(&msg, 2U) = B2U8(move_rsrc);
RPC_U8(&msg, 3U) = B2U8(move_pads);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -204,52 +204,52 @@ sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_RESOURCE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = pt;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_RESOURCE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(pt);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
sc_rsrc_t resource_lst, bool movable)
sc_rsrc_t resource_lst, sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_RESOURCE_MOVABLE;
RPC_U16(&msg, 0) = resource_fst;
RPC_U16(&msg, 2) = resource_lst;
RPC_U8(&msg, 4) = (uint8_t)movable;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_RESOURCE_MOVABLE);
RPC_U16(&msg, 0U) = U16(resource_fst);
RPC_U16(&msg, 2U) = U16(resource_lst);
RPC_U8(&msg, 4U) = B2U8(movable);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
bool movable)
sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_SUBSYS_RSRC_MOVABLE;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = (uint8_t)movable;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_SUBSYS_RSRC_MOVABLE);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = B2U8(movable);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -257,21 +257,21 @@ sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_spa_t sa, sc_rm_spa_t pa,
bool smmu_bypass)
sc_bool_t smmu_bypass)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_ATTRIBUTES;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = sa;
RPC_U8(&msg, 3) = pa;
RPC_U8(&msg, 4) = (uint8_t)smmu_bypass;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_ATTRIBUTES);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(sa);
RPC_U8(&msg, 3U) = U8(pa);
RPC_U8(&msg, 4U) = B2U8(smmu_bypass);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -283,13 +283,13 @@ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MASTER_SID;
RPC_U16(&msg, 0) = resource;
RPC_U16(&msg, 2) = sid;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_SID);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U16(&msg, 2U) = U16(sid);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -302,68 +302,68 @@ sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PERIPHERAL_PERMISSIONS;
RPC_U16(&msg, 0) = resource;
RPC_U8(&msg, 2) = pt;
RPC_U8(&msg, 3) = perm;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_PERIPHERAL_PERMISSIONS);
RPC_U16(&msg, 0U) = U16(resource);
RPC_U8(&msg, 2U) = U8(pt);
RPC_U8(&msg, 3U) = U8(perm);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
sc_bool_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_OWNED;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_OWNED);
RPC_U16(&msg, 0U) = U16(resource);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (bool)result;
result = U2B(RPC_R8(&msg));
return result;
}
bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
sc_bool_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_MASTER;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_MASTER);
RPC_U16(&msg, 0U) = U16(resource);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (bool)result;
result = U2B(RPC_R8(&msg));
return result;
}
bool sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource)
{
sc_rpc_msg_t msg;
uint8_t result;
sc_bool_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_RESOURCE_PERIPHERAL;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_PERIPHERAL);
RPC_U16(&msg, 0U) = U16(resource);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (bool)result;
result = U2B(RPC_R8(&msg));
return result;
}
sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
@ -373,15 +373,15 @@ sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_RESOURCE_INFO;
RPC_U16(&msg, 0) = resource;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_INFO);
RPC_U16(&msg, 0U) = U16(resource);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (sid != NULL) {
*sid = RPC_U16(&msg, 0);
*sid = RPC_U16(&msg, 0U);
}
result = RPC_R8(&msg);
@ -395,19 +395,19 @@ sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_ALLOC;
RPC_U32(&msg, 0) = (uint32_t)(addr_start >> 32u);
RPC_U32(&msg, 4) = (uint32_t)addr_start;
RPC_U32(&msg, 8) = (uint32_t)(addr_end >> 32u);
RPC_U32(&msg, 12) = (uint32_t)addr_end;
RPC_SIZE(&msg) = 5;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_ALLOC);
RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr_start);
RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
RPC_U32(&msg, 12U) = U32(addr_end);
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr != NULL) {
*mr = RPC_U8(&msg, 0);
*mr = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -421,20 +421,45 @@ sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_SPLIT;
RPC_U32(&msg, 0) = (uint32_t)(addr_start >> 32u);
RPC_U32(&msg, 4) = (uint32_t)addr_start;
RPC_U32(&msg, 8) = (uint32_t)(addr_end >> 32u);
RPC_U32(&msg, 12) = (uint32_t)addr_end;
RPC_U8(&msg, 16) = mr;
RPC_SIZE(&msg) = 6;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_SPLIT);
RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr_start);
RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
RPC_U32(&msg, 12U) = U32(addr_end);
RPC_U8(&msg, 16U) = U8(mr);
RPC_SIZE(&msg) = 6U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr_ret != NULL) {
*mr_ret = RPC_U8(&msg, 0);
*mr_ret = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
}
sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret,
sc_faddr_t addr_start, sc_faddr_t addr_end)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FRAG);
RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr_start);
RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
RPC_U32(&msg, 12U) = U32(addr_end);
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr_ret != NULL) {
*mr_ret = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -446,12 +471,12 @@ sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_MEMREG_FREE;
RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FREE);
RPC_U8(&msg, 0U) = U8(mr);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -464,19 +489,19 @@ sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_FIND_MEMREG;
RPC_U32(&msg, 0) = (uint32_t)(addr_start >> 32u);
RPC_U32(&msg, 4) = (uint32_t)addr_start;
RPC_U32(&msg, 8) = (uint32_t)(addr_end >> 32u);
RPC_U32(&msg, 12) = (uint32_t)addr_end;
RPC_SIZE(&msg) = 5;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_FIND_MEMREG);
RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL);
RPC_U32(&msg, 4U) = U32(addr_start);
RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL);
RPC_U32(&msg, 12U) = U32(addr_end);
RPC_SIZE(&msg) = 5U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
if (mr != NULL) {
*mr = RPC_U8(&msg, 0);
*mr = RPC_U8(&msg, 0U);
}
return (sc_err_t)result;
@ -488,13 +513,13 @@ sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_MEMREG;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = mr;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_MEMREG);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(mr);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -507,34 +532,34 @@ sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_MEMREG_PERMISSIONS;
RPC_U8(&msg, 0) = mr;
RPC_U8(&msg, 1) = pt;
RPC_U8(&msg, 2) = perm;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_MEMREG_PERMISSIONS);
RPC_U8(&msg, 0U) = U8(mr);
RPC_U8(&msg, 1U) = U8(pt);
RPC_U8(&msg, 2U) = U8(perm);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
bool sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
{
sc_rpc_msg_t msg;
uint8_t result;
sc_bool_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_MEMREG_OWNED;
RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_IS_MEMREG_OWNED);
RPC_U8(&msg, 0U) = U8(mr);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (bool)result;
result = U2B(RPC_R8(&msg));
return result;
}
sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
@ -544,21 +569,21 @@ sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_GET_MEMREG_INFO;
RPC_U8(&msg, 0) = mr;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_GET_MEMREG_INFO);
RPC_U8(&msg, 0U) = U8(mr);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (addr_start != NULL) {
*addr_start =
((uint64_t) RPC_U32(&msg, 0) << 32u) | RPC_U32(&msg, 4);
((uint64_t) RPC_U32(&msg, 0U) << 32U) | RPC_U32(&msg, 4U);
}
if (addr_end != NULL) {
*addr_end =
((uint64_t) RPC_U32(&msg, 8) << 32u) | RPC_U32(&msg, 12);
((uint64_t) RPC_U32(&msg, 8U) << 32U) | RPC_U32(&msg, 12U);
}
result = RPC_R8(&msg);
@ -571,53 +596,53 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_ASSIGN_PAD;
RPC_U16(&msg, 0) = pad;
RPC_U8(&msg, 2) = pt;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_PAD);
RPC_U16(&msg, 0U) = U16(pad);
RPC_U8(&msg, 2U) = U8(pt);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
sc_pad_t pad_lst, bool movable)
sc_pad_t pad_lst, sc_bool_t movable)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_SET_PAD_MOVABLE;
RPC_U16(&msg, 0) = pad_fst;
RPC_U16(&msg, 2) = pad_lst;
RPC_U8(&msg, 4) = (uint8_t)movable;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_SET_PAD_MOVABLE);
RPC_U16(&msg, 0U) = U16(pad_fst);
RPC_U16(&msg, 2U) = U16(pad_lst);
RPC_U8(&msg, 4U) = B2U8(movable);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
bool sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
{
sc_rpc_msg_t msg;
uint8_t result;
sc_bool_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_IS_PAD_OWNED;
RPC_U8(&msg, 0) = pad;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_IS_PAD_OWNED);
RPC_U8(&msg, 0U) = U8(pad);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (bool)result;
result = U2B(RPC_R8(&msg));
return result;
}
void sc_rm_dump(sc_ipc_t ipc)
@ -625,11 +650,11 @@ void sc_rm_dump(sc_ipc_t ipc)
sc_rpc_msg_t msg;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_RM;
RPC_FUNC(&msg) = (uint8_t)RM_FUNC_DUMP;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_RM);
RPC_FUNC(&msg) = U8(RM_FUNC_DUMP);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
return;
}

59
drivers/soc/imx/sc/svc/timer/rpc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -12,34 +12,39 @@
* @{
*/
#ifndef _SC_TIMER_RPC_H
#define _SC_TIMER_RPC_H
#ifndef SC_TIMER_RPC_H
#define SC_TIMER_RPC_H
/* Includes */
/* Defines */
/* Types */
/*!
* This type is used to indicate RPC TIMER function calls.
* @name Defines for RPC TIMER function calls
*/
typedef enum timer_func_e {
TIMER_FUNC_UNKNOWN = 0, /* Unknown function */
TIMER_FUNC_SET_WDOG_TIMEOUT = 1, /* Index for timer_set_wdog_timeout() RPC call */
TIMER_FUNC_SET_WDOG_PRE_TIMEOUT = 12, /* Index for timer_set_wdog_pre_timeout() RPC call */
TIMER_FUNC_START_WDOG = 2, /* Index for timer_start_wdog() RPC call */
TIMER_FUNC_STOP_WDOG = 3, /* Index for timer_stop_wdog() RPC call */
TIMER_FUNC_PING_WDOG = 4, /* Index for timer_ping_wdog() RPC call */
TIMER_FUNC_GET_WDOG_STATUS = 5, /* Index for timer_get_wdog_status() RPC call */
TIMER_FUNC_PT_GET_WDOG_STATUS = 13, /* Index for timer_pt_get_wdog_status() RPC call */
TIMER_FUNC_SET_WDOG_ACTION = 10, /* Index for timer_set_wdog_action() RPC call */
TIMER_FUNC_SET_RTC_TIME = 6, /* Index for timer_set_rtc_time() RPC call */
TIMER_FUNC_GET_RTC_TIME = 7, /* Index for timer_get_rtc_time() RPC call */
TIMER_FUNC_GET_RTC_SEC1970 = 9, /* Index for timer_get_rtc_sec1970() RPC call */
TIMER_FUNC_SET_RTC_ALARM = 8, /* Index for timer_set_rtc_alarm() RPC call */
TIMER_FUNC_SET_RTC_CALB = 11, /* Index for timer_set_rtc_calb() RPC call */
} timer_func_t;
/*@{*/
#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for timer_set_wdog_timeout() RPC call */
#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for timer_set_wdog_pre_timeout() RPC call */
#define TIMER_FUNC_START_WDOG 2U /* Index for timer_start_wdog() RPC call */
#define TIMER_FUNC_STOP_WDOG 3U /* Index for timer_stop_wdog() RPC call */
#define TIMER_FUNC_PING_WDOG 4U /* Index for timer_ping_wdog() RPC call */
#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for timer_get_wdog_status() RPC call */
#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for timer_pt_get_wdog_status() RPC call */
#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for timer_set_wdog_action() RPC call */
#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for timer_set_rtc_time() RPC call */
#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for timer_get_rtc_time() RPC call */
#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for timer_get_rtc_sec1970() RPC call */
#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for timer_set_rtc_alarm() RPC call */
#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for timer_set_rtc_periodic_alarm() RPC call */
#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for timer_cancel_rtc_alarm() RPC call */
#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for timer_set_rtc_calb() RPC call */
#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for timer_set_sysctr_alarm() RPC call */
#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for timer_set_sysctr_periodic_alarm() RPC call */
#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for timer_cancel_sysctr_alarm() RPC call */
/*@}*/
/* Types */
/* Functions */
@ -51,14 +56,6 @@ typedef enum timer_func_e {
*/
void timer_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
/*!
* This function translates and dispatches an TIMER RPC request.
*
* @param[in] ipc IPC handle
* @param[in] msg pointer to RPC message
*/
void timer_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
#endif /* _SC_TIMER_RPC_H */
#endif /* SC_TIMER_RPC_H */
/**@}*/

260
drivers/soc/imx/sc/svc/timer/rpc_clnt.c
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -33,12 +33,12 @@ sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_TIMEOUT;
RPC_U32(&msg, 0) = timeout;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_TIMEOUT);
RPC_U32(&msg, 0U) = U32(timeout);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -51,29 +51,29 @@ sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_PRE_TIMEOUT;
RPC_U32(&msg, 0) = pre_timeout;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_PRE_TIMEOUT);
RPC_U32(&msg, 0U) = U32(pre_timeout);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, bool lock)
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_START_WDOG;
RPC_U8(&msg, 0) = (uint8_t)lock;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_START_WDOG);
RPC_U8(&msg, 0U) = B2U8(lock);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -85,11 +85,11 @@ sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_STOP_WDOG;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_STOP_WDOG);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -101,11 +101,11 @@ sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PING_WDOG;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_PING_WDOG);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -120,29 +120,30 @@ sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_WDOG_STATUS;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_WDOG_STATUS);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (timeout != NULL) {
*timeout = RPC_U32(&msg, 0);
*timeout = RPC_U32(&msg, 0U);
}
if (max_timeout != NULL) {
*max_timeout = RPC_U32(&msg, 4);
*max_timeout = RPC_U32(&msg, 4U);
}
if (remaining_time != NULL) {
*remaining_time = RPC_U32(&msg, 8);
*remaining_time = RPC_U32(&msg, 8U);
}
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_bool_t *enb,
sc_timer_wdog_time_t *timeout,
sc_timer_wdog_time_t *remaining_time)
{
@ -150,24 +151,24 @@ sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_PT_GET_WDOG_STATUS;
RPC_U8(&msg, 0) = pt;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_PT_GET_WDOG_STATUS);
RPC_U8(&msg, 0U) = U8(pt);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (timeout != NULL) {
*timeout = RPC_U32(&msg, 0);
*timeout = RPC_U32(&msg, 0U);
}
if (remaining_time != NULL) {
*remaining_time = RPC_U32(&msg, 4);
*remaining_time = RPC_U32(&msg, 4U);
}
result = RPC_R8(&msg);
if (enb != NULL) {
*enb = RPC_U8(&msg, 8);
*enb = U2B(RPC_U8(&msg, 8U));
}
return (sc_err_t)result;
@ -180,13 +181,13 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_WDOG_ACTION;
RPC_U8(&msg, 0) = pt;
RPC_U8(&msg, 1) = action;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_ACTION);
RPC_U8(&msg, 0U) = U8(pt);
RPC_U8(&msg, 1U) = U8(action);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -200,17 +201,17 @@ sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_TIME;
RPC_U16(&msg, 0) = year;
RPC_U8(&msg, 2) = mon;
RPC_U8(&msg, 3) = day;
RPC_U8(&msg, 4) = hour;
RPC_U8(&msg, 5) = min;
RPC_U8(&msg, 6) = sec;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_TIME);
RPC_U16(&msg, 0U) = U16(year);
RPC_U8(&msg, 2U) = U8(mon);
RPC_U8(&msg, 3U) = U8(day);
RPC_U8(&msg, 4U) = U8(hour);
RPC_U8(&msg, 5U) = U8(min);
RPC_U8(&msg, 6U) = U8(sec);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -224,35 +225,35 @@ sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_TIME;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_TIME);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (year != NULL) {
*year = RPC_U16(&msg, 0);
*year = RPC_U16(&msg, 0U);
}
result = RPC_R8(&msg);
if (mon != NULL) {
*mon = RPC_U8(&msg, 2);
*mon = RPC_U8(&msg, 2U);
}
if (day != NULL) {
*day = RPC_U8(&msg, 3);
*day = RPC_U8(&msg, 3U);
}
if (hour != NULL) {
*hour = RPC_U8(&msg, 4);
*hour = RPC_U8(&msg, 4U);
}
if (min != NULL) {
*min = RPC_U8(&msg, 5);
*min = RPC_U8(&msg, 5U);
}
if (sec != NULL) {
*sec = RPC_U8(&msg, 6);
*sec = RPC_U8(&msg, 6U);
}
return (sc_err_t)result;
@ -264,14 +265,14 @@ sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_GET_RTC_SEC1970;
RPC_SIZE(&msg) = 1;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_SEC1970);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
if (sec != NULL) {
*sec = RPC_U32(&msg, 0);
*sec = RPC_U32(&msg, 0U);
}
result = RPC_R8(&msg);
@ -286,17 +287,50 @@ sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_ALARM;
RPC_U16(&msg, 0) = year;
RPC_U8(&msg, 2) = mon;
RPC_U8(&msg, 3) = day;
RPC_U8(&msg, 4) = hour;
RPC_U8(&msg, 5) = min;
RPC_U8(&msg, 6) = sec;
RPC_SIZE(&msg) = 3;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_ALARM);
RPC_U16(&msg, 0U) = U16(year);
RPC_U8(&msg, 2U) = U8(mon);
RPC_U8(&msg, 3U) = U8(day);
RPC_U8(&msg, 4U) = U8(hour);
RPC_U8(&msg, 5U) = U8(min);
RPC_U8(&msg, 6U) = U8(sec);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_PERIODIC_ALARM);
RPC_U32(&msg, 0U) = U32(sec);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_RTC_ALARM);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
@ -308,12 +342,64 @@ sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count)
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = (uint8_t)SC_RPC_SVC_TIMER;
RPC_FUNC(&msg) = (uint8_t)TIMER_FUNC_SET_RTC_CALB;
RPC_I8(&msg, 0) = count;
RPC_SIZE(&msg) = 2;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_CALB);
RPC_I8(&msg, 0U) = I8(count);
RPC_SIZE(&msg) = 2U;
sc_call_rpc(ipc, &msg, false);
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_ALARM);
RPC_U32(&msg, 0U) = U32(ticks >> 32ULL);
RPC_U32(&msg, 4U) = U32(ticks);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM);
RPC_U32(&msg, 0U) = U32(ticks >> 32ULL);
RPC_U32(&msg, 4U) = U32(ticks);
RPC_SIZE(&msg) = 3U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;
}
sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc)
{
sc_rpc_msg_t msg;
uint8_t result;
RPC_VER(&msg) = SC_RPC_VERSION;
RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER);
RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_SYSCTR_ALARM);
RPC_SIZE(&msg) = 1U;
sc_call_rpc(ipc, &msg, SC_FALSE);
result = RPC_R8(&msg);
return (sc_err_t)result;

1
drivers/soc/imx/soc-imx8.c
View File

@ -24,6 +24,7 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <soc/imx8/sc/types.h>
#include <soc/imx8/sc/sci.h>
#include <soc/imx8/soc.h>
#include <soc/imx/revision.h>

5
include/soc/imx/fsl_sip.h
View File

@ -44,11 +44,6 @@
#define IMX8MQ_PD_MIPI_CSI2 9
#define IMX8MQ_PD_PCIE2 10
#define SC_TIMER_WDOG_ACTION_PARTITION 0 /*!< Reset partition */
#define SC_TIMER_WDOG_ACTION_WARM 1 /*!< Warm reset system */
#define SC_TIMER_WDOG_ACTION_COLD 2 /*!< Cold reset system */
#define SC_TIMER_WDOG_ACTION_BOARD 3 /*!< Reset board */
#define FSL_SIP_DDR_DVFS 0xc2000004
#define FSL_SIP_SRC 0xc2000005

11
include/soc/imx8/sc/ipc.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,8 +9,8 @@
* Header file for the IPC implementation.
*/
#ifndef _SC_IPC_H
#define _SC_IPC_H
#ifndef SC_IPC_H
#define SC_IPC_H
/* Includes */
@ -62,10 +62,9 @@ void sc_ipc_read(sc_ipc_t ipc, void *data);
*
* This function will block if the outgoing buffer is full.
*/
void sc_ipc_write(sc_ipc_t ipc, void *data);
void sc_ipc_write(sc_ipc_t ipc, const void *data);
int register_scu_notifier(struct notifier_block *nb);
int unregister_scu_notifier(struct notifier_block *nb);
#endif /* _SC_IPC_H */
#endif /* SC_IPC_H */

80
include/soc/imx8/sc/svc/irq/api.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -16,8 +16,8 @@
* @{
*/
#ifndef _SC_IRQ_API_H
#define _SC_IRQ_API_H
#ifndef SC_IRQ_API_H
#define SC_IRQ_API_H
/* Includes */
@ -25,66 +25,74 @@
/* Defines */
#define SC_IRQ_NUM_GROUP 4 /* Number of groups */
#define SC_IRQ_NUM_GROUP 5U /* Number of groups */
/*!
* @name Defines for sc_irq_group_t
*/
/*@{*/
#define SC_IRQ_GROUP_TEMP 0 /* Temp interrupts */
#define SC_IRQ_GROUP_WDOG 1 /* Watchdog interrupts */
#define SC_IRQ_GROUP_RTC 2 /* RTC interrupts */
#define SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */
#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */
#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */
#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */
#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */
#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */
/*@}*/
/*!
* @name Defines for sc_irq_temp_t
*/
/*@{*/
#define SC_IRQ_TEMP_HIGH (1 << 0) /* Temp alarm interrupt */
#define SC_IRQ_TEMP_CPU0_HIGH (1 << 1) /* CPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_CPU1_HIGH (1 << 2) /* CPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU0_HIGH (1 << 3) /* GPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU1_HIGH (1 << 4) /* GPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC0_HIGH (1 << 5) /* DRC0 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC1_HIGH (1 << 6) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_VPU_HIGH (1 << 7) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC0_HIGH (1 << 8) /* PMIC0 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC1_HIGH (1 << 9) /* PMIC1 temp alarm interrupt */
#define SC_IRQ_TEMP_LOW (1 << 10) /* Temp alarm interrupt */
#define SC_IRQ_TEMP_CPU0_LOW (1 << 11) /* CPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_CPU1_LOW (1 << 12) /* CPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU0_LOW (1 << 13) /* GPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU1_LOW (1 << 14) /* GPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC0_LOW (1 << 15) /* DRC0 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC1_LOW (1 << 16) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_VPU_LOW (1 << 17) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC0_LOW (1 << 18) /* PMIC0 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC1_LOW (1 << 19) /* PMIC1 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC2_HIGH (1 << 20) /* PMIC2 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC2_LOW (1 << 21) /* PMIC2 temp alarm interrupt */
#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */
#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */
#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */
#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */
#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */
#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */
#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */
/*@}*/
/*!
* @name Defines for sc_irq_wdog_t
*/
/*@{*/
#define SC_IRQ_WDOG (1 << 0) /* Watchdog interrupt */
#define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */
#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */
/*@}*/
/*!
* @name Defines for sc_irq_rtc_t
*/
/*@{*/
#define SC_IRQ_RTC (1 << 0) /* RTC interrupt */
#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */
/*@}*/
/*!
* @name Defines for sc_irq_wake_t
*/
/*@{*/
#define SC_IRQ_BUTTON (1 << 0) /* Button interrupt */
#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */
#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */
/*@}*/
/*!
* @name Defines for sc_irq_sysctr_t
*/
/*@{*/
#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */
/*@}*/
/* Types */
@ -132,7 +140,7 @@ typedef uint8_t sc_irq_wake_t;
* - SC_PARM if group invalid
*/
sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_irq_group_t group, uint32_t mask, bool enable);
sc_irq_group_t group, uint32_t mask, sc_bool_t enable);
/*!
* This function returns the current interrupt status (regardless if
@ -154,6 +162,6 @@ sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
sc_irq_group_t group, uint32_t *status);
#endif /* _SC_IRQ_API_H */
#endif /* SC_IRQ_API_H */
/**@}*/

349
include/soc/imx8/sc/svc/misc/api.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -16,8 +16,8 @@
* @{
*/
#ifndef _SC_MISC_API_H
#define _SC_MISC_API_H
#ifndef SC_MISC_API_H
#define SC_MISC_API_H
/* Includes */
@ -30,45 +30,50 @@
* @name Defines for type widths
*/
/*@{*/
#define SC_MISC_DMA_GRP_W 5 /* Width of sc_misc_dma_group_t */
#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */
/*@}*/
/*! Max DMA channel priority group */
#define SC_MISC_DMA_GRP_MAX 31
#define SC_MISC_DMA_GRP_MAX 31U
/*!
* @name Defines for sc_misc_boot_status_t
*/
/*@{*/
#define SC_MISC_BOOT_STATUS_SUCCESS 0 /* Success */
#define SC_MISC_BOOT_STATUS_SECURITY 1 /* Security violation */
/*@}*/
/*!
* @name Defines for sc_misc_seco_auth_cmd_t
*/
/*@{*/
#define SC_MISC_SECO_AUTH_SECO_FW 0 /* SECO Firmware */
#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1 /* HDMI TX Firmware */
#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2 /* HDMI RX Firmware */
#define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */
#define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */
/*@}*/
/*!
* @name Defines for sc_misc_temp_t
*/
/*@{*/
#define SC_MISC_TEMP 0 /* Temp sensor */
#define SC_MISC_TEMP_HIGH 1 /* Temp high alarm */
#define SC_MISC_TEMP_LOW 2 /* Temp low alarm */
#define SC_MISC_TEMP 0U /* Temp sensor */
#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */
#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */
/*@}*/
/*!
* @name Defines for sc_misc_seco_auth_cmd_t
*/
/*@{*/
#define SC_MISC_AUTH_CONTAINER 0 /* Authenticate container */
#define SC_MISC_VERIFY_IMAGE 1 /* Verify image */
#define SC_MISC_REL_CONTAINER 2 /* Release container */
#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */
#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */
#define SC_MISC_REL_CONTAINER 2U /* Release container */
#define SC_MISC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */
#define SC_MISC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */
#define SC_MISC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */
/*@}*/
/*!
* @name Defines for sc_misc_bt_t
*/
/*@{*/
#define SC_MISC_BT_PRIMARY 0U
#define SC_MISC_BT_SECONDARY 1U
#define SC_MISC_BT_RECOVERY 2U
#define SC_MISC_BT_MANUFACTURE 3U
#define SC_MISC_BT_SERIAL 4U
/*@}*/
/* Types */
@ -93,6 +98,11 @@ typedef uint8_t sc_misc_seco_auth_cmd_t;
*/
typedef uint8_t sc_misc_temp_t;
/*!
* This type is used report the boot type.
*/
typedef uint8_t sc_misc_bt_t;
/* Functions */
/*!
@ -203,33 +213,274 @@ sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource,
* @param[in] addr_src address of image source
* @param[in] addr_dst address of image destination
* @param[in] len lenth of image to load
* @param[in] fw true = firmware load
* @param[in] fw SC_TRUE = firmware load
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if word fuse index param out of range or invalid
* - SC_ERR_UNAVAILABLE if SECO not available
*
* This is used to load images via the SECO. Examples include SECO
* Firmware and IVT/CSF data used for authentication. These are usually
* loaded into SECO TCM. \a addr_src is in secure memory.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, uint32_t addr_src,
uint32_t addr_dst, uint32_t len, bool fw);
sc_err_t sc_misc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src,
sc_faddr_t addr_dst, uint32_t len,
sc_bool_t fw);
/*!
* This function is used to authenticate a SECO image or command.
*
* @param[in] ipc IPC handle
* @param[in] cmd authenticate command
* @param[in] addr_meta address of/or metadata
* @param[in] addr address of/or metadata
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if word fuse index param out of range or invalid
* - SC_ERR_UNAVAILABLE if SECO not available
*
* This is used to authenticate a SECO image or issue a security
* command. \a addr_meta often points to an container. It is also
* command. \a addr often points to an container. It is also
* just data (or even unused) for some commands.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_authenticate(sc_ipc_t ipc,
sc_misc_seco_auth_cmd_t cmd,
uint32_t addr_meta);
sc_faddr_t addr);
/*!
* This function securely writes a group of fuse words.
*
* @param[in] ipc IPC handle
* @param[in] addr address of message block
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_UNAVAILABLE if SECO not available
*
* Note \a addr must be a pointer to a signed message block.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function securely enables debug.
*
* @param[in] ipc IPC handle
* @param[in] addr address of message block
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_UNAVAILABLE if SECO not available
*
* Note \a addr must be a pointer to a signed message block.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function updates the lifecycle of the device.
*
* @param[in] ipc IPC handle
* @param[in] change desired lifecycle transistion
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_UNAVAILABLE if SECO not available
*
* This message is used for going from Open to NXP Closed to OEM Closed.
* Note \a change is NOT the new desired lifecycle. It is a lifecycle
* transition as documented in the Security Reference Manual (SRM).
*
* If any SECO request fails or only succeeds because the part is in an
* "OEM open" lifecycle, then a request to transition from "NXP closed"
* to "OEM closed" will also fail. For example, booting a signed container
* when the OEM SRK is not fused will succeed, but as it is an abnormal
* situation, a subsequent request to transition the lifecycle will return
* an error.
*/
sc_err_t sc_misc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change);
/*!
* This function updates the lifecycle to one of the return lifecycles.
*
* @param[in] ipc IPC handle
* @param[in] addr address of message block
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_UNAVAILABLE if SECO not available
*
* Note \a addr must be a pointer to a signed message block.
*
* To switch back to NXP states (Full Field Return), message must be signed
* by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM
* SRK.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function is used to return the SECO FW build info.
*
* @param[in] ipc IPC handle
* @param[out] version pointer to return build number
* @param[out] commit pointer to return commit ID (git SHA-1)
*/
void sc_misc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit);
/*!
* This function is used to return SECO chip info.
*
* @param[in] ipc IPC handle
* @param[out] lc pointer to return lifecycle
* @param[out] monotonic pointer to return monotonic counter
* @param[out] uid_l pointer to return UID (lower 32 bits)
* @param[out] uid_h pointer to return UID (upper 32 bits)
*/
sc_err_t sc_misc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc,
uint16_t *monotonic, uint32_t *uid_l,
uint32_t *uid_h);
/*!
* This function is used to set the attestation mode. Only the owner of
* the SC_R_ATTESTATION resource may make this call.
*
* @param[in] ipc IPC handle
* @param[in] mode mode
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if \a mode is invalid
* - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
* - SC_ERR_UNAVAILABLE if SECO not available
*
* This is used to set the SECO attestation mode. This can be prover
* or verfier. See the Security Reference Manual (SRM) for more on the
* suported modes, mode values, and mode behavior.
*/
sc_err_t sc_misc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode);
/*!
* This function is used to request atestation. Only the owner of
* the SC_R_ATTESTATION resource may make this call.
*
* @param[in] ipc IPC handle
* @param[in] nonce unique value
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
* - SC_ERR_UNAVAILABLE if SECO not available
*
* This is used to ask SECO to perform an attestation. The result depends
* on the attestation mode. After this call, the signature can be
* requested or a verify can be requested.
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_attest(sc_ipc_t ipc, uint64_t nonce);
/*!
* This function is used to retrieve the attestation public key.
* Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource
* may make this call.
*
* @param[in] ipc IPC handle
* @param[in] addr address to write response
*
* Result will be written to \a addr. The \a addr parmater must point
* to an address SECO can access. It must be 64-bit aligned. There
* should be 96 bytes of space.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if \a addr bad or attestation has not been requested
* - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
* - SC_ERR_UNAVAILABLE if SECO not available
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function is used to retrieve attestation signature and parameters.
* Mode must be provider. Only the owner of the SC_R_ATTESTATION resource
* may make this call.
*
* @param[in] ipc IPC handle
* @param[in] addr address to write response
*
* Result will be written to \a addr. The \a addr parmater must point
* to an address SECO can access. It must be 64-bit aligned. There
* should be 120 bytes of space.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if \a addr bad or attestation has not been requested
* - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
* - SC_ERR_UNAVAILABLE if SECO not available
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function is used to verify attestation. Mode must be verifier.
* Only the owner of the SC_R_ATTESTATION resource may make this call.
*
* @param[in] ipc IPC handle
* @param[in] addr address of signature
*
* The \a addr parmater must point to an address SECO can access. It must be
* 64-bit aligned.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if \a addr bad or attestation has not been requested
* - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller
* - SC_ERR_UNAVAILABLE if SECO not available
* - SC_ERR_FAIL if signature doesn't match
*
* See the Security Reference Manual (SRM) for more info.
*/
sc_err_t sc_misc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr);
/*!
* This function is used to commit into the fuses any new SRK revocation
* and FW version information that have been found in the primary and
* secondary containers.
*
* @param[in] ipc IPC handle
* @param[in,out] info pointer to information type to be committed
*
* The return \a info will contain what was actually committed.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors codes:
* - SC_ERR_PARM if \a info is invalid
* - SC_ERR_UNAVAILABLE if SECO not available
*/
sc_err_t sc_misc_seco_commit(sc_ipc_t ipc, uint32_t *info);
/* @} */
@ -257,7 +508,7 @@ void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch);
* Return errors:
* - SC_ERR_UNAVAILABLE if not running on emulation
*/
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, bool enable);
sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable);
/*!
* This function is used to return the SCFW build info.
@ -305,7 +556,8 @@ void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h);
* FISType and PM_Port.
*/
sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rsrc_t resource_mst, uint16_t ari, bool enable);
sc_rsrc_t resource_mst, uint16_t ari,
sc_bool_t enable);
/*!
* This function reports boot status.
@ -360,6 +612,11 @@ sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val);
* @param[in] word fuse word index
* @param[in] val fuse write value
*
* The command is passed as is to SECO. SECO uses part of the
* \a word parameter to indicate if the fuse should be locked
* after programming. See the "Write common fuse" section of
* the Security Reference Manual (SRM) for more info.
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors codes:
@ -380,6 +637,10 @@ sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val);
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* This function will enable the alarm interrupt if the temp requested is
* not the min/max temp. This enable automatically clears when the alarm
* occurs and this function has to be called again to re-enable.
*
* Return errors codes:
* - SC_ERR_PARM if parameters invalid
*/
@ -399,6 +660,7 @@ sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource,
*
* Return errors codes:
* - SC_ERR_PARM if parameters invalid
* - SC_ERR_BUSY if temp not ready yet (time delay after power on)
*/
sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
sc_misc_temp_t temp, int16_t * celsius,
@ -412,16 +674,39 @@ sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource,
*/
void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev);
/*!
* This function returns the boot type.
*
* @param[in] ipc IPC handle
* @param[out] type pointer to return boot type
*
* @return Returns and error code (SC_ERR_NONE = success).
*
* Return errors code:
* - SC_ERR_UNAVAILABLE if type not passed by ROM
*/
sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type);
/*!
* This function returns the current status of the ON/OFF button.
*
* @param[in] ipc IPC handle
* @param[out] status pointer to return button status
*/
void sc_misc_get_button_status(sc_ipc_t ipc, bool *status);
void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
/*!
* This function returns the ROM patch checksum.
*
* @param[in] ipc IPC handle
* @param[out] checksum pointer to return checksum
*
* @return Returns and error code (SC_ERR_NONE = success).
*/
sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum);
/* @} */
#endif /* _SC_MISC_API_H */
#endif /* SC_MISC_API_H */
/**@}*/

119
include/soc/imx8/sc/svc/pad/api.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -45,14 +45,19 @@
* assigned owners and only the owners can configure the pads. Some of the
* pads are reserved for use by the SCFW itself and this can be overriden
* with the implementation of board_config_sc(). Additionally, pads may
* be assigned to various other partitions via SCD or via the implementation
* of board_system_config().
* be assigned to various other partitions via the implementation of
* board_system_config().
*
* Note muxing two input pads to the same IP functional signal will
* result in undefined behavior.
*
* @includedoc pad/details.dox
*
* @{
*/
#ifndef _SC_PAD_API_H
#define _SC_PAD_API_H
#ifndef SC_PAD_API_H
#define SC_PAD_API_H
/* Includes */
@ -65,79 +70,79 @@
* @name Defines for type widths
*/
/*@{*/
#define SC_PAD_MUX_W 3 /* Width of mux parameter */
#define SC_PAD_MUX_W 3U /* Width of mux parameter */
/*@}*/
/*!
* @name Defines for sc_pad_config_t
*/
/*@{*/
#define SC_PAD_CONFIG_NORMAL 0 /* Normal */
#define SC_PAD_CONFIG_OD 1 /* Open Drain */
#define SC_PAD_CONFIG_OD_IN 2 /* Open Drain and input */
#define SC_PAD_CONFIG_OUT_IN 3 /* Output and input */
#define SC_PAD_CONFIG_NORMAL 0U /* Normal */
#define SC_PAD_CONFIG_OD 1U /* Open Drain */
#define SC_PAD_CONFIG_OD_IN 2U /* Open Drain and input */
#define SC_PAD_CONFIG_OUT_IN 3U /* Output and input */
/*@}*/
/*!
* @name Defines for sc_pad_iso_t
*/
/*@{*/
#define SC_PAD_ISO_OFF 0 /* ISO latch is transparent */
#define SC_PAD_ISO_EARLY 1 /* Follow EARLY_ISO */
#define SC_PAD_ISO_LATE 2 /* Follow LATE_ISO */
#define SC_PAD_ISO_ON 3 /* ISO latched data is held */
#define SC_PAD_ISO_OFF 0U /* ISO latch is transparent */
#define SC_PAD_ISO_EARLY 1U /* Follow EARLY_ISO */
#define SC_PAD_ISO_LATE 2U /* Follow LATE_ISO */
#define SC_PAD_ISO_ON 3U /* ISO latched data is held */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_dse_t
*/
/*@{*/
#define SC_PAD_28FDSOI_DSE_18V_1MA 0 /* Drive strength of 1mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_2MA 1 /* Drive strength of 2mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_4MA 2 /* Drive strength of 4mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_6MA 3 /* Drive strength of 6mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_8MA 4 /* Drive strength of 8mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_10MA 5 /* Drive strength of 10mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_12MA 6 /* Drive strength of 12mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_HS 7 /* High-speed drive strength for 1.8v */
#define SC_PAD_28FDSOI_DSE_33V_2MA 0 /* Drive strength of 2mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_4MA 1 /* Drive strength of 4mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_8MA 2 /* Drive strength of 8mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_12MA 3 /* Drive strength of 12mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_DV_HIGH 0 /* High drive strength for dual volt */
#define SC_PAD_28FDSOI_DSE_DV_LOW 1 /* Low drive strength for dual volt */
#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /* Drive strength of 1mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /* Drive strength of 2mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /* Drive strength of 4mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /* Drive strength of 6mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /* Drive strength of 8mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /* Drive strength of 10mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /* Drive strength of 12mA for 1.8v */
#define SC_PAD_28FDSOI_DSE_18V_HS 7U /* High-speed drive strength for 1.8v */
#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /* Drive strength of 2mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /* Drive strength of 4mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /* Drive strength of 8mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /* Drive strength of 12mA for 3.3v */
#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /* High drive strength for dual volt */
#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /* Low drive strength for dual volt */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_ps_t
*/
/*@{*/
#define SC_PAD_28FDSOI_PS_KEEPER 0 /* Bus-keeper (only valid for 1.8v) */
#define SC_PAD_28FDSOI_PS_PU 1 /* Pull-up */
#define SC_PAD_28FDSOI_PS_PD 2 /* Pull-down */
#define SC_PAD_28FDSOI_PS_NONE 3 /* No pull (disabled) */
#define SC_PAD_28FDSOI_PS_KEEPER 0U /* Bus-keeper (only valid for 1.8v) */
#define SC_PAD_28FDSOI_PS_PU 1U /* Pull-up */
#define SC_PAD_28FDSOI_PS_PD 2U /* Pull-down */
#define SC_PAD_28FDSOI_PS_NONE 3U /* No pull (disabled) */
/*@}*/
/*!
* @name Defines for sc_pad_28fdsoi_pus_t
*/
/*@{*/
#define SC_PAD_28FDSOI_PUS_30K_PD 0 /* 30K pull-down */
#define SC_PAD_28FDSOI_PUS_100K_PU 1 /* 100K pull-up */
#define SC_PAD_28FDSOI_PUS_3K_PU 2 /* 3K pull-up */
#define SC_PAD_28FDSOI_PUS_30K_PU 3 /* 30K pull-up */
#define SC_PAD_28FDSOI_PUS_30K_PD 0U /* 30K pull-down */
#define SC_PAD_28FDSOI_PUS_100K_PU 1U /* 100K pull-up */
#define SC_PAD_28FDSOI_PUS_3K_PU 2U /* 3K pull-up */
#define SC_PAD_28FDSOI_PUS_30K_PU 3U /* 30K pull-up */
/*@}*/
/*!
* @name Defines for sc_pad_wakeup_t
*/
/*@{*/
#define SC_PAD_WAKEUP_OFF 0 /* Off */
#define SC_PAD_WAKEUP_CLEAR 1 /* Clears pending flag */
#define SC_PAD_WAKEUP_LOW_LVL 4 /* Low level */
#define SC_PAD_WAKEUP_FALL_EDGE 5 /* Falling edge */
#define SC_PAD_WAKEUP_RISE_EDGE 6 /* Rising edge */
#define SC_PAD_WAKEUP_HIGH_LVL 7 /* High-level */
#define SC_PAD_WAKEUP_OFF 0U /* Off */
#define SC_PAD_WAKEUP_CLEAR 1U /* Clears pending flag */
#define SC_PAD_WAKEUP_LOW_LVL 4U /* Low level */
#define SC_PAD_WAKEUP_FALL_EDGE 5U /* Falling edge */
#define SC_PAD_WAKEUP_RISE_EDGE 6U /* Rising edge */
#define SC_PAD_WAKEUP_HIGH_LVL 7U /* High-level */
/*@}*/
/* Types */
@ -205,6 +210,9 @@ typedef uint8_t sc_pad_wakeup_t;
* - SC_PARM if arguments out of range or invalid,
* - SC_ERR_NOACCESS if caller's partition is not the pad owner
*
* Note muxing two input pads to the same IP functional signal will
* result in undefined behavior.
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad,
@ -326,6 +334,9 @@ sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup);
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Note muxing two input pads to the same IP functional signal will
* result in undefined behavior.
*
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux,
@ -471,9 +482,9 @@ sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t dse, bool hys,
sc_pad_28fdsoi_pus_t pus, bool pke,
bool pue);
sc_pad_28fdsoi_dse_t dse, sc_bool_t hys,
sc_pad_28fdsoi_pus_t pus, sc_bool_t pke,
sc_bool_t pue);
/*!
* This function gets the pad control specific to 28FDSOI.
@ -496,9 +507,9 @@ sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
sc_pad_28fdsoi_dse_t *dse, bool *hys,
sc_pad_28fdsoi_pus_t *pus, bool *pke,
bool *pue);
sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys,
sc_pad_28fdsoi_pus_t *pus, sc_bool_t *pke,
sc_bool_t *pue);
/*!
* This function configures the compensation control specific to 28FDSOI.
@ -525,9 +536,9 @@ sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad,
* operation (e.g. some Ethernet pads).
*/
sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t compen, bool fastfrz,
uint8_t compen, sc_bool_t fastfrz,
uint8_t rasrcp, uint8_t rasrcn,
bool nasrc_sel, bool psw_ovr);
sc_bool_t nasrc_sel, sc_bool_t psw_ovr);
/*!
* This function gets the compensation control specific to 28FDSOI.
@ -553,13 +564,13 @@ sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
* Refer to the SoC [Pad List](@ref PADS) for valid pad values.
*/
sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad,
uint8_t *compen, bool *fastfrz,
uint8_t *compen, sc_bool_t *fastfrz,
uint8_t *rasrcp, uint8_t *rasrcn,
bool *nasrc_sel, bool *compok,
uint8_t *nasrc, bool *psw_ovr);
sc_bool_t *nasrc_sel, sc_bool_t *compok,
uint8_t *nasrc, sc_bool_t *psw_ovr);
/* @} */
#endif /* _SC_PAD_API_H */
#endif /* SC_PAD_API_H */
/**@}*/

293
include/soc/imx8/sc/svc/pm/api.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -14,11 +14,13 @@
*
* Module for the Power Management (PM) service.
*
* @includedoc pm/details.dox
*
* @{
*/
#ifndef _SC_PM_API_H
#define _SC_PM_API_H
#ifndef SC_PM_API_H
#define SC_PM_API_H
/* Includes */
@ -31,10 +33,10 @@
* @name Defines for type widths
*/
/*@{*/
#define SC_PM_POWER_MODE_W 2 /* Width of sc_pm_power_mode_t */
#define SC_PM_CLOCK_MODE_W 3 /* Width of sc_pm_clock_mode_t */
#define SC_PM_RESET_TYPE_W 2 /* Width of sc_pm_reset_type_t */
#define SC_PM_RESET_REASON_W 3 /* Width of sc_pm_reset_reason_t */
#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */
#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */
#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */
#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */
/*@}*/
/*!
@ -47,92 +49,108 @@
* @name Defines for ALL parameters
*/
/*@{*/
#define SC_PM_CLK_ALL UINT8_MAX /* All clocks */
#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */
/*@}*/
/*!
* @name Defines for sc_pm_power_mode_t
*/
/*@{*/
#define SC_PM_PW_MODE_OFF 0 /* Power off */
#define SC_PM_PW_MODE_STBY 1 /* Power in standby */
#define SC_PM_PW_MODE_LP 2 /* Power in low-power */
#define SC_PM_PW_MODE_ON 3 /* Power on */
#define SC_PM_PW_MODE_OFF 0U /* Power off */
#define SC_PM_PW_MODE_STBY 1U /* Power in standby */
#define SC_PM_PW_MODE_LP 2U /* Power in low-power */
#define SC_PM_PW_MODE_ON 3U /* Power on */
/*@}*/
/*!
* @name Defines for sc_pm_clk_t
*/
/*@{*/
#define SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
#define SC_PM_CLK_MST_BUS 1 /* Master bus clock */
#define SC_PM_CLK_PER 2 /* Peripheral clock */
#define SC_PM_CLK_PHY 3 /* Phy clock */
#define SC_PM_CLK_MISC 4 /* Misc clock */
#define SC_PM_CLK_MISC0 0 /* Misc 0 clock */
#define SC_PM_CLK_MISC1 1 /* Misc 1 clock */
#define SC_PM_CLK_MISC2 2 /* Misc 2 clock */
#define SC_PM_CLK_MISC3 3 /* Misc 3 clock */
#define SC_PM_CLK_MISC4 4 /* Misc 4 clock */
#define SC_PM_CLK_CPU 2 /* CPU clock */
#define SC_PM_CLK_PLL 4 /* PLL */
#define SC_PM_CLK_BYPASS 4 /* Bypass clock */
#define SC_PM_CLK_SLV_BUS 0U /* Slave bus clock */
#define SC_PM_CLK_MST_BUS 1U /* Master bus clock */
#define SC_PM_CLK_PER 2U /* Peripheral clock */
#define SC_PM_CLK_PHY 3U /* Phy clock */
#define SC_PM_CLK_MISC 4U /* Misc clock */
#define SC_PM_CLK_MISC0 0U /* Misc 0 clock */
#define SC_PM_CLK_MISC1 1U /* Misc 1 clock */
#define SC_PM_CLK_MISC2 2U /* Misc 2 clock */
#define SC_PM_CLK_MISC3 3U /* Misc 3 clock */
#define SC_PM_CLK_MISC4 4U /* Misc 4 clock */
#define SC_PM_CLK_CPU 2U /* CPU clock */
#define SC_PM_CLK_PLL 4U /* PLL */
#define SC_PM_CLK_BYPASS 4U /* Bypass clock */
/*@}*/
/*!
* @name Defines for sc_pm_clk_mode_t
*/
/*@{*/
#define SC_PM_CLK_MODE_ROM_INIT 0 /* Clock is initialized by ROM. */
#define SC_PM_CLK_MODE_OFF 1 /* Clock is disabled */
#define SC_PM_CLK_MODE_ON 2 /* Clock is enabled. */
#define SC_PM_CLK_MODE_AUTOGATE_SW 3 /* Clock is in SW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_HW 4 /* Clock is in HW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5 /* Clock is in SW-HW autogate mode */
#define SC_PM_CLK_MODE_ROM_INIT 0U /* Clock is initialized by ROM. */
#define SC_PM_CLK_MODE_OFF 1U /* Clock is disabled */
#define SC_PM_CLK_MODE_ON 2U /* Clock is enabled. */
#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /* Clock is in SW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */
#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */
/*@}*/
/*!
* @name Defines for sc_pm_clk_parent_t
*/
/*@{*/
#define SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
#define SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
#define SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
#define SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
#define SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
#define SC_PM_PARENT_XTAL 0U /* Parent is XTAL. */
#define SC_PM_PARENT_PLL0 1U /* Parent is PLL0 */
#define SC_PM_PARENT_PLL1 2U /* Parent is PLL1 or PLL0/2 */
#define SC_PM_PARENT_PLL2 3U /* Parent in PLL2 or PLL0/4 */
#define SC_PM_PARENT_BYPS 4U /* Parent is a bypass clock. */
/*@}*/
/*!
* @name Defines for sc_pm_reset_type_t
*/
/*@{*/
#define SC_PM_RESET_TYPE_COLD 0 /* Cold reset */
#define SC_PM_RESET_TYPE_WARM 1 /* Warm reset */
#define SC_PM_RESET_TYPE_BOARD 2 /* Board reset */
#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */
#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */
#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */
/*@}*/
/*!
* @name Defines for sc_pm_reset_reason_t
*/
/*@{*/
#define SC_PM_RESET_REASON_POR 0 /* Power on reset */
#define SC_PM_RESET_REASON_WARM 1 /* Warm reset */
#define SC_PM_RESET_REASON_SW 2 /* Software reset */
#define SC_PM_RESET_REASON_WDOG 3 /* Watchdog reset */
#define SC_PM_RESET_REASON_LOCKUP 4 /* Lockup reset */
#define SC_PM_RESET_REASON_TAMPER 5 /* Tamper reset */
#define SC_PM_RESET_REASON_TEMP 6 /* Temp reset */
#define SC_PM_RESET_REASON_LOW_VOLT 7 /* Low voltage reset */
#define SC_PM_RESET_REASON_POR 0U /* Power on reset */
#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */
#define SC_PM_RESET_REASON_SW 2U /* Software reset */
#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */
#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */
#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */
#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */
#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */
#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */
#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */
#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */
#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */
#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */
/*@}*/
/*!
* @name Defines for sc_pm_sys_if_t
*/
/*@{*/
#define SC_PM_SYS_IF_INTERCONNECT 0 /* System interconnect */
#define SC_PM_SYS_IF_MU 1 /* AP -> SCU message units */
#define SC_PM_SYS_IF_OCMEM 2 /* On-chip memory (ROM/OCRAM) */
#define SC_PM_SYS_IF_DDR 3 /* DDR memory */
#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */
#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */
#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */
#define SC_PM_SYS_IF_DDR 3U /* DDR memory */
/*@}*/
/*!
* @name Defines for sc_pm_wake_src_t
*/
/*@{*/
#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */
#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */
/*@}*/
/* Types */
@ -179,6 +197,11 @@ typedef uint8_t sc_pm_reset_reason_t;
*/
typedef uint8_t sc_pm_sys_if_t;
/*!
* This type is used to specify a wake source for CPU resources.
*/
typedef uint8_t sc_pm_wake_src_t;
/* Functions */
/*!
@ -188,7 +211,8 @@ typedef uint8_t sc_pm_sys_if_t;
/*!
* This function sets the system power mode. Only the owner of the
* SC_R_SYSTEM resource can do this.
* SC_R_SYSTEM resource or a partition with access permissions to
* SC_R_SYSTEM can do this.
*
* @param[in] ipc IPC handle
* @param[in] mode power mode to apply
@ -197,7 +221,7 @@ typedef uint8_t sc_pm_sys_if_t;
*
* Return errors:
* - SC_ERR_PARM if invalid mode,
* - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
* - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access
*
* @see sc_pm_set_sys_power_mode().
*/
@ -217,10 +241,10 @@ sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode);
* - SC_ERR_NOACCESS if caller's partition is not the owner or
* parent of \a pt
*
* All resources owned by \a pt that are on will have their power
* mode changed to \a mode.
*
* @see sc_pm_set_resource_power_mode().
* The power mode of the partitions is a max power any resource will
* be set to. Calling this will result in all resources owned
* by \a pt to have their power changed to the lower of \a mode or the
* individual resource mode set using sc_pm_set_resource_power_mode().
*/
sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_pm_power_mode_t mode);
@ -254,19 +278,58 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
* - SC_ERR_NOACCESS if caller's partition is not the resource owner
* or parent of the owner
*
* Resources set to SC_PM_PW_MODE_ON will reflect the
* power mode of the partition and will change as that changes.
* Resources must be at SC_PM_PW_MODE_LP mode or higher to access them,
* otherwise the master will get a bus error or hang.
*
* This function will record the individual resource power mode
* and change it if the requested mode is lower than or equal to the
* partition power mode set with sc_pm_set_partition_power_mode().
* In other words, the power mode of the resource will be the minimum
* of the resource power mode and the partition power mode.
*
* Note some resources are still not accessible even when powered up if bus
* transactions go through a fabric not powered up. Examples of this are
* resources in display and capture subsystems which require the display
* controller or the imaging subsytem to be powered up first.
*
* @see sc_pm_set_partition_power_mode().
* Not that resources are grouped into power domains by the underlying
* hardware. If any resource in the domain is on, the entire power domain
* will be on. Other power domains required to access the resource will
* also be turned on. Clocks required to access the peripheral will be
* turned on. Refer to the SoC RM for more info on power domains and access
* infrastructure (bus fabrics, clock domains, etc.).
*/
sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
/*!
* This function sets the power mode for all the resources owned
* by a child partition.
*
* @param[in] ipc IPC handle
* @param[in] pt handle of child partition
* @param[in] mode power mode to apply
* @param[in] exclude resource to exclude
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid partition or mode,
* - SC_ERR_NOACCESS if caller's partition is not the parent
* of \a pt
*
* This functions loops through all the resources owned by \a pt
* and sets the power mode to \a mode. It will skip setting
* \a exclude (SC_R_LAST to skip none).
*
* This function can only be called by the parent. It is used to
* implement some aspects of virtualization.
*/
sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc,
sc_rm_pt_t pt,
sc_pm_power_mode_t mode,
sc_rsrc_t exclude);
/*!
* This function gets the power mode of a resource.
*
@ -295,7 +358,7 @@ sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[out] mode pointer to return power mode
* @param[in] mode power mode to apply
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@ -303,6 +366,30 @@ sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode);
/*!
* This function requests low-power mode entry for CPU/cluster
* resources. This API is only valid for the following resources:
* SC_R_A53, SC_R_A53_x, SC_R_A72, SC_R_A72_x, SC_R_A35, SC_R_A35_x,
* SC_R_CCI. For all other resources it will return SC_ERR_PARAM.
* For individual core resources, the specified power mode
* and wake source will be applied after the core has entered
* WFI. For cluster resources, the specified power mode is
* applied after all cores in the cluster have entered low-power mode.
* For multicluster resources, the specified power mode is applied
* after all clusters have reached low-power mode.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] mode power mode to apply
* @param[in] wake_src wake source for low-power exit
*
* @return Returns an error code (SC_ERR_NONE = success).
*
*/
sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_power_mode_t mode,
sc_pm_wake_src_t wake_src);
/*!
* This function is used to set the resume address of a CPU.
*
@ -320,6 +407,25 @@ sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource,
sc_faddr_t address);
/*!
* This function is used to set parameters for CPU resume from
* low-power mode.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
* @param[in] isPrimary set SC_TRUE if primary wake CPU
* @param[in] address 64-bit resume address
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid resource or address,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* resource (CPU) owner
*/
sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource,
sc_bool_t isPrimary, sc_faddr_t address);
/*!
* This function requests the power mode configuration for system-level
* interfaces including messaging units, interconnect, and memories. This API
@ -398,9 +504,15 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
* @param[in] ipc IPC handle
* @param[in] resource ID of the resource
* @param[in] clk clock to affect
* @param[in] enable enable if true; otherwise disabled
* @param[in] enable enable if SC_TRUE; otherwise disabled
* @param[in] autog HW auto clock gating
*
* If \a resource is SC_R_ALL then all resources owned will be affected.
* No error will be returned.
*
* If \a clk is SC_PM_CLK_ALL, then an error will be returned if any
* of the available clocks returns an error.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
@ -412,7 +524,7 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
sc_pm_clk_t clk, bool enable, bool autog);
sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
/*!
* This function sets the parent of a resource's clock.
@ -431,6 +543,7 @@ sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
* or parent of the owner,
* - SC_ERR_UNAVAILABLE if clock not applicable to this resource
* - SC_ERR_BUSY if clock is currently enabled.
* - SC_ERR_NOPOWER if resource not powered
*
* Refer to the [Clock List](@ref CLOCKS) for valid clock values.
*/
@ -467,7 +580,8 @@ sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
/*!
* This function is used to reset the system. Only the owner of the
* SC_R_SYSTEM resource can do this.
* SC_R_SYSTEM resource or a partition with access permissions to
* SC_R_SYSTEM can do this.
*
* @param[in] ipc IPC handle
* @param[in] type reset type
@ -476,7 +590,7 @@ sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource,
*
* Return errors:
* - SC_ERR_PARM if invalid type,
* - SC_ERR_NOACCESS if caller not the owner of SC_R_SYSTEM
* - SC_ERR_NOACCESS if caller cannot access SC_R_SYSTEM
*
* If this function returns, then the reset did not occur due to an
* invalid parameter.
@ -489,6 +603,13 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type);
* @param[in] ipc IPC handle
* @param[out] reason pointer to return reset reason
*
* This function returns the reason a partition was reset. If the reason
* is POR, then the system reset reason will be returned.
*
* Note depending on the connection of the WDOG_OUT signal and the OTP
* programming of the PMIC, some resets may trigger a system POR
* and the original reason will be lost.
*
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
@ -509,6 +630,10 @@ sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason);
* - SC_ERR_PARM if invalid partition, resource, or addr,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* partition to boot
*
* This must be used to boot a partition. Only a partition booted this
* way can be rebooted using the watchdog, sc_pm_boot() or
* sc_pm_reboot_partition().
*/
sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
@ -560,7 +685,8 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
*
* Return errors:
* - SC_ERR_PARM if invalid partition or type
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt,
* - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt
* and the caller does not have access to SC_R_SYSTEM
*
* Most peripherals owned by the partition will be reset if
* possible. SC state (partitions, power, clocks, etc.) is reset. The
@ -575,7 +701,7 @@ sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
* @param[in] enable start if true; otherwise stop
* @param[in] enable start if SC_TRUE; otherwise stop
* @param[in] address 64-bit boot address
*
* @return Returns an error code (SC_ERR_NONE = success).
@ -584,12 +710,41 @@ sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
* - SC_ERR_PARM if invalid resource or address,
* - SC_ERR_NOACCESS if caller's partition is not the parent of the
* resource (CPU) owner
*
* This function is usually used to start a secondar CPU in the
* same partition as the caller. It is not used to start the first
* CPU in a dedicated partition. That would be started by calling
* sc_pm_boot().
*
* A CPU started with sc_pm_cpu_start() will not restart as a result
* of a watchdog event or calling sc_pm_reboot() or sc_pm_reboot_partition().
* Those will reboot that partition which will start the CPU started with
* sc_pm_boot().
*/
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
sc_faddr_t address);
/*!
* This function is used to reset a CPU.
*
* @param[in] ipc IPC handle
* @param[in] resource ID of the CPU resource
* @param[in] address 64-bit boot address
*
* This function does not return anything as the calling core may have been
* reset. It can still fail if the resource or address is invalid. It can also
* fail if the caller's partition is not the owner of the CPU, not the parent
* of the CPU resource owner, or has access to SC_R_SYSTEM. Will also fail if
* the resource is not powered on. No indication of failure is returned.
*
* Note this just resets the CPU. None of the peripherals or bus fabric used by
* the CPU is reset. State configured in the SCFW is not reset. The SW running
* on the core has to understand and deal with this.
*/
void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address);
/* @} */
#endif /* _SC_PM_API_H */
#endif /* SC_PM_API_H */
/**@}*/

139
include/soc/imx8/sc/svc/rm/api.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -19,8 +19,8 @@
* @{
*/
#ifndef _SC_RM_API_H
#define _SC_RM_API_H
#ifndef SC_RM_API_H
#define SC_RM_API_H
/* Includes */
@ -32,44 +32,44 @@
* @name Defines for type widths
*/
/*@{*/
#define SC_RM_PARTITION_W 5 /* Width of sc_rm_pt_t */
#define SC_RM_MEMREG_W 6 /* Width of sc_rm_mr_t */
#define SC_RM_DID_W 4 /* Width of sc_rm_did_t */
#define SC_RM_SID_W 6 /* Width of sc_rm_sid_t */
#define SC_RM_SPA_W 2 /* Width of sc_rm_spa_t */
#define SC_RM_PERM_W 3 /* Width of sc_rm_perm_t */
#define SC_RM_PARTITION_W 5U /* Width of sc_rm_pt_t */
#define SC_RM_MEMREG_W 6U /* Width of sc_rm_mr_t */
#define SC_RM_DID_W 4U /* Width of sc_rm_did_t */
#define SC_RM_SID_W 6U /* Width of sc_rm_sid_t */
#define SC_RM_SPA_W 2U /* Width of sc_rm_spa_t */
#define SC_RM_PERM_W 3U /* Width of sc_rm_perm_t */
/*@}*/
/*!
* @name Defines for ALL parameters
*/
/*@{*/
#define SC_RM_PT_ALL UINT8_MAX /* All partitions */
#define SC_RM_MR_ALL UINT8_MAX /* All memory regions */
#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /* All partitions */
#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /* All memory regions */
/*@}*/
/*!
* @name Defines for sc_rm_spa_t
*/
/*@{*/
#define SC_RM_SPA_PASSTHRU 0 /* Pass through (attribute driven by master) */
#define SC_RM_SPA_PASSSID 1 /* Pass through and output on SID */
#define SC_RM_SPA_ASSERT 2 /* Assert (force to be secure/privileged) */
#define SC_RM_SPA_NEGATE 3 /* Negate (force to be non-secure/user) */
#define SC_RM_SPA_PASSTHRU 0U /* Pass through (attribute driven by master) */
#define SC_RM_SPA_PASSSID 1U /* Pass through and output on SID */
#define SC_RM_SPA_ASSERT 2U /* Assert (force to be secure/privileged) */
#define SC_RM_SPA_NEGATE 3U /* Negate (force to be non-secure/user) */
/*@}*/
/*!
* @name Defines for sc_rm_perm_t
*/
/*@{*/
#define SC_RM_PERM_NONE 0 /* No access */
#define SC_RM_PERM_SEC_R 1 /* Secure RO */
#define SC_RM_PERM_SECPRIV_RW 2 /* Secure privilege R/W */
#define SC_RM_PERM_SEC_RW 3 /* Secure R/W */
#define SC_RM_PERM_NSPRIV_R 4 /* Secure R/W, non-secure privilege RO */
#define SC_RM_PERM_NS_R 5 /* Secure R/W, non-secure RO */
#define SC_RM_PERM_NSPRIV_RW 6 /* Secure R/W, non-secure privilege R/W */
#define SC_RM_PERM_FULL 7 /* Full access */
#define SC_RM_PERM_NONE 0U /* No access */
#define SC_RM_PERM_SEC_R 1U /* Secure RO */
#define SC_RM_PERM_SECPRIV_RW 2U /* Secure privilege R/W */
#define SC_RM_PERM_SEC_RW 3U /* Secure R/W */
#define SC_RM_PERM_NSPRIV_R 4U /* Secure R/W, non-secure privilege RO */
#define SC_RM_PERM_NS_R 5U /* Secure R/W, non-secure RO */
#define SC_RM_PERM_NSPRIV_RW 6U /* Secure R/W, non-secure privilege R/W */
#define SC_RM_PERM_FULL 7U /* Full access */
/*@}*/
/* Types */
@ -122,13 +122,13 @@ typedef uint8_t sc_rm_perm_t;
* @param[in] secure boolean indicating if this partition should be secure; only
* valid if caller is secure
* @param[in] isolated boolean indicating if this partition should be HW isolated
* via XRDC; set true if new DID is desired
* via XRDC; set SC_TRUE if new DID is desired
* @param[in] restricted boolean indicating if this partition should be restricted; set
* true if masters in this partition cannot create new partitions
* SC_TRUE if masters in this partition cannot create new partitions
* @param[in] grant boolean indicating if this partition should always grant
* access and control to the parent
* @param[in] coherent boolean indicating if this partition is coherent;
* set true if only this partition will contain both AP clusters
* set SC_TRUE if only this partition will contain both AP clusters
* and they will be coherent via the CCI
*
* @return Returns an error code (SC_ERR_NONE = success).
@ -147,9 +147,9 @@ typedef uint8_t sc_rm_perm_t;
* memory without isolating the peripheral interface of the master or the API
* controls of that master.
*/
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
bool isolated, bool restricted, bool grant,
bool coherent);
sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
sc_bool_t isolated, sc_bool_t restricted,
sc_bool_t grant, sc_bool_t coherent);
/*!
* This function makes a partition confidential.
@ -171,7 +171,7 @@ sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, bool secure,
* If retroactive, then all resources owned by other partitions will have
* access rights for this partition removed, even if locked.
*/
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, bool retro);
sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro);
/*!
* This function frees a partition and assigns all resources to the caller.
@ -299,7 +299,7 @@ sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
* - SC_ERR_LOCKED if either partition is locked
*/
sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
bool move_rsrc, bool move_pads);
sc_bool_t move_rsrc, sc_bool_t move_pads);
/* @} */
@ -323,7 +323,7 @@ sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst,
* ASSERT if the partition si secure and NEGATE if it is not, and
* masters will defaulted to SMMU bypass. Access permissions will reset
* to SEC_RW for the owning partition only for secure partitions, FULL for
* non-secure. DEfault is no access by other partitions.
* non-secure. Default is no access by other partitions.
*
* Return errors:
* - SC_ERR_NOACCESS if caller's partition is restricted,
@ -340,7 +340,7 @@ sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
* @param[in] ipc IPC handle
* @param[in] resource_fst first resource for which flag should be set
* @param[in] resource_lst last resource for which flag should be set
* @param[in] movable movable flag (true) is movable
* @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@ -355,7 +355,7 @@ sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
* resources from moving.
*/
sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
sc_rsrc_t resource_lst, bool movable);
sc_rsrc_t resource_lst, sc_bool_t movable);
/*!
* This function flags all of a subsystem's resources as movable
@ -363,7 +363,7 @@ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
*
* @param[in] ipc IPC handle
* @param[in] resource resource to use to identify subsystem
* @param[in] movable movable flag (true) is movable
* @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@ -374,7 +374,7 @@ sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst,
* resources owned by the caller are set.
*/
sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
bool movable);
sc_bool_t movable);
/*!
* This function sets attributes for a resource which is a bus master (i.e.
@ -400,7 +400,7 @@ sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource,
*/
sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_spa_t sa, sc_rm_spa_t pa,
bool smmu_bypass);
sc_bool_t smmu_bypass);
/*!
* This function sets the StreamID for a resource which is a bus master (i.e.
@ -444,7 +444,8 @@ sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource,
* - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt
*
* This function configures how the HW isolation will restrict access to a
* peripheral based on the attributes of a transaction from bus master.
* peripheral based on the attributes of a transaction from bus master. It
* also allows the access permissions of SC_R_SYSTEM to be set.
*/
sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
sc_rm_pt_t pt, sc_rm_perm_t perm);
@ -455,11 +456,11 @@ sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource,
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* @return Returns a boolean (true if caller's partition owns the resource).
* @return Returns a boolean (SC_TRUE if caller's partition owns the resource).
*
* If \a resource is out of range then false is returned.
* If \a resource is out of range then SC_FALSE is returned.
*/
bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to test if a resource is a bus master.
@ -467,11 +468,11 @@ bool sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* @return Returns a boolean (true if the resource is a bus master).
* @return Returns a boolean (SC_TRUE if the resource is a bus master).
*
* If \a resource is out of range then false is returned.
* If \a resource is out of range then SC_FALSE is returned.
*/
bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to test if a resource is a peripheral.
@ -479,11 +480,11 @@ bool sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource);
* @param[in] ipc IPC handle
* @param[in] resource resource to check
*
* @return Returns a boolean (true if the resource is a peripheral).
* @return Returns a boolean (SC_TRUE if the resource is a peripheral).
*
* If \a resource is out of range then false is returned.
* If \a resource is out of range then SC_FALSE is returned.
*/
bool sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource);
/*!
* This function is used to obtain info about a resource.
@ -563,6 +564,32 @@ sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr,
sc_rm_mr_t *mr_ret, sc_faddr_t addr_start,
sc_faddr_t addr_end);
/*!
* This function requests that the SC fragment a memory region.
*
* @param[in] ipc IPC handle
* @param[out] mr_ret return handle for new region; used for
* subsequent function calls
* associated with this region
* @param[in] addr_start start address of region (physical)
* @param[in] addr_end end address of region (physical)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_LOCKED if caller's partition is locked,
* - SC_ERR_PARM if the new memory region spans multiple existing regions,
* - SC_ERR_NOACCESS if caller's partition does not own the memory containing
* the new region,
* - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation
* space)
*
* This function finds the memory region containing the address range.
* It then splits it as required and returns the extracted region.
*/
sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret,
sc_faddr_t addr_start, sc_faddr_t addr_end);
/*!
* This function frees a memory region.
*
@ -653,12 +680,12 @@ sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
* @param[in] ipc IPC handle
* @param[in] mr handle of memory region to check
*
* @return Returns a boolean (true if caller's partition owns the
* @return Returns a boolean (SC_TRUE if caller's partition owns the
* memory region).
*
* If \a mr is out of range then false is returned.
* If \a mr is out of range then SC_FALSE is returned.
*/
bool sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
/*!
* This function is used to obtain info about a memory region.
@ -708,7 +735,7 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
* @param[in] ipc IPC handle
* @param[in] pad_fst first pad for which flag should be set
* @param[in] pad_lst last pad for which flag should be set
* @param[in] movable movable flag (true) is movable
* @param[in] movable movable flag (SC_TRUE is movable)
*
* @return Returns an error code (SC_ERR_NONE = success).
*
@ -723,7 +750,7 @@ sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
* pads from moving.
*/
sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
sc_pad_t pad_lst, bool movable);
sc_pad_t pad_lst, sc_bool_t movable);
/*!
* This function gets ownership status of a pad.
@ -731,11 +758,11 @@ sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst,
* @param[in] ipc IPC handle
* @param[in] pad pad to check
*
* @return Returns a boolean (true if caller's partition owns the pad).
* @return Returns a boolean (SC_TRUE if caller's partition owns the pad).
*
* If \a pad is out of range then false is returned.
* If \a pad is out of range then SC_FALSE is returned.
*/
bool sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
/* @} */
@ -753,6 +780,6 @@ void sc_rm_dump(sc_ipc_t ipc);
/* @} */
#endif /* _SC_RM_API_H */
#endif /* SC_RM_API_H */
/**@}*/

109
include/soc/imx8/sc/svc/timer/api.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -18,8 +18,8 @@
* @{
*/
#ifndef _SC_TIMER_API_H
#define _SC_TIMER_API_H
#ifndef SC_TIMER_API_H
#define SC_TIMER_API_H
/* Includes */
@ -32,18 +32,18 @@
* @name Defines for type widths
*/
/*@{*/
#define SC_TIMER_ACTION_W 3 /* Width of sc_timer_wdog_action_t */
#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */
/*@}*/
/*!
* @name Defines for sc_timer_wdog_action_t
*/
/*@{*/
#define SC_TIMER_WDOG_ACTION_PARTITION 0 /* Reset partition */
#define SC_TIMER_WDOG_ACTION_WARM 1 /* Warm reset system */
#define SC_TIMER_WDOG_ACTION_COLD 2 /* Cold reset system */
#define SC_TIMER_WDOG_ACTION_BOARD 3 /* Reset board */
#define SC_TIMER_WDOG_ACTION_IRQ 4 /* Only generate IRQs */
#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */
#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */
#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */
#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */
#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */
/*@}*/
/* Types */
@ -106,7 +106,7 @@ sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc,
* If \a lock is set then the watchdog cannot be stopped or the timeout
* period changed.
*/
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, bool lock);
sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock);
/*!
* This function stops the watchdog if it is not locked.
@ -158,7 +158,8 @@ sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc,
*
* @return Returns an error code (SC_ERR_NONE = success).
*/
sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, bool *enb,
sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt,
sc_bool_t *enb,
sc_timer_wdog_time_t *timeout,
sc_timer_wdog_time_t *remaining_time);
@ -191,7 +192,8 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
/*!
* This function sets the RTC time. Only the owner of the SC_R_SYSTEM
* resource can set the time.
* resource or a partition with access permissions to SC_R_SYSTEM can
* set the time.
*
* @param[in] ipc IPC handle
* @param[in] year year (min 1970)
@ -205,7 +207,7 @@ sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc,
*
* Return errors:
* - SC_ERR_PARM if invalid time/date parameters,
* - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner
* - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM
*/
sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon,
uint8_t day, uint8_t hour, uint8_t min,
@ -260,9 +262,37 @@ sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon,
uint8_t day, uint8_t hour, uint8_t min,
uint8_t sec);
/*!
* This function sets the RTC alarm (periodic mode).
*
* @param[in] ipc IPC handle
* @param[in] sec period in seconds
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid time/date parameters
*/
sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec);
/*!
* This function cancels the RTC alarm.
*
* @param[in] ipc IPC handle
*
* Note this alarm setting clears when the alarm is triggered.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid time/date parameters
*/
sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc);
/*!
* This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM
* resource can set the calibration.
* resource or a partition with access permissions to SC_R_SYSTEM can set the
* calibration.
*
* @param[in] ipc IPC handle
* @param[in] count calbration count (-16 to 15)
@ -277,6 +307,55 @@ sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count);
/* @} */
#endif /* _SC_TIMER_API_H */
/*!
* @name System Counter (SYSCTR) Functions
* @{
*/
/*!
* This function sets the SYSCTR alarm.
*
* @param[in] ipc IPC handle
* @param[in] ticks number of 8MHz cycles
*
* Note this alarm setting clears when the alarm is triggered.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid time/date parameters
*/
sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks);
/*!
* This function sets the SYSCTR alarm (periodic mode).
*
* @param[in] ipc IPC handle
* @param[in] ticks number of 8MHz cycles
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid time/date parameters
*/
sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks);
/*!
* This function cancels the SYSCTR alarm.
*
* @param[in] ipc IPC handle
*
* Note this alarm setting clears when the alarm is triggered.
*
* @return Returns an error code (SC_ERR_NONE = success).
*
* Return errors:
* - SC_ERR_PARM if invalid time/date parameters
*/
sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc);
/* @} */
#endif /* SC_TIMER_API_H */
/**@}*/

1487
include/soc/imx8/sc/types.h
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