rapidio/tsi721: modify PCIe capability settings
Modify initialization of PCIe capability registers in Tsi721 mport driver: - change Completion Timeout value to avoid unexpected data transfer aborts during intensive traffic. - replace hardcoded offset of PCIe capability block by making it use the common function. This patch is applicable to kernel versions starting from 3.2-rc1. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Cc: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -2154,7 +2154,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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const struct pci_device_id *id)
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{
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{
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struct tsi721_device *priv;
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struct tsi721_device *priv;
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int i;
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int i, cap;
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int err;
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int err;
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u32 regval;
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u32 regval;
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@ -2262,10 +2262,20 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
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dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
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dev_info(&pdev->dev, "Unable to set consistent DMA mask\n");
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}
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}
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/* Clear "no snoop" and "relaxed ordering" bits. */
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cap = pci_pcie_cap(pdev);
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pci_read_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, ®val);
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BUG_ON(cap == 0);
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regval &= ~(PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN);
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pci_write_config_dword(pdev, 0x40 + PCI_EXP_DEVCTL, regval);
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/* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
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pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, ®val);
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regval &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
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PCI_EXP_DEVCTL_NOSNOOP_EN);
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regval |= 0x2 << MAX_READ_REQUEST_SZ_SHIFT;
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pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL, regval);
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/* Adjust PCIe completion timeout. */
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pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL2, ®val);
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regval &= ~(0x0f);
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pci_write_config_dword(pdev, cap + PCI_EXP_DEVCTL2, regval | 0x2);
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/*
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/*
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* FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
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* FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block
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@ -72,6 +72,8 @@
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#define TSI721_MSIXPBA_OFFSET 0x2a000
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#define TSI721_MSIXPBA_OFFSET 0x2a000
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#define TSI721_PCIECFG_EPCTL 0x400
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#define TSI721_PCIECFG_EPCTL 0x400
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#define MAX_READ_REQUEST_SZ_SHIFT 12
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/*
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/*
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* Event Management Registers
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* Event Management Registers
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*/
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*/
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