Merge tag 'drm-fixes-for-v4.7-rc7' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "One nouveau fix, and a few AMD Polaris fixes and some Allwinner fixes. I've got some vmware fixes that I might send separate over the weekend, they fix some black screens, but I'm still debating them" * tag 'drm-fixes-for-v4.7-rc7' of git://people.freedesktop.org/~airlied/linux: drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation. drm/amd/powerplay: fix bug that get wrong polaris evv voltage. drm/amd/powerplay: incorrectly use of the function return value drm/amd/powerplay: fix incorrect voltage table value for tonga drm/amd/powerplay: fix incorrect voltage table value for polaris10 drm/nouveau/disp/sor/gf119: select correct sor when poking training pattern gpu: drm: sun4i_drv: add missing of_node_put after calling of_parse_phandle drm/sun4i: Send vblank event when the CRTC is disabled drm/sun4i: Report proper vblank
This commit is contained in:
commit
1d110cf5d3
|
@ -98,7 +98,6 @@
|
|||
#define PCIE_BUS_CLK 10000
|
||||
#define TCLK (PCIE_BUS_CLK / 10)
|
||||
|
||||
#define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))
|
||||
|
||||
static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =
|
||||
{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
|
||||
|
@ -733,7 +732,7 @@ static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
|
|||
table->Smio[level] |=
|
||||
data->mvdd_voltage_table.entries[level].smio_low;
|
||||
}
|
||||
table->SmioMask2 = data->vddci_voltage_table.mask_low;
|
||||
table->SmioMask2 = data->mvdd_voltage_table.mask_low;
|
||||
|
||||
table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
|
||||
}
|
||||
|
@ -1807,27 +1806,25 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
|
|||
|
||||
ro = efuse * (max -min)/255 + min;
|
||||
|
||||
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset
|
||||
* there is a little difference in calculating
|
||||
* volt_with_cks with windows */
|
||||
/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
|
||||
for (i = 0; i < sclk_table->count; i++) {
|
||||
data->smc_state_table.Sclk_CKS_masterEn0_7 |=
|
||||
sclk_table->entries[i].cks_enable << i;
|
||||
if (hwmgr->chip_id == CHIP_POLARIS10) {
|
||||
volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
|
||||
volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \
|
||||
(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
|
||||
volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \
|
||||
(252248000 - sclk_table->entries[i].clk/100 * 115764));
|
||||
volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
|
||||
(2522480 - sclk_table->entries[i].clk/100 * 115764/100));
|
||||
} else {
|
||||
volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
|
||||
(2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));
|
||||
volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \
|
||||
(3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));
|
||||
volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \
|
||||
(2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
|
||||
volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
|
||||
(3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
|
||||
}
|
||||
|
||||
if (volt_without_cks >= volt_with_cks)
|
||||
volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +
|
||||
sclk_table->entries[i].cks_voffset) * 100 / 625);
|
||||
volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
|
||||
sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
|
||||
|
||||
data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
|
||||
}
|
||||
|
@ -2685,7 +2682,7 @@ static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
|
|||
{
|
||||
struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
|
||||
uint16_t vv_id;
|
||||
uint16_t vddc = 0;
|
||||
uint32_t vddc = 0;
|
||||
uint16_t i, j;
|
||||
uint32_t sclk = 0;
|
||||
struct phm_ppt_v1_information *table_info =
|
||||
|
@ -2716,8 +2713,9 @@ static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr)
|
|||
continue);
|
||||
|
||||
|
||||
/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
|
||||
PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
|
||||
/* need to make sure vddc is less than 2v or else, it could burn the ASIC.
|
||||
* real voltage level in unit of 0.01mv */
|
||||
PP_ASSERT_WITH_CODE((vddc < 200000 && vddc != 0),
|
||||
"Invalid VDDC value", result = -EINVAL;);
|
||||
|
||||
/* the voltage should not be zero nor equal to leakage ID */
|
||||
|
|
|
@ -1256,7 +1256,7 @@ int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
|
|||
}
|
||||
|
||||
int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
||||
uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage)
|
||||
uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage)
|
||||
{
|
||||
|
||||
int result;
|
||||
|
@ -1274,7 +1274,7 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
|
|||
if (0 != result)
|
||||
return result;
|
||||
|
||||
*voltage = get_voltage_info_param_space.usVoltageLevel;
|
||||
*voltage = ((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
@ -305,7 +305,7 @@ extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t
|
|||
extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
|
||||
uint8_t level);
|
||||
extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
||||
uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
|
||||
uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
|
||||
extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
|
||||
|
||||
extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
|
||||
|
|
|
@ -1302,7 +1302,7 @@ static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
|
|||
table->Smio[count] |=
|
||||
data->mvdd_voltage_table.entries[count].smio_low;
|
||||
}
|
||||
table->SmioMask2 = data->vddci_voltage_table.mask_low;
|
||||
table->SmioMask2 = data->mvdd_voltage_table.mask_low;
|
||||
|
||||
CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
|
||||
}
|
||||
|
|
|
@ -302,7 +302,7 @@ static int init_dpm_2_parameters(
|
|||
(((unsigned long)powerplay_table) + le16_to_cpu(powerplay_table->usPPMTableOffset));
|
||||
|
||||
if (0 != powerplay_table->usPPMTableOffset) {
|
||||
if (1 == get_platform_power_management_table(hwmgr, atom_ppm_table)) {
|
||||
if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) {
|
||||
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_EnablePlatformPowerManagement);
|
||||
}
|
||||
|
|
|
@ -40,7 +40,8 @@ static int
|
|||
gf119_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
|
||||
{
|
||||
struct nvkm_device *device = outp->base.disp->engine.subdev.device;
|
||||
nvkm_mask(device, 0x61c110, 0x0f0f0f0f, 0x01010101 * pattern);
|
||||
const u32 soff = gf119_sor_soff(outp);
|
||||
nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -65,6 +65,14 @@ static void sun4i_crtc_disable(struct drm_crtc *crtc)
|
|||
DRM_DEBUG_DRIVER("Disabling the CRTC\n");
|
||||
|
||||
sun4i_tcon_disable(drv->tcon);
|
||||
|
||||
if (crtc->state->event && !crtc->state->active) {
|
||||
spin_lock_irq(&crtc->dev->event_lock);
|
||||
drm_crtc_send_vblank_event(crtc, crtc->state->event);
|
||||
spin_unlock_irq(&crtc->dev->event_lock);
|
||||
|
||||
crtc->state->event = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static void sun4i_crtc_enable(struct drm_crtc *crtc)
|
||||
|
|
|
@ -92,7 +92,7 @@ static struct drm_driver sun4i_drv_driver = {
|
|||
/* Frame Buffer Operations */
|
||||
|
||||
/* VBlank Operations */
|
||||
.get_vblank_counter = drm_vblank_count,
|
||||
.get_vblank_counter = drm_vblank_no_hw_counter,
|
||||
.enable_vblank = sun4i_drv_enable_vblank,
|
||||
.disable_vblank = sun4i_drv_disable_vblank,
|
||||
};
|
||||
|
@ -310,6 +310,7 @@ static int sun4i_drv_probe(struct platform_device *pdev)
|
|||
|
||||
count += sun4i_drv_add_endpoints(&pdev->dev, &match,
|
||||
pipeline);
|
||||
of_node_put(pipeline);
|
||||
|
||||
DRM_DEBUG_DRIVER("Queued %d outputs on pipeline %d\n",
|
||||
count, i);
|
||||
|
|
Loading…
Reference in a new issue