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x86: remove mach_apic.h

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Spread mach_apic.h definitions into genapic.h. (with some knock-on effects
on smp.h and apic.h.)

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar 2009-01-28 17:55:37 +01:00
parent 7c20dcc545
commit 1dcdd3d15e
22 changed files with 175 additions and 207 deletions
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2
arch/x86/include/asm/apic.h
View file

@ -215,7 +215,7 @@ static inline void disable_local_APIC(void) { }
#define SET_APIC_ID(x) (apic->set_apic_id(x))
#else
static inline unsigned default_get_apic_id(unsigned long x)
static inline unsigned default_get_apic_id(unsigned long x)
{
unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));

139
arch/x86/include/asm/genapic.h
View file

@ -120,4 +120,143 @@ static inline void default_wait_for_init_deassert(atomic_t *deassert)
return;
}
extern void generic_bigsmp_probe(void);
#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/smp.h>
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
static inline const struct cpumask *default_target_cpus(void)
{
#ifdef CONFIG_SMP
return cpu_online_mask;
#else
return cpumask_of(0);
#endif
}
DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
static inline unsigned int read_apic_id(void)
{
unsigned int reg;
reg = *(u32 *)(APIC_BASE + APIC_ID);
return apic->get_apic_id(reg);
}
#ifdef CONFIG_X86_64
extern void default_setup_apic_routing(void);
#else
/*
* Set up the logical destination ID.
*
* Intel recommends to set DFR, LDR and TPR before enabling
* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
* document number 292116). So here it goes...
*/
extern void default_init_apic_ldr(void);
static inline int default_apic_id_registered(void)
{
return physid_isset(read_apic_id(), phys_cpu_present_map);
}
static inline unsigned int
default_cpu_mask_to_apicid(const struct cpumask *cpumask)
{
return cpumask_bits(cpumask)[0];
}
static inline unsigned int
default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
const struct cpumask *andmask)
{
unsigned long mask1 = cpumask_bits(cpumask)[0];
unsigned long mask2 = cpumask_bits(andmask)[0];
unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
return (unsigned int)(mask1 & mask2 & mask3);
}
static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
{
return cpuid_apic >> index_msb;
}
static inline void default_setup_apic_routing(void)
{
#ifdef CONFIG_X86_IO_APIC
printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
"Flat", nr_ioapics);
#endif
}
extern int default_apicid_to_node(int logical_apicid);
#endif
static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
{
return physid_isset(apicid, bitmap);
}
static inline unsigned long default_check_apicid_present(int bit)
{
return physid_isset(bit, phys_cpu_present_map);
}
static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
{
return phys_map;
}
/* Mapping from cpu number to logical apicid */
static inline int default_cpu_to_logical_apicid(int cpu)
{
return 1 << cpu;
}
static inline int __default_cpu_present_to_apicid(int mps_cpu)
{
if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
else
return BAD_APICID;
}
static inline int
__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
{
return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
}
#ifdef CONFIG_X86_32
static inline int default_cpu_present_to_apicid(int mps_cpu)
{
return __default_cpu_present_to_apicid(mps_cpu);
}
static inline int
default_check_phys_apicid_present(int boot_cpu_physical_apicid)
{
return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
}
#else
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
#endif
static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
{
return physid_mask_of_physid(phys_apicid);
}
#endif /* CONFIG_X86_LOCAL_APIC */
#endif /* _ASM_X86_GENAPIC_64_H */

144
arch/x86/include/asm/mach-default/mach_apic.h
View file

@ -1,144 +0,0 @@
#ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
#define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/smp.h>
#define APIC_DFR_VALUE (APIC_DFR_FLAT)
static inline const struct cpumask *default_target_cpus(void)
{
#ifdef CONFIG_SMP
return cpu_online_mask;
#else
return cpumask_of(0);
#endif
}
#ifdef CONFIG_X86_64
#include <asm/genapic.h>
#define read_apic_id() (apic->get_apic_id(apic_read(APIC_ID)))
extern void default_setup_apic_routing(void);
#else
/*
* Set up the logical destination ID.
*
* Intel recommends to set DFR, LDR and TPR before enabling
* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
* document number 292116). So here it goes...
*/
static inline void default_init_apic_ldr(void)
{
unsigned long val;
apic_write(APIC_DFR, APIC_DFR_VALUE);
val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
apic_write(APIC_LDR, val);
}
static inline int default_apic_id_registered(void)
{
return physid_isset(read_apic_id(), phys_cpu_present_map);
}
static inline unsigned int
default_cpu_mask_to_apicid(const struct cpumask *cpumask)
{
return cpumask_bits(cpumask)[0];
}
static inline unsigned int
default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
const struct cpumask *andmask)
{
unsigned long mask1 = cpumask_bits(cpumask)[0];
unsigned long mask2 = cpumask_bits(andmask)[0];
unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
return (unsigned int)(mask1 & mask2 & mask3);
}
static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
{
return cpuid_apic >> index_msb;
}
static inline void default_setup_apic_routing(void)
{
#ifdef CONFIG_X86_IO_APIC
printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
"Flat", nr_ioapics);
#endif
}
static inline int default_apicid_to_node(int logical_apicid)
{
#ifdef CONFIG_SMP
return apicid_2_node[hard_smp_processor_id()];
#else
return 0;
#endif
}
#endif
static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
{
return physid_isset(apicid, bitmap);
}
static inline unsigned long default_check_apicid_present(int bit)
{
return physid_isset(bit, phys_cpu_present_map);
}
static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
{
return phys_map;
}
/* Mapping from cpu number to logical apicid */
static inline int default_cpu_to_logical_apicid(int cpu)
{
return 1 << cpu;
}
static inline int __default_cpu_present_to_apicid(int mps_cpu)
{
if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
else
return BAD_APICID;
}
static inline int
__default_check_phys_apicid_present(int boot_cpu_physical_apicid)
{
return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
}
#ifdef CONFIG_X86_32
static inline int default_cpu_present_to_apicid(int mps_cpu)
{
return __default_cpu_present_to_apicid(mps_cpu);
}
static inline int
default_check_phys_apicid_present(int boot_cpu_physical_apicid)
{
return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
}
#else
extern int default_cpu_present_to_apicid(int mps_cpu);
extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
#endif
static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
{
return physid_mask_of_physid(phys_apicid);
}
#endif /* CONFIG_X86_LOCAL_APIC */
#endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */

8
arch/x86/include/asm/mach-generic/mach_apic.h
View file

@ -1,8 +0,0 @@
#ifndef _ASM_X86_MACH_GENERIC_MACH_APIC_H
#define _ASM_X86_MACH_GENERIC_MACH_APIC_H
#include <asm/genapic.h>
extern void generic_bigsmp_probe(void);
#endif /* _ASM_X86_MACH_GENERIC_MACH_APIC_H */

19
arch/x86/include/asm/smp.h
View file

@ -173,8 +173,6 @@ extern int safe_smp_processor_id(void);
#endif
#include <asm/genapic.h>
#ifdef CONFIG_X86_LOCAL_APIC
#ifndef CONFIG_X86_64
@ -184,26 +182,9 @@ static inline int logical_smp_processor_id(void)
return GET_APIC_LOGICAL_ID(*(u32 *)(APIC_BASE + APIC_LDR));
}
static inline unsigned int read_apic_id(void)
{
unsigned int reg;
reg = *(u32 *)(APIC_BASE + APIC_ID);
return apic->get_apic_id(reg);
}
#endif
# if defined(APIC_DEFINITION) || defined(CONFIG_X86_64)
extern int hard_smp_processor_id(void);
# else
static inline int hard_smp_processor_id(void)
{
/* we don't want to mark this access volatile - bad code generation */
return read_apic_id();
}
# endif /* APIC_DEFINITION */
#else /* CONFIG_X86_LOCAL_APIC */

14
arch/x86/kernel/acpi/boot.c
View file

@ -42,10 +42,6 @@
#include <asm/mpspec.h>
#include <asm/smp.h>
#ifdef CONFIG_X86_LOCAL_APIC
# include <mach_apic.h>
#endif
static int __initdata acpi_force = 0;
u32 acpi_rsdt_forced;
#ifdef CONFIG_ACPI
@ -56,15 +52,7 @@ int acpi_disabled = 1;
EXPORT_SYMBOL(acpi_disabled);
#ifdef CONFIG_X86_64
#include <asm/proto.h>
#else /* X86 */
#ifdef CONFIG_X86_LOCAL_APIC
#include <mach_apic.h>
#endif /* CONFIG_X86_LOCAL_APIC */
# include <asm/proto.h>
#endif /* X86 */
#define BAD_MADT_ENTRY(entry, end) ( \

22
arch/x86/kernel/apic.c
View file

@ -49,7 +49,6 @@
#include <asm/i8259.h>
#include <asm/smp.h>
#include <mach_apic.h>
#include <mach_ipi.h>
/*
@ -1910,11 +1909,30 @@ void __cpuinit generic_processor_info(int apicid, int version)
set_cpu_present(cpu, true);
}
#ifdef CONFIG_X86_64
int hard_smp_processor_id(void)
{
return read_apic_id();
}
void default_init_apic_ldr(void)
{
unsigned long val;
apic_write(APIC_DFR, APIC_DFR_VALUE);
val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
apic_write(APIC_LDR, val);
}
#ifdef CONFIG_X86_32
int default_apicid_to_node(int logical_apicid)
{
#ifdef CONFIG_SMP
return apicid_2_node[hard_smp_processor_id()];
#else
return 0;
#endif
}
#endif
/*

2
arch/x86/kernel/cpu/addon_cpuid_features.c
View file

@ -7,7 +7,7 @@
#include <asm/pat.h>
#include <asm/processor.h>
#include <mach_apic.h>
#include <asm/genapic.h>
struct cpuid_bit {
u16 feature;

2
arch/x86/kernel/cpu/amd.c
View file

@ -12,7 +12,7 @@
# include <asm/cacheflush.h>
#endif
#include <mach_apic.h>
#include <asm/genapic.h>
#include "cpu.h"

2
arch/x86/kernel/cpu/common.c
View file

@ -26,7 +26,7 @@
#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
#include <asm/genapic.h>
#include <asm/genapic.h>
#include <asm/uv/uv.h>
#endif

2
arch/x86/kernel/cpu/intel.c
View file

@ -24,7 +24,7 @@
#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
#include <asm/genapic.h>
#endif
static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)

2
arch/x86/kernel/io_apic.c
View file

@ -63,7 +63,7 @@
#include <asm/uv/uv_irq.h>
#include <mach_ipi.h>
#include <mach_apic.h>
#include <asm/genapic.h>
#define __apicdebuginit(type) static type __init

2
arch/x86/kernel/ipi.c
View file

@ -19,7 +19,7 @@
#include <asm/proto.h>
#ifdef CONFIG_X86_32
#include <mach_apic.h>
#include <asm/genapic.h>
#include <mach_ipi.h>
/*

2
arch/x86/kernel/irq_32.c
View file

@ -231,7 +231,7 @@ unsigned int do_IRQ(struct pt_regs *regs)
}
#ifdef CONFIG_HOTPLUG_CPU
#include <mach_apic.h>
#include <asm/genapic.h>
/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
void fixup_irqs(void)

3
arch/x86/kernel/mpparse.c
View file

@ -29,8 +29,7 @@
#include <asm/setup.h>
#include <asm/smp.h>
#include <mach_apic.h>
#include <asm/genapic.h>
/*
* Checksum an MP configuration block.
*/

2
arch/x86/kernel/setup.c
View file

@ -97,7 +97,7 @@
#include <asm/mmu_context.h>
#include <asm/proto.h>
#include <mach_apic.h>
#include <asm/genapic.h>
#include <asm/paravirt.h>
#include <asm/hypervisor.h>

2
arch/x86/kernel/smp.c
View file

@ -27,7 +27,7 @@
#include <asm/mmu_context.h>
#include <asm/proto.h>
#include <mach_ipi.h>
#include <mach_apic.h>
#include <asm/genapic.h>
/*
* Some notes on x86 processor bugs affecting SMP operation:
*

2
arch/x86/kernel/smpboot.c
View file

@ -65,7 +65,7 @@
#include <asm/uv/uv.h>
#include <linux/mc146818rtc.h>
#include <mach_apic.h>
#include <asm/genapic.h>
#include <smpboot_hooks.h>
#ifdef CONFIG_X86_32

2
arch/x86/kernel/tlb_uv.c
View file

@ -20,7 +20,7 @@
#include <asm/tsc.h>
#include <asm/irq_vectors.h>
#include <mach_apic.h>
#include <asm/genapic.h>
static struct bau_control **uv_bau_table_bases __read_mostly;
static int uv_bau_retry_limit __read_mostly;

2
arch/x86/kernel/visws_quirks.c
View file

@ -34,7 +34,7 @@
#include <mach_ipi.h>
#include "mach_apic.h"
#include <asm/genapic.h>
#include <linux/kernel_stat.h>

2
arch/x86/mach-generic/default.c
View file

@ -12,7 +12,7 @@
#include <linux/string.h>
#include <linux/smp.h>
#include <linux/init.h>
#include <asm/mach-default/mach_apic.h>
#include <asm/genapic.h>
#include <asm/mach-default/mach_ipi.h>
static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)

5
arch/x86/mach-generic/probe.c
View file

@ -154,8 +154,3 @@ int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
}
return 0;
}
int hard_smp_processor_id(void)
{
return apic->get_apic_id(*(unsigned long *)(APIC_BASE+APIC_ID));
}