pinctrl: sirf: move sgpio lock into state container
Instead of referring to a global static variable for the sgpio locking, use the state container to contain the lock. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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7414b0993c
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1dfe0d159d
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@ -39,10 +39,9 @@ struct sirfsoc_gpio_bank {
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struct sirfsoc_gpio_chip {
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struct of_mm_gpio_chip chip;
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struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
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spinlock_t lock;
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};
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static DEFINE_SPINLOCK(sgpio_lock);
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static struct sirfsoc_pin_group *sirfsoc_pin_groups;
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static int sirfsoc_pingrp_cnt;
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@ -427,13 +426,13 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)
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offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
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spin_lock_irqsave(&sgpio_lock, flags);
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spin_lock_irqsave(&sgpio->lock, flags);
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val = readl(sgpio->chip.regs + offset);
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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spin_unlock_irqrestore(&sgpio->lock, flags);
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}
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static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
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@ -445,14 +444,14 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
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offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
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spin_lock_irqsave(&sgpio_lock, flags);
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spin_lock_irqsave(&sgpio->lock, flags);
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val = readl(sgpio->chip.regs + offset);
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val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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spin_unlock_irqrestore(&sgpio->lock, flags);
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}
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static void sirfsoc_gpio_irq_mask(struct irq_data *d)
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@ -475,14 +474,14 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
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offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
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spin_lock_irqsave(&sgpio_lock, flags);
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spin_lock_irqsave(&sgpio->lock, flags);
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val = readl(sgpio->chip.regs + offset);
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val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
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val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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spin_unlock_irqrestore(&sgpio->lock, flags);
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}
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static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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@ -496,7 +495,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
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spin_lock_irqsave(&sgpio_lock, flags);
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spin_lock_irqsave(&sgpio->lock, flags);
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val = readl(sgpio->chip.regs + offset);
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val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
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@ -533,7 +532,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
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writel(val, sgpio->chip.regs + offset);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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spin_unlock_irqrestore(&sgpio->lock, flags);
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return 0;
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}
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@ -697,11 +696,11 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
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offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
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spin_lock_irqsave(&sgpio_lock, flags);
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spin_lock_irqsave(&sgpio->lock, flags);
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sirfsoc_gpio_set_output(sgpio, bank, offset, value);
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spin_unlock_irqrestore(&sgpio_lock, flags);
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spin_unlock_irqrestore(&sgpio->lock, flags);
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return 0;
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}
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@ -793,6 +792,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
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sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
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if (!sgpio)
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return -ENOMEM;
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spin_lock_init(&sgpio->lock);
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regs = of_iomap(np, 0);
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if (!regs)
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