Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts: drivers/net/bonding/bond_3ad.h drivers/net/bonding/bond_main.c Two minor conflicts in bonding, both of which were overlapping changes. Signed-off-by: David S. Miller <davem@davemloft.net>wifi-calibration
David S. Miller
commit
1e8d6421cf
|
|
@ -3,7 +3,8 @@ Date: Nov 2010
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|||
Contact: Kay Sievers <kay.sievers@vrfy.org>
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||||
Description:
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||||
Shows the list of currently configured
|
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console devices, like 'tty1 ttyS0'.
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tty devices used for the console,
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like 'tty1 ttyS0'.
|
||||
The last entry in the file is the active
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||||
device connected to /dev/console.
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The file supports poll() to detect virtual
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|
|
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@ -13,6 +13,9 @@ Required properties:
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- #address-cells: should be one. The cell is the slot id.
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- #size-cells: should be zero.
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- at least one slot node
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- clock-names: tuple listing input clock names.
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Required elements: "mci_clk"
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- clocks: phandles to input clocks.
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The node contains child nodes for each slot that the platform uses
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@ -24,6 +27,8 @@ mmc0: mmc@f0008000 {
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interrupts = <12 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "mci_clk";
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clocks = <&mci0_clk>;
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[ child node definitions...]
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};
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|
|
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@ -0,0 +1,58 @@
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STMicroelectronics SoC DWMAC glue layer controller
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The device node has following properties.
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Required properties:
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- compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
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"st,stid127-dwmac".
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- reg : Offset of the glue configuration register map in system
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configuration regmap pointed by st,syscon property and size.
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- reg-names : Should be "sti-ethconf".
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- st,syscon : Should be phandle to system configuration node which
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encompases this glue registers.
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- st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
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wired up in from different sources. One via TXCLK pin and other via CLK_125
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pin. This wiring is totally board dependent. However the retiming glue
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logic should be configured accordingly. Possible values for this property
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"txclk" - if 125Mhz clock is wired up via txclk line.
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"clk_125" - if 125Mhz clock is wired up via clk_125 line.
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This property is only valid for Giga bit setup( GMII, RGMII), and it is
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un-used for non-giga bit (MII and RMII) setups. Also note that internal
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clockgen can not generate stable 125Mhz clock.
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- st,ext-phyclk: This boolean property indicates who is generating the clock
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for tx and rx. This property is only valid for RMII case where the clock can
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be generated from the MAC or PHY.
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- clock-names: should be "sti-ethclk".
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- clocks: Should point to ethernet clockgen which can generate phyclk.
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Example:
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ethernet0: dwmac@fe810000 {
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device_type = "network";
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compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
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reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
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reg-names = "stmmaceth", "sti-ethconf";
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interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
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interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
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phy-mode = "mii";
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st,syscon = <&syscfg_rear>;
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snps,pbl = <32>;
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snps,mixed-burst;
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resets = <&softreset STIH416_ETH0_SOFTRESET>;
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reset-names = "stmmaceth";
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pinctrl-0 = <&pinctrl_mii0>;
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pinctrl-names = "default";
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clocks = <&CLK_S_GMAC0_PHY>;
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clock-names = "stmmaceth";
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};
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@ -0,0 +1,47 @@
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Binding for TI bq2415x Li-Ion Charger
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Required properties:
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- compatible: Should contain one of the following:
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* "ti,bq24150"
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* "ti,bq24150"
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* "ti,bq24150a"
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* "ti,bq24151"
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* "ti,bq24151a"
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* "ti,bq24152"
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* "ti,bq24153"
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* "ti,bq24153a"
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* "ti,bq24155"
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* "ti,bq24156"
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* "ti,bq24156a"
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* "ti,bq24158"
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- reg: integer, i2c address of the device.
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- ti,current-limit: integer, initial maximum current charger can pull
|
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from power supply in mA.
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- ti,weak-battery-voltage: integer, weak battery voltage threshold in mV.
|
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The chip will use slow precharge if battery voltage
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is below this value.
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- ti,battery-regulation-voltage: integer, maximum charging voltage in mV.
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- ti,charge-current: integer, maximum charging current in mA.
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- ti,termination-current: integer, charge will be terminated when current in
|
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constant-voltage phase drops below this value (in mA).
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- ti,resistor-sense: integer, value of sensing resistor in milliohm.
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Optional properties:
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- ti,usb-charger-detection: phandle to usb charger detection device.
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(required for auto mode)
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|
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Example from Nokia N900:
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|
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bq24150a {
|
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compatible = "ti,bq24150a";
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reg = <0x6b>;
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|
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ti,current-limit = <100>;
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ti,weak-battery-voltage = <3400>;
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ti,battery-regulation-voltage = <4200>;
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ti,charge-current = <650>;
|
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ti,termination-current = <100>;
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||||
ti,resistor-sense = <68>;
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ti,usb-charger-detection = <&isp1704>;
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};
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|
|
@ -5,6 +5,9 @@ Required properties:
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- reg: Address and length of the register set for the device
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- interrupts: Should contain spi interrupt
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- cs-gpios: chipselects
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- clock-names: tuple listing input clock names.
|
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Required elements: "spi_clk"
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- clocks: phandles to input clocks.
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|
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Example:
|
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|
|
@ -14,6 +17,8 @@ spi1: spi@fffcc000 {
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interrupts = <13 4 5>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&spi1_clk>;
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clock-names = "spi_clk";
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cs-gpios = <&pioB 3 0>;
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status = "okay";
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|
|
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|
|
@ -8,6 +8,7 @@ ad Avionic Design GmbH
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|||
adi Analog Devices, Inc.
|
||||
aeroflexgaisler Aeroflex Gaisler AB
|
||||
ak Asahi Kasei Corp.
|
||||
allwinner Allwinner Technology Co., Ltd.
|
||||
altr Altera Corp.
|
||||
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
|
||||
amstaos AMS-Taos Inc.
|
||||
|
|
@ -40,6 +41,7 @@ gmt Global Mixed-mode Technology, Inc.
|
|||
gumstix Gumstix, Inc.
|
||||
haoyu Haoyu Microelectronic Co. Ltd.
|
||||
hisilicon Hisilicon Limited.
|
||||
honeywell Honeywell
|
||||
hp Hewlett Packard
|
||||
ibm International Business Machines (IBM)
|
||||
idt Integrated Device Technologies, Inc.
|
||||
|
|
@ -55,6 +57,7 @@ maxim Maxim Integrated Products
|
|||
microchip Microchip Technology Inc.
|
||||
mosaixtech Mosaix Technologies, Inc.
|
||||
national National Semiconductor
|
||||
neonode Neonode Inc.
|
||||
nintendo Nintendo
|
||||
nvidia NVIDIA
|
||||
nxp NXP Semiconductors
|
||||
|
|
@ -64,7 +67,7 @@ phytec PHYTEC Messtechnik GmbH
|
|||
picochip Picochip Ltd
|
||||
powervr PowerVR (deprecated, use img)
|
||||
qca Qualcomm Atheros, Inc.
|
||||
qcom Qualcomm, Inc.
|
||||
qcom Qualcomm Technologies, Inc
|
||||
ralink Mediatek/Ralink Technology Corp.
|
||||
ramtron Ramtron International
|
||||
realtek Realtek Semiconductor Corp.
|
||||
|
|
@ -78,6 +81,7 @@ silabs Silicon Laboratories
|
|||
simtek
|
||||
sirf SiRF Technology, Inc.
|
||||
snps Synopsys, Inc.
|
||||
spansion Spansion Inc.
|
||||
st STMicroelectronics
|
||||
ste ST-Ericsson
|
||||
stericsson ST-Ericsson
|
||||
|
|
|
|||
|
|
@ -8,8 +8,8 @@ reason, the kernel code must instantiate I2C devices explicitly. There are
|
|||
several ways to achieve this, depending on the context and requirements.
|
||||
|
||||
|
||||
Method 1: Declare the I2C devices by bus number
|
||||
-----------------------------------------------
|
||||
Method 1a: Declare the I2C devices by bus number
|
||||
------------------------------------------------
|
||||
|
||||
This method is appropriate when the I2C bus is a system bus as is the case
|
||||
for many embedded systems. On such systems, each I2C bus has a number
|
||||
|
|
@ -51,6 +51,43 @@ The devices will be automatically unbound and destroyed when the I2C bus
|
|||
they sit on goes away (if ever.)
|
||||
|
||||
|
||||
Method 1b: Declare the I2C devices via devicetree
|
||||
-------------------------------------------------
|
||||
|
||||
This method has the same implications as method 1a. The declaration of I2C
|
||||
devices is here done via devicetree as subnodes of the master controller.
|
||||
|
||||
Example:
|
||||
|
||||
i2c1: i2c@400a0000 {
|
||||
/* ... master properties skipped ... */
|
||||
clock-frequency = <100000>;
|
||||
|
||||
flash@50 {
|
||||
compatible = "atmel,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
pca9532: gpio@60 {
|
||||
compatible = "nxp,pca9532";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
Here, two devices are attached to the bus using a speed of 100kHz. For
|
||||
additional properties which might be needed to set up the device, please refer
|
||||
to its devicetree documentation in Documentation/devicetree/bindings/.
|
||||
|
||||
|
||||
Method 1c: Declare the I2C devices via ACPI
|
||||
-------------------------------------------
|
||||
|
||||
ACPI can also describe I2C devices. There is special documentation for this
|
||||
which is currently located at Documentation/acpi/enumeration.txt.
|
||||
|
||||
|
||||
Method 2: Instantiate the devices explicitly
|
||||
--------------------------------------------
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||||
|
||||
|
|
|
|||
|
|
@ -1,45 +0,0 @@
|
|||
The 3Com Etherlink Plus (3c505) driver.
|
||||
|
||||
This driver now uses DMA. There is currently no support for PIO operation.
|
||||
The default DMA channel is 6; this is _not_ autoprobed, so you must
|
||||
make sure you configure it correctly. If loading the driver as a
|
||||
module, you can do this with "modprobe 3c505 dma=n". If the driver is
|
||||
linked statically into the kernel, you must either use an "ether="
|
||||
statement on the command line, or change the definition of ELP_DMA in 3c505.h.
|
||||
|
||||
The driver will warn you if it has to fall back on the compiled in
|
||||
default DMA channel.
|
||||
|
||||
If no base address is given at boot time, the driver will autoprobe
|
||||
ports 0x300, 0x280 and 0x310 (in that order). If no IRQ is given, the driver
|
||||
will try to probe for it.
|
||||
|
||||
The driver can be used as a loadable module.
|
||||
|
||||
Theoretically, one instance of the driver can now run multiple cards,
|
||||
in the standard way (when loading a module, say "modprobe 3c505
|
||||
io=0x300,0x340 irq=10,11 dma=6,7" or whatever). I have not tested
|
||||
this, though.
|
||||
|
||||
The driver may now support revision 2 hardware; the dependency on
|
||||
being able to read the host control register has been removed. This
|
||||
is also untested, since I don't have a suitable card.
|
||||
|
||||
Known problems:
|
||||
I still see "DMA upload timed out" messages from time to time. These
|
||||
seem to be fairly non-fatal though.
|
||||
The card is old and slow.
|
||||
|
||||
To do:
|
||||
Improve probe/setup code
|
||||
Test multicast and promiscuous operation
|
||||
|
||||
Authors:
|
||||
The driver is mainly written by Craig Southeren, email
|
||||
<craigs@ineluki.apana.org.au>.
|
||||
Parts of the driver (adapting the driver to 1.1.4+ kernels,
|
||||
IRQ/address detection, some changes) and this README by
|
||||
Juha Laiho <jlaiho@ichaos.nullnet.fi>.
|
||||
DMA mode, more fixes, etc, by Philip Blundell <pjb27@cam.ac.uk>
|
||||
Multicard support, Software configurable DMA, etc., by
|
||||
Christopher Collins <ccollins@pcug.org.au>
|
||||
|
|
@ -75,14 +75,26 @@ Before the controller can make use of the PHY, it has to get a reference to
|
|||
it. This framework provides the following APIs to get a reference to the PHY.
|
||||
|
||||
struct phy *phy_get(struct device *dev, const char *string);
|
||||
struct phy *phy_optional_get(struct device *dev, const char *string);
|
||||
struct phy *devm_phy_get(struct device *dev, const char *string);
|
||||
struct phy *devm_phy_optional_get(struct device *dev, const char *string);
|
||||
|
||||
phy_get and devm_phy_get can be used to get the PHY. In the case of dt boot,
|
||||
the string arguments should contain the phy name as given in the dt data and
|
||||
in the case of non-dt boot, it should contain the label of the PHY.
|
||||
The only difference between the two APIs is that devm_phy_get associates the
|
||||
device with the PHY using devres on successful PHY get. On driver detach,
|
||||
release function is invoked on the the devres data and devres data is freed.
|
||||
phy_get, phy_optional_get, devm_phy_get and devm_phy_optional_get can
|
||||
be used to get the PHY. In the case of dt boot, the string arguments
|
||||
should contain the phy name as given in the dt data and in the case of
|
||||
non-dt boot, it should contain the label of the PHY. The two
|
||||
devm_phy_get associates the device with the PHY using devres on
|
||||
successful PHY get. On driver detach, release function is invoked on
|
||||
the the devres data and devres data is freed. phy_optional_get and
|
||||
devm_phy_optional_get should be used when the phy is optional. These
|
||||
two functions will never return -ENODEV, but instead returns NULL when
|
||||
the phy cannot be found.
|
||||
|
||||
It should be noted that NULL is a valid phy reference. All phy
|
||||
consumer calls on the NULL phy become NOPs. That is the release calls,
|
||||
the phy_init() and phy_exit() calls, and phy_power_on() and
|
||||
phy_power_off() calls are all NOP when applied to a NULL phy. The NULL
|
||||
phy is useful in devices for handling optional phy devices.
|
||||
|
||||
5. Releasing a reference to the PHY
|
||||
|
||||
|
|
|
|||
|
|
@ -543,7 +543,22 @@ SPI MASTER METHODS
|
|||
queuing transfers that arrive in the meantime. When the driver is
|
||||
finished with this message, it must call
|
||||
spi_finalize_current_message() so the subsystem can issue the next
|
||||
transfer. This may sleep.
|
||||
message. This may sleep.
|
||||
|
||||
master->transfer_one(struct spi_master *master, struct spi_device *spi,
|
||||
struct spi_transfer *transfer)
|
||||
The subsystem calls the driver to transfer a single transfer while
|
||||
queuing transfers that arrive in the meantime. When the driver is
|
||||
finished with this transfer, it must call
|
||||
spi_finalize_current_transfer() so the subsystem can issue the next
|
||||
transfer. This may sleep. Note: transfer_one and transfer_one_message
|
||||
are mutually exclusive; when both are set, the generic subsystem does
|
||||
not call your transfer_one callback.
|
||||
|
||||
Return values:
|
||||
negative errno: error
|
||||
0: transfer is finished
|
||||
1: transfer is still in progress
|
||||
|
||||
DEPRECATED METHODS
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ help. Contact the Chinese maintainer if this translation is outdated
|
|||
or if there is a problem with the translation.
|
||||
|
||||
Maintainer: Will Deacon <will.deacon@arm.com>
|
||||
Chinese maintainer: Fu Wei <tekkamanninja@gmail.com>
|
||||
Chinese maintainer: Fu Wei <wefu@redhat.com>
|
||||
---------------------------------------------------------------------
|
||||
Documentation/arm64/booting.txt 的中文翻译
|
||||
|
||||
|
|
@ -16,9 +16,9 @@ Documentation/arm64/booting.txt 的中文翻译
|
|||
译存在问题，请联系中文版维护者。
|
||||
|
||||
英文版维护者： Will Deacon <will.deacon@arm.com>
|
||||
中文版维护者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版翻译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版校译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版维护者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
中文版翻译者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
中文版校译者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
|
||||
以下为正文
|
||||
---------------------------------------------------------------------
|
||||
|
|
@ -64,8 +64,8 @@ RAM，或可能使用对这个设备已知的 RAM 信息，还可能使用任何
|
|||
|
||||
必要性: 强制
|
||||
|
||||
设备树数据块（dtb）大小必须不大于 2 MB，且位于从内核映像起始算起第一个
|
||||
512MB 内的 2MB 边界上。这使得内核可以通过初始页表中的单个节描述符来
|
||||
设备树数据块（dtb）必须 8 字节对齐，并位于从内核映像起始算起第一个 512MB
|
||||
内，且不得跨越 2MB 对齐边界。这使得内核可以通过初始页表中的单个节描述符来
|
||||
映射此数据块。
|
||||
|
||||
|
||||
|
|
@ -84,13 +84,23 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内
|
|||
|
||||
必要性: 强制
|
||||
|
||||
已解压的内核映像包含一个 32 字节的头，内容如下：
|
||||
已解压的内核映像包含一个 64 字节的头，内容如下：
|
||||
|
||||
u32 magic = 0x14000008; /* 跳转到 stext, 小端 */
|
||||
u32 res0 = 0; /* 保留 */
|
||||
u32 code0; /* 可执行代码 */
|
||||
u32 code1; /* 可执行代码 */
|
||||
u64 text_offset; /* 映像装载偏移 */
|
||||
u64 res0 = 0; /* 保留 */
|
||||
u64 res1 = 0; /* 保留 */
|
||||
u64 res2 = 0; /* 保留 */
|
||||
u64 res3 = 0; /* 保留 */
|
||||
u64 res4 = 0; /* 保留 */
|
||||
u32 magic = 0x644d5241; /* 魔数, 小端, "ARM\x64" */
|
||||
u32 res5 = 0; /* 保留 */
|
||||
|
||||
|
||||
映像头注释：
|
||||
|
||||
- code0/code1 负责跳转到 stext.
|
||||
|
||||
映像必须位于系统 RAM 起始处的特定偏移（当前是 0x80000）。系统 RAM
|
||||
的起始地址必须是以 2MB 对齐的。
|
||||
|
|
@ -118,9 +128,9 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内
|
|||
外部高速缓存（如果存在）必须配置并禁用。
|
||||
|
||||
- 架构计时器
|
||||
CNTFRQ 必须设定为计时器的频率。
|
||||
如果在 EL1 模式下进入内核，则 CNTHCTL_EL2 中的 EL1PCTEN (bit 0)
|
||||
必须置位。
|
||||
CNTFRQ 必须设定为计时器的频率，且 CNTVOFF 必须设定为对所有 CPU
|
||||
都一致的值。如果在 EL1 模式下进入内核，则 CNTHCTL_EL2 中的
|
||||
EL1PCTEN (bit 0) 必须置位。
|
||||
|
||||
- 一致性
|
||||
通过内核启动的所有 CPU 在内核入口地址上必须处于相同的一致性域中。
|
||||
|
|
@ -131,23 +141,40 @@ AArch64 内核当前没有提供自解压代码，因此如果使用了压缩内
|
|||
在进入内核映像的异常级中，所有构架中可写的系统寄存器必须通过软件
|
||||
在一个更高的异常级别下初始化，以防止在 未知 状态下运行。
|
||||
|
||||
以上对于 CPU 模式、高速缓存、MMU、架构计时器、一致性、系统寄存器的
|
||||
必要条件描述适用于所有 CPU。所有 CPU 必须在同一异常级别跳入内核。
|
||||
|
||||
引导装载程序必须在每个 CPU 处于以下状态时跳入内核入口：
|
||||
|
||||
- 主 CPU 必须直接跳入内核映像的第一条指令。通过此 CPU 传递的设备树
|
||||
数据块必须在每个 CPU 节点中包含以下内容：
|
||||
|
||||
1、‘enable-method’属性。目前，此字段支持的值仅为字符串“spin-table”。
|
||||
|
||||
2、‘cpu-release-addr’标识一个 64-bit、初始化为零的内存位置。
|
||||
数据块必须在每个 CPU 节点中包含一个 ‘enable-method’ 属性，所
|
||||
支持的 enable-method 请见下文。
|
||||
|
||||
引导装载程序必须生成这些设备树属性，并在跳入内核入口之前将其插入
|
||||
数据块。
|
||||
|
||||
- 任何辅助 CPU 必须在内存保留区（通过设备树中的 /memreserve/ 域传递
|
||||
- enable-method 为 “spin-table” 的 CPU 必须在它们的 CPU
|
||||
节点中包含一个 ‘cpu-release-addr’ 属性。这个属性标识了一个
|
||||
64 位自然对齐且初始化为零的内存位置。
|
||||
|
||||
这些 CPU 必须在内存保留区（通过设备树中的 /memreserve/ 域传递
|
||||
给内核）中自旋于内核之外，轮询它们的 cpu-release-addr 位置（必须
|
||||
包含在保留区中）。可通过插入 wfe 指令来降低忙循环开销，而主 CPU 将
|
||||
发出 sev 指令。当对 cpu-release-addr 所指位置的读取操作返回非零值
|
||||
时，CPU 必须直接跳入此值所指向的地址。
|
||||
时，CPU 必须跳入此值所指向的地址。此值为一个单独的 64 位小端值，
|
||||
因此 CPU 须在跳转前将所读取的值转换为其本身的端模式。
|
||||
|
||||
- enable-method 为 “psci” 的 CPU 保持在内核外（比如，在
|
||||
memory 节点中描述为内核空间的内存区外，或在通过设备树 /memreserve/
|
||||
域中描述为内核保留区的空间中）。内核将会发起在 ARM 文档（编号
|
||||
ARM DEN 0022A：用于 ARM 上的电源状态协调接口系统软件）中描述的
|
||||
CPU_ON 调用来将 CPU 带入内核。
|
||||
|
||||
*译者注:到文档翻译时，此文档已更新为 ARM DEN 0022B。
|
||||
|
||||
设备树必须包含一个 ‘psci’ 节点，请参考以下文档：
|
||||
Documentation/devicetree/bindings/arm/psci.txt
|
||||
|
||||
|
||||
- 辅助 CPU 通用寄存器设置
|
||||
x0 = 0 (保留，将来可能使用)
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ help. Contact the Chinese maintainer if this translation is outdated
|
|||
or if there is a problem with the translation.
|
||||
|
||||
Maintainer: Catalin Marinas <catalin.marinas@arm.com>
|
||||
Chinese maintainer: Fu Wei <tekkamanninja@gmail.com>
|
||||
Chinese maintainer: Fu Wei <wefu@redhat.com>
|
||||
---------------------------------------------------------------------
|
||||
Documentation/arm64/memory.txt 的中文翻译
|
||||
|
||||
|
|
@ -16,9 +16,9 @@ Documentation/arm64/memory.txt 的中文翻译
|
|||
译存在问题，请联系中文版维护者。
|
||||
|
||||
英文版维护者： Catalin Marinas <catalin.marinas@arm.com>
|
||||
中文版维护者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版翻译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版校译者： 傅炜 Fu Wei <tekkamanninja@gmail.com>
|
||||
中文版维护者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
中文版翻译者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
中文版校译者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
|
||||
以下为正文
|
||||
---------------------------------------------------------------------
|
||||
|
|
@ -41,7 +41,7 @@ AArch64 Linux 使用页大小为 4KB 的 3 级转换表配置，对于用户和
|
|||
TTBR1 中，且从不写入 TTBR0。
|
||||
|
||||
|
||||
AArch64 Linux 内存布局：
|
||||
AArch64 Linux 在页大小为 4KB 时的内存布局：
|
||||
|
||||
起始地址 结束地址 大小 用途
|
||||
-----------------------------------------------------------------------
|
||||
|
|
@ -55,15 +55,42 @@ ffffffbc00000000 ffffffbdffffffff 8GB vmemmap
|
|||
|
||||
ffffffbe00000000 ffffffbffbbfffff ~8GB [防护页，未来用于 vmmemap]
|
||||
|
||||
ffffffbffbc00000 ffffffbffbdfffff 2MB earlyprintk 设备
|
||||
|
||||
ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O 空间
|
||||
|
||||
ffffffbbffff0000 ffffffbcffffffff ~2MB [防护页]
|
||||
ffffffbffbe10000 ffffffbcffffffff ~2MB [防护页]
|
||||
|
||||
ffffffbffc000000 ffffffbfffffffff 64MB 模块
|
||||
|
||||
ffffffc000000000 ffffffffffffffff 256GB 内核逻辑内存映射
|
||||
|
||||
|
||||
AArch64 Linux 在页大小为 64KB 时的内存布局：
|
||||
|
||||
起始地址 结束地址 大小 用途
|
||||
-----------------------------------------------------------------------
|
||||
0000000000000000 000003ffffffffff 4TB 用户空间
|
||||
|
||||
fffffc0000000000 fffffdfbfffeffff ~2TB vmalloc
|
||||
|
||||
fffffdfbffff0000 fffffdfbffffffff 64KB [防护页]
|
||||
|
||||
fffffdfc00000000 fffffdfdffffffff 8GB vmemmap
|
||||
|
||||
fffffdfe00000000 fffffdfffbbfffff ~8GB [防护页，未来用于 vmmemap]
|
||||
|
||||
fffffdfffbc00000 fffffdfffbdfffff 2MB earlyprintk 设备
|
||||
|
||||
fffffdfffbe00000 fffffdfffbe0ffff 64KB PCI I/O 空间
|
||||
|
||||
fffffdfffbe10000 fffffdfffbffffff ~2MB [防护页]
|
||||
|
||||
fffffdfffc000000 fffffdffffffffff 64MB 模块
|
||||
|
||||
fffffe0000000000 ffffffffffffffff 2TB 内核逻辑内存映射
|
||||
|
||||
|
||||
4KB 页大小的转换表查找：
|
||||
|
||||
+--------+--------+--------+--------+--------+--------+--------+--------+
|
||||
|
|
@ -91,3 +118,10 @@ ffffffc000000000 ffffffffffffffff 256GB 内核逻辑内存映射
|
|||
| | +--------------------------> [41:29] L2 索引 (仅使用 38:29 )
|
||||
| +-------------------------------> [47:42] L1 索引 (未使用)
|
||||
+-------------------------------------------------> [63] TTBR0/1
|
||||
|
||||
当使用 KVM 时, 管理程序（hypervisor）在 EL2 中通过相对内核虚拟地址的
|
||||
一个固定偏移来映射内核页（内核虚拟地址的高 24 位设为零）:
|
||||
|
||||
起始地址 结束地址 大小 用途
|
||||
-----------------------------------------------------------------------
|
||||
0000004000000000 0000007fffffffff 256GB 在 HYP 中映射的内核对象
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
Chinese translated version of Documentation/arm64/tagged-pointers.txt
|
||||
|
||||
If you have any comment or update to the content, please contact the
|
||||
original document maintainer directly. However, if you have a problem
|
||||
communicating in English you can also ask the Chinese maintainer for
|
||||
help. Contact the Chinese maintainer if this translation is outdated
|
||||
or if there is a problem with the translation.
|
||||
|
||||
Maintainer: Will Deacon <will.deacon@arm.com>
|
||||
Chinese maintainer: Fu Wei <wefu@redhat.com>
|
||||
---------------------------------------------------------------------
|
||||
Documentation/arm64/tagged-pointers.txt 的中文翻译
|
||||
|
||||
如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文
|
||||
交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻
|
||||
译存在问题，请联系中文版维护者。
|
||||
|
||||
英文版维护者： Will Deacon <will.deacon@arm.com>
|
||||
中文版维护者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
中文版翻译者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
中文版校译者： 傅炜 Fu Wei <wefu@redhat.com>
|
||||
|
||||
以下为正文
|
||||
---------------------------------------------------------------------
|
||||
Linux 在 AArch64 中带标记的虚拟地址
|
||||
=================================
|
||||
|
||||
作者: Will Deacon <will.deacon@arm.com>
|
||||
日期: 2013 年 06 月 12 日
|
||||
|
||||
本文档简述了在 AArch64 地址转换系统中提供的带标记的虚拟地址及其在
|
||||
AArch64 Linux 中的潜在用途。
|
||||
|
||||
内核提供的地址转换表配置使通过 TTBR0 完成的虚拟地址转换（即用户空间
|
||||
映射），其虚拟地址的最高 8 位（63:56）会被转换硬件所忽略。这种机制
|
||||
让这些位可供应用程序自由使用，其注意事项如下：
|
||||
|
||||
(1) 内核要求所有传递到 EL1 的用户空间地址带有 0x00 标记。
|
||||
这意味着任何携带用户空间虚拟地址的系统调用（syscall）
|
||||
参数 *必须* 在陷入内核前使它们的最高字节被清零。
|
||||
|
||||
(2) 非零标记在传递信号时不被保存。这意味着在应用程序中利用了
|
||||
标记的信号处理函数无法依赖 siginfo_t 的用户空间虚拟
|
||||
地址所携带的包含其内部域信息的标记。此规则的一个例外是
|
||||
当信号是在调试观察点的异常处理程序中产生的，此时标记的
|
||||
信息将被保存。
|
||||
|
||||
(3) 当使用带标记的指针时需特别留心，因为仅对两个虚拟地址
|
||||
的高字节，C 编译器很可能无法判断它们是不同的。
|
||||
|
||||
此构架会阻止对带标记的 PC 指针的利用，因此在异常返回时，其高字节
|
||||
将被设置成一个为 “55” 的扩展符。
|
||||
15
MAINTAINERS
15
MAINTAINERS
|
|
@ -2373,7 +2373,7 @@ F: include/linux/cpufreq.h
|
|||
|
||||
CPU FREQUENCY DRIVERS - ARM BIG LITTLE
|
||||
M: Viresh Kumar <viresh.kumar@linaro.org>
|
||||
M: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
|
||||
M: Sudeep Holla <sudeep.holla@arm.com>
|
||||
L: cpufreq@vger.kernel.org
|
||||
L: linux-pm@vger.kernel.org
|
||||
W: http://www.arm.com/products/processors/technologies/biglittleprocessing.php
|
||||
|
|
@ -2863,7 +2863,7 @@ M: Jani Nikula <jani.nikula@linux.intel.com>
|
|||
L: intel-gfx@lists.freedesktop.org
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
Q: http://patchwork.freedesktop.org/project/intel-gfx/
|
||||
T: git git://people.freedesktop.org/~danvet/drm-intel
|
||||
T: git git://anongit.freedesktop.org/drm-intel
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/i915/
|
||||
F: include/drm/i915*
|
||||
|
|
@ -3330,6 +3330,17 @@ S: Maintained
|
|||
F: include/linux/netfilter_bridge/
|
||||
F: net/bridge/
|
||||
|
||||
ETHERNET PHY LIBRARY
|
||||
M: Florian Fainelli <f.fainelli@gmail.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: include/linux/phy.h
|
||||
F: include/linux/phy_fixed.h
|
||||
F: drivers/net/phy/
|
||||
F: Documentation/networking/phy.txt
|
||||
F: drivers/of/of_mdio.c
|
||||
F: drivers/of/of_net.c
|
||||
|
||||
EXT2 FILE SYSTEM
|
||||
M: Jan Kara <jack@suse.cz>
|
||||
L: linux-ext4@vger.kernel.org
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 14
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Shuffling Zombie Juror
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb
|
|||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb
|
||||
# sama5d3
|
||||
dtb-$(CONFIG_ARCH_AT91) += at91-sama5d3_xplained.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
|
||||
dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
|
||||
|
|
|
|||
|
|
@ -0,0 +1,229 @@
|
|||
/*
|
||||
* at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
|
||||
*
|
||||
* Copyright (C) 2014 Atmel,
|
||||
* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "sama5d36.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMA5D3 Xplained";
|
||||
compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x10000000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
mmc0: mmc@f0000000 {
|
||||
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <8>;
|
||||
cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f0004000 {
|
||||
cs-gpios = <&pioD 13 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
can0: can@f000c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@f0014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f0028000 {
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart0: serial@f001c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@f0020000 {
|
||||
pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart0: serial@f0024000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc1: mmc@f8000000 {
|
||||
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioE 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
spi1: spi@f8008000 {
|
||||
cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioD 16 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adc0: adc@f8018000 {
|
||||
pinctrl-0 = <
|
||||
&pinctrl_adc0_adtrg
|
||||
&pinctrl_adc0_ad0
|
||||
&pinctrl_adc0_ad1
|
||||
&pinctrl_adc0_ad2
|
||||
&pinctrl_adc0_ad3
|
||||
&pinctrl_adc0_ad4
|
||||
&pinctrl_adc0_ad5
|
||||
&pinctrl_adc0_ad6
|
||||
&pinctrl_adc0_ad7
|
||||
&pinctrl_adc0_ad8
|
||||
&pinctrl_adc0_ad9
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c2: i2c@f801c000 {
|
||||
dmas = <0>, <0>; /* Do not use DMA for i2c2 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb1: ethernet@f802c000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dbgu: serial@ffffee00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fffff200 {
|
||||
board {
|
||||
pinctrl_mmc0_cd: mmc0_cd {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
|
||||
pinctrl_mmc1_cd: mmc1_cd {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
|
||||
pinctrl_usba_vbus: usba_vbus {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PE9, conflicts with A9 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
main: mainck {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@60000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
atmel,has-pmecc;
|
||||
atmel,pmecc-cap = <4>;
|
||||
atmel,pmecc-sector-size = <512>;
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
bootloader@40000 {
|
||||
label = "bootloader";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
bootloaderenv@c0000 {
|
||||
label = "bootloader env";
|
||||
reg = <0xc0000 0xc0000>;
|
||||
};
|
||||
|
||||
dtb@180000 {
|
||||
label = "device tree";
|
||||
reg = <0x180000 0x80000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb0: gadget@00500000 {
|
||||
atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; /* PE9, conflicts with A9 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usba_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: ohci@00600000 {
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0
|
||||
&pioE 3 GPIO_ACTIVE_LOW
|
||||
&pioE 4 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: ehci@00700000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
bp3 {
|
||||
label = "PB_USER";
|
||||
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <0x104>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
d2 {
|
||||
label = "d2";
|
||||
gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
d3 {
|
||||
label = "d3";
|
||||
gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -523,7 +523,7 @@
|
|||
};
|
||||
|
||||
i2c0: i2c@fff88000 {
|
||||
compatible = "atmel,at91sam9263-i2c";
|
||||
compatible = "atmel,at91sam9260-i2c";
|
||||
reg = <0xfff88000 0x100>;
|
||||
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -124,6 +124,10 @@
|
|||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -52,12 +52,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
codec: spdif-transmitter {
|
||||
compatible = "linux,spdif-dit";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
|
||||
};
|
||||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
|
|
@ -111,7 +105,7 @@
|
|||
};
|
||||
|
||||
pinctrl_hummingboard_spdif: hummingboard-spdif {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
|
||||
};
|
||||
|
||||
pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
|
||||
|
|
@ -142,6 +136,8 @@
|
|||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -46,12 +46,6 @@
|
|||
};
|
||||
};
|
||||
|
||||
codec: spdif-transmitter {
|
||||
compatible = "linux,spdif-dit";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cubox_i_spdif>;
|
||||
};
|
||||
|
||||
sound-spdif {
|
||||
compatible = "fsl,imx-audio-spdif";
|
||||
model = "imx-spdif";
|
||||
|
|
@ -89,7 +83,7 @@
|
|||
};
|
||||
|
||||
pinctrl_cubox_i_spdif: cubox-i-spdif {
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
|
||||
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
|
||||
};
|
||||
|
||||
pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
|
||||
|
|
@ -121,6 +115,8 @@
|
|||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cubox_i_spdif>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1228,7 +1228,7 @@
|
|||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00600000 0x100000>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
|
||||
<&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -188,7 +188,6 @@
|
|||
msp2: msp@80117000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&msp2_default_mode>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
msp3: msp@80125000 {
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ CONFIG_ARCH_OMAP3=y
|
|||
CONFIG_ARCH_OMAP4=y
|
||||
CONFIG_SOC_OMAP5=y
|
||||
CONFIG_SOC_AM33XX=y
|
||||
CONFIG_SOC_DRA7XX=y
|
||||
CONFIG_SOC_AM43XX=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SOCFPGA=y
|
||||
|
|
|
|||
|
|
@ -212,6 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
|
|||
static inline void __flush_icache_all(void)
|
||||
{
|
||||
__flush_icache_preferred();
|
||||
dsb();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -120,13 +120,16 @@
|
|||
/*
|
||||
* 2nd stage PTE definitions for LPAE.
|
||||
*/
|
||||
#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
|
||||
#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
|
||||
#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
|
||||
#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
|
||||
#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
|
||||
#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
|
||||
#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
|
||||
#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
|
||||
#define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
|
||||
#define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
|
||||
|
||||
#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
|
||||
#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
|
||||
#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
|
||||
|
||||
#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
|
||||
|
||||
/*
|
||||
* Hyp-mode PL2 PTE definitions for LPAE.
|
||||
|
|
|
|||
|
|
@ -37,18 +37,9 @@
|
|||
|
||||
static inline void dsb_sev(void)
|
||||
{
|
||||
#if __LINUX_ARM_ARCH__ >= 7
|
||||
__asm__ __volatile__ (
|
||||
"dsb ishst\n"
|
||||
SEV
|
||||
);
|
||||
#else
|
||||
__asm__ __volatile__ (
|
||||
"mcr p15, 0, %0, c7, c10, 4\n"
|
||||
SEV
|
||||
: : "r" (0)
|
||||
);
|
||||
#endif
|
||||
|
||||
dsb(ishst);
|
||||
__asm__(SEV);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -731,7 +731,7 @@ static void __init request_standard_resources(const struct machine_desc *mdesc)
|
|||
kernel_data.end = virt_to_phys(_end - 1);
|
||||
|
||||
for_each_memblock(memory, region) {
|
||||
res = memblock_virt_alloc_low(sizeof(*res), 0);
|
||||
res = memblock_virt_alloc(sizeof(*res), 0);
|
||||
res->name = "System RAM";
|
||||
res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
|
||||
res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ config ARCH_HI3xxx
|
|||
select CLKSRC_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_ARM_SCU
|
||||
select HAVE_ARM_TWD
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select HAVE_SMP
|
||||
select PINCTRL
|
||||
select PINCTRL_SINGLE
|
||||
|
|
|
|||
|
|
@ -482,6 +482,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
|
|
|||
|
|
@ -266,6 +266,9 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
|
|
|||
|
|
@ -236,8 +236,6 @@ void __init imx6q_pm_init(void)
|
|||
regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
|
||||
IMX6Q_GPR1_GINT);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
suspend_set_ops(&imx6q_pm_ops);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,6 @@ config ARCH_MOXART
|
|||
bool "MOXA ART SoC" if ARCH_MULTI_V4T
|
||||
select CPU_FA526
|
||||
select ARM_DMA_MEM_BUFFERABLE
|
||||
select DMA_OF
|
||||
select USE_OF
|
||||
select CLKSRC_OF
|
||||
select CLKSRC_MMIO
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ config SOC_OMAP5
|
|||
select ARM_GIC
|
||||
select CPU_V7
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if LOCAL_TIMERS
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select HAVE_SMP
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
select ARM_ERRATA_798181 if SMP
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@
|
|||
|
||||
#include <mach/gumstix.h>
|
||||
#include <mach/mfp-pxa25x.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <linux/platform_data/video-pxafb.h>
|
||||
|
||||
#include "generic.h"
|
||||
|
|
|
|||
|
|
@ -14,6 +14,8 @@
|
|||
#ifndef ASM_ARCH_BALLOON3_H
|
||||
#define ASM_ARCH_BALLOON3_H
|
||||
|
||||
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
|
||||
|
||||
enum balloon3_features {
|
||||
BALLOON3_FEATURE_OHCI,
|
||||
BALLOON3_FEATURE_MMC,
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#ifndef __ASM_ARCH_CORGI_H
|
||||
#define __ASM_ARCH_CORGI_H 1
|
||||
|
||||
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
|
||||
|
||||
/*
|
||||
* Corgi (Non Standard) GPIO Definitions
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@
|
|||
#ifndef CSB726_H
|
||||
#define CSB726_H
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
#define CSB726_GPIO_IRQ_LAN 52
|
||||
#define CSB726_GPIO_IRQ_SM501 53
|
||||
#define CSB726_GPIO_MMC_DETECT 100
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/* BTRESET - Reset line to Bluetooth module, active low signal. */
|
||||
#define GPIO_GUMSTIX_BTRESET 7
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
* IDP hardware.
|
||||
*/
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
#define IDP_FLASH_PHYS (PXA_CS0_PHYS)
|
||||
#define IDP_ALT_FLASH_PHYS (PXA_CS1_PHYS)
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@
|
|||
#ifndef _INCLUDE_PALMLD_H_
|
||||
#define _INCLUDE_PALMLD_H_
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/** HERE ARE GPIOs **/
|
||||
|
||||
/* GPIOs */
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#ifndef _INCLUDE_PALMT5_H_
|
||||
#define _INCLUDE_PALMT5_H_
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/** HERE ARE GPIOs **/
|
||||
|
||||
/* GPIOs */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
#ifndef _INCLUDE_PALMTC_H_
|
||||
#define _INCLUDE_PALMTC_H_
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/** HERE ARE GPIOs **/
|
||||
|
||||
/* GPIOs */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
#ifndef _INCLUDE_PALMTX_H_
|
||||
#define _INCLUDE_PALMTX_H_
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/** HERE ARE GPIOs **/
|
||||
|
||||
/* GPIOs */
|
||||
|
|
|
|||
|
|
@ -23,6 +23,8 @@
|
|||
* Definitions of CPU card resources only
|
||||
*/
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/* phyCORE-PXA270 (PCM027) Interrupts */
|
||||
#define PCM027_IRQ(x) (IRQ_BOARD_START + (x))
|
||||
#define PCM027_BTDET_IRQ PCM027_IRQ(0)
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
*/
|
||||
|
||||
#include <mach/pcm027.h>
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/*
|
||||
* definitions relevant only when the PCM-990
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#ifndef __ASM_ARCH_POODLE_H
|
||||
#define __ASM_ARCH_POODLE_H 1
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/*
|
||||
* GPIOs
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -15,8 +15,8 @@
|
|||
#define __ASM_ARCH_SPITZ_H 1
|
||||
#endif
|
||||
|
||||
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */
|
||||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
/* Spitz/Akita GPIOs */
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@
|
|||
#ifndef _ASM_ARCH_TOSA_H_
|
||||
#define _ASM_ARCH_TOSA_H_ 1
|
||||
|
||||
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
|
||||
|
||||
/* TOSA Chip selects */
|
||||
#define TOSA_LCDC_PHYS PXA_CS4_PHYS
|
||||
/* Internel Scoop */
|
||||
|
|
|
|||
|
|
@ -10,6 +10,8 @@
|
|||
#ifndef _TRIPEPS4_H_
|
||||
#define _TRIPEPS4_H_
|
||||
|
||||
#include "irqs.h" /* PXA_GPIO_TO_IRQ */
|
||||
|
||||
/* physical memory regions */
|
||||
#define TRIZEPS4_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */
|
||||
#define TRIZEPS4_DISK_PHYS (PXA_CS1_PHYS) /* Disk On Chip region */
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ config ARCH_SHMOBILE_MULTI
|
|||
select CPU_V7
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_ARM_SCU if SMP
|
||||
select HAVE_ARM_TWD if LOCAL_TIMERS
|
||||
select HAVE_ARM_TWD if SMP
|
||||
select HAVE_SMP
|
||||
select ARM_GIC
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
|
||||
|
|
@ -41,6 +42,18 @@
|
|||
|
||||
void __iomem *zynq_scu_base;
|
||||
|
||||
/**
|
||||
* zynq_memory_init - Initialize special memory
|
||||
*
|
||||
* We need to stop things allocating the low memory as DMA can't work in
|
||||
* the 1st 512K of memory.
|
||||
*/
|
||||
static void __init zynq_memory_init(void)
|
||||
{
|
||||
if (!__pa(PAGE_OFFSET))
|
||||
memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir));
|
||||
}
|
||||
|
||||
static struct platform_device zynq_cpuidle_device = {
|
||||
.name = "cpuidle-zynq",
|
||||
};
|
||||
|
|
@ -117,5 +130,6 @@ DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
|
|||
.init_machine = zynq_init_machine,
|
||||
.init_time = zynq_timer_init,
|
||||
.dt_compat = zynq_dt_match,
|
||||
.reserve = zynq_memory_init,
|
||||
.restart = zynq_system_reset,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
|
|||
|
||||
struct mem_type {
|
||||
pteval_t prot_pte;
|
||||
pteval_t prot_pte_s2;
|
||||
pmdval_t prot_l1;
|
||||
pmdval_t prot_sect;
|
||||
unsigned int domain;
|
||||
|
|
|
|||
|
|
@ -232,12 +232,16 @@ __setup("noalign", noalign_setup);
|
|||
#endif /* ifdef CONFIG_CPU_CP15 / else */
|
||||
|
||||
#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
|
||||
#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
|
||||
#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
|
||||
|
||||
static struct mem_type mem_types[] = {
|
||||
[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
|
||||
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
|
||||
L_PTE_SHARED,
|
||||
.prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
|
||||
s2_policy(L_PTE_S2_MT_DEV_SHARED) |
|
||||
L_PTE_SHARED,
|
||||
.prot_l1 = PMD_TYPE_TABLE,
|
||||
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
|
||||
.domain = DOMAIN_IO,
|
||||
|
|
@ -508,7 +512,8 @@ static void __init build_mem_type_table(void)
|
|||
cp = &cache_policies[cachepolicy];
|
||||
vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
|
||||
s2_pgprot = cp->pte_s2;
|
||||
hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
|
||||
hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
|
||||
s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
|
||||
|
||||
/*
|
||||
* ARMv6 and above have extended page tables.
|
||||
|
|
|
|||
|
|
@ -208,7 +208,6 @@ __v6_setup:
|
|||
mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
|
||||
mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
|
||||
mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
|
||||
mcr p15, 0, r0, c2, c0, 2 @ TTB control register
|
||||
|
|
@ -218,6 +217,8 @@ __v6_setup:
|
|||
ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
|
||||
mcr p15, 0, r8, c2, c0, 1 @ load TTB1
|
||||
#endif /* CONFIG_MMU */
|
||||
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
|
||||
@ complete invalidations
|
||||
adr r5, v6_crval
|
||||
ldmia r5, {r5, r6}
|
||||
ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
|
||||
|
|
|
|||
|
|
@ -351,7 +351,6 @@ __v7_setup:
|
|||
|
||||
4: mov r10, #0
|
||||
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
||||
dsb
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
|
||||
v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
|
||||
|
|
@ -360,6 +359,7 @@ __v7_setup:
|
|||
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
|
||||
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
|
||||
#endif
|
||||
dsb @ Complete invalidations
|
||||
#ifndef CONFIG_ARM_THUMBEE
|
||||
mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
|
||||
and r0, r0, #(0xf << 12) @ ThumbEE enabled field
|
||||
|
|
|
|||
|
|
@ -148,6 +148,15 @@ struct kvm_arch_memory_slot {
|
|||
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
|
||||
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
|
||||
|
||||
/* Device Control API: ARM VGIC */
|
||||
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
|
||||
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
|
||||
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
|
||||
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
|
||||
#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
|
||||
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
|
||||
#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
|
||||
|
||||
/* KVM_IRQ_LINE irq field index values */
|
||||
#define KVM_ARM_IRQ_TYPE_SHIFT 24
|
||||
#define KVM_ARM_IRQ_TYPE_MASK 0xff
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ all: uImage vmlinux.elf
|
|||
|
||||
KBUILD_DEFCONFIG := atstk1002_defconfig
|
||||
|
||||
KBUILD_CFLAGS += -pipe -fno-builtin -mno-pic
|
||||
KBUILD_CFLAGS += -pipe -fno-builtin -mno-pic -D__linux__
|
||||
KBUILD_AFLAGS += -mrelax -mno-pic
|
||||
KBUILD_CFLAGS_MODULE += -mno-relax
|
||||
LDFLAGS_vmlinux += --relax
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#define FRAM_VERSION "1.0"
|
||||
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/io.h>
|
||||
|
|
|
|||
|
|
@ -17,5 +17,6 @@ generic-y += scatterlist.h
|
|||
generic-y += sections.h
|
||||
generic-y += topology.h
|
||||
generic-y += trace_clock.h
|
||||
generic-y += vga.h
|
||||
generic-y += xor.h
|
||||
generic-y += hash.h
|
||||
|
|
|
|||
|
|
@ -295,6 +295,8 @@ extern void __iounmap(void __iomem *addr);
|
|||
#define iounmap(addr) \
|
||||
__iounmap(addr)
|
||||
|
||||
#define ioremap_wc ioremap_nocache
|
||||
|
||||
#define cached(addr) P1SEGADDR(addr)
|
||||
#define uncached(addr) P2SEGADDR(addr)
|
||||
|
||||
|
|
|
|||
|
|
@ -134,6 +134,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
|
|||
}
|
||||
|
||||
extern int dma_set_mask(struct device *dev, u64 dma_mask);
|
||||
extern int __dma_set_mask(struct device *dev, u64 dma_mask);
|
||||
|
||||
#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL)
|
||||
|
||||
|
|
|
|||
|
|
@ -172,10 +172,20 @@ struct eeh_ops {
|
|||
};
|
||||
|
||||
extern struct eeh_ops *eeh_ops;
|
||||
extern int eeh_subsystem_enabled;
|
||||
extern bool eeh_subsystem_enabled;
|
||||
extern raw_spinlock_t confirm_error_lock;
|
||||
extern int eeh_probe_mode;
|
||||
|
||||
static inline bool eeh_enabled(void)
|
||||
{
|
||||
return eeh_subsystem_enabled;
|
||||
}
|
||||
|
||||
static inline void eeh_set_enable(bool mode)
|
||||
{
|
||||
eeh_subsystem_enabled = mode;
|
||||
}
|
||||
|
||||
#define EEH_PROBE_MODE_DEV (1<<0) /* From PCI device */
|
||||
#define EEH_PROBE_MODE_DEVTREE (1<<1) /* From device tree */
|
||||
|
||||
|
|
@ -246,7 +256,7 @@ void eeh_remove_device(struct pci_dev *);
|
|||
* If this macro yields TRUE, the caller relays to eeh_check_failure()
|
||||
* which does further tests out of line.
|
||||
*/
|
||||
#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
|
||||
#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
|
||||
|
||||
/*
|
||||
* Reads from a device which has been isolated by EEH will return
|
||||
|
|
@ -257,6 +267,13 @@ void eeh_remove_device(struct pci_dev *);
|
|||
|
||||
#else /* !CONFIG_EEH */
|
||||
|
||||
static inline bool eeh_enabled(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline void eeh_set_enable(bool mode) { }
|
||||
|
||||
static inline int eeh_init(void)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
|
|||
unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
#ifdef CONFIG_PPC64
|
||||
return __pte(pte_update(mm, addr, ptep, ~0UL, 1));
|
||||
return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1));
|
||||
#else
|
||||
return __pte(pte_update(ptep, ~0UL, 0));
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -77,6 +77,7 @@ struct iommu_table {
|
|||
#ifdef CONFIG_IOMMU_API
|
||||
struct iommu_group *it_group;
|
||||
#endif
|
||||
void (*set_bypass)(struct iommu_table *tbl, bool enable);
|
||||
};
|
||||
|
||||
/* Pure 2^n version of get_order */
|
||||
|
|
|
|||
|
|
@ -195,6 +195,7 @@ extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
|
|||
static inline unsigned long pte_update(struct mm_struct *mm,
|
||||
unsigned long addr,
|
||||
pte_t *ptep, unsigned long clr,
|
||||
unsigned long set,
|
||||
int huge)
|
||||
{
|
||||
#ifdef PTE_ATOMIC_UPDATES
|
||||
|
|
@ -205,14 +206,15 @@ static inline unsigned long pte_update(struct mm_struct *mm,
|
|||
andi. %1,%0,%6\n\
|
||||
bne- 1b \n\
|
||||
andc %1,%0,%4 \n\
|
||||
or %1,%1,%7\n\
|
||||
stdcx. %1,0,%3 \n\
|
||||
bne- 1b"
|
||||
: "=&r" (old), "=&r" (tmp), "=m" (*ptep)
|
||||
: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
|
||||
: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
|
||||
: "cc" );
|
||||
#else
|
||||
unsigned long old = pte_val(*ptep);
|
||||
*ptep = __pte(old & ~clr);
|
||||
*ptep = __pte((old & ~clr) | set);
|
||||
#endif
|
||||
/* huge pages use the old page table lock */
|
||||
if (!huge)
|
||||
|
|
@ -231,9 +233,9 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
|
|||
{
|
||||
unsigned long old;
|
||||
|
||||
if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
|
||||
if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
|
||||
return 0;
|
||||
old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
|
||||
old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
|
||||
return (old & _PAGE_ACCESSED) != 0;
|
||||
}
|
||||
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
||||
|
|
@ -252,7 +254,7 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
|
|||
if ((pte_val(*ptep) & _PAGE_RW) == 0)
|
||||
return;
|
||||
|
||||
pte_update(mm, addr, ptep, _PAGE_RW, 0);
|
||||
pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
|
||||
}
|
||||
|
||||
static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
|
||||
|
|
@ -261,7 +263,7 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
|
|||
if ((pte_val(*ptep) & _PAGE_RW) == 0)
|
||||
return;
|
||||
|
||||
pte_update(mm, addr, ptep, _PAGE_RW, 1);
|
||||
pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -284,14 +286,14 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
|
|||
static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
|
||||
unsigned long addr, pte_t *ptep)
|
||||
{
|
||||
unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
|
||||
unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
|
||||
return __pte(old);
|
||||
}
|
||||
|
||||
static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t * ptep)
|
||||
{
|
||||
pte_update(mm, addr, ptep, ~0UL, 0);
|
||||
pte_update(mm, addr, ptep, ~0UL, 0, 0);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -506,7 +508,9 @@ extern int pmdp_set_access_flags(struct vm_area_struct *vma,
|
|||
|
||||
extern unsigned long pmd_hugepage_update(struct mm_struct *mm,
|
||||
unsigned long addr,
|
||||
pmd_t *pmdp, unsigned long clr);
|
||||
pmd_t *pmdp,
|
||||
unsigned long clr,
|
||||
unsigned long set);
|
||||
|
||||
static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
|
||||
unsigned long addr, pmd_t *pmdp)
|
||||
|
|
@ -515,7 +519,7 @@ static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
|
|||
|
||||
if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
|
||||
return 0;
|
||||
old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED);
|
||||
old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
|
||||
return ((old & _PAGE_ACCESSED) != 0);
|
||||
}
|
||||
|
||||
|
|
@ -542,7 +546,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
|
|||
if ((pmd_val(*pmdp) & _PAGE_RW) == 0)
|
||||
return;
|
||||
|
||||
pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW);
|
||||
pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW, 0);
|
||||
}
|
||||
|
||||
#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
|
||||
|
|
|
|||
|
|
@ -75,12 +75,34 @@ static inline pte_t pte_mknuma(pte_t pte)
|
|||
return pte;
|
||||
}
|
||||
|
||||
#define ptep_set_numa ptep_set_numa
|
||||
static inline void ptep_set_numa(struct mm_struct *mm, unsigned long addr,
|
||||
pte_t *ptep)
|
||||
{
|
||||
if ((pte_val(*ptep) & _PAGE_PRESENT) == 0)
|
||||
VM_BUG_ON(1);
|
||||
|
||||
pte_update(mm, addr, ptep, _PAGE_PRESENT, _PAGE_NUMA, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
#define pmd_numa pmd_numa
|
||||
static inline int pmd_numa(pmd_t pmd)
|
||||
{
|
||||
return pte_numa(pmd_pte(pmd));
|
||||
}
|
||||
|
||||
#define pmdp_set_numa pmdp_set_numa
|
||||
static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
|
||||
pmd_t *pmdp)
|
||||
{
|
||||
if ((pmd_val(*pmdp) & _PAGE_PRESENT) == 0)
|
||||
VM_BUG_ON(1);
|
||||
|
||||
pmd_hugepage_update(mm, addr, pmdp, _PAGE_PRESENT, _PAGE_NUMA);
|
||||
return;
|
||||
}
|
||||
|
||||
#define pmd_mknonnuma pmd_mknonnuma
|
||||
static inline pmd_t pmd_mknonnuma(pmd_t pmd)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#ifdef __powerpc64__
|
||||
|
||||
extern char __start_interrupts[];
|
||||
extern char __end_interrupts[];
|
||||
|
||||
extern char __prom_init_toc_start[];
|
||||
|
|
@ -21,6 +22,17 @@ static inline int in_kernel_text(unsigned long addr)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline int overlaps_interrupt_vector_text(unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
unsigned long real_start, real_end;
|
||||
real_start = __start_interrupts - _stext;
|
||||
real_end = __end_interrupts - _stext;
|
||||
|
||||
return start < (unsigned long)__va(real_end) &&
|
||||
(unsigned long)__va(real_start) < end;
|
||||
}
|
||||
|
||||
static inline int overlaps_kernel_text(unsigned long start, unsigned long end)
|
||||
{
|
||||
return start < (unsigned long)__init_end &&
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@
|
|||
#ifdef __KERNEL__
|
||||
|
||||
/* Default link addresses for the vDSOs */
|
||||
#define VDSO32_LBASE 0x100000
|
||||
#define VDSO64_LBASE 0x100000
|
||||
#define VDSO32_LBASE 0x0
|
||||
#define VDSO64_LBASE 0x0
|
||||
|
||||
/* Default map addresses for 32bit vDSO */
|
||||
#define VDSO32_MBASE VDSO32_LBASE
|
||||
#define VDSO32_MBASE 0x100000
|
||||
|
||||
#define VDSO_VERSION_STRING LINUX_2.6.15
|
||||
|
||||
|
|
|
|||
|
|
@ -191,12 +191,10 @@ EXPORT_SYMBOL(dma_direct_ops);
|
|||
|
||||
#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
|
||||
|
||||
int dma_set_mask(struct device *dev, u64 dma_mask)
|
||||
int __dma_set_mask(struct device *dev, u64 dma_mask)
|
||||
{
|
||||
struct dma_map_ops *dma_ops = get_dma_ops(dev);
|
||||
|
||||
if (ppc_md.dma_set_mask)
|
||||
return ppc_md.dma_set_mask(dev, dma_mask);
|
||||
if ((dma_ops != NULL) && (dma_ops->set_dma_mask != NULL))
|
||||
return dma_ops->set_dma_mask(dev, dma_mask);
|
||||
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
|
||||
|
|
@ -204,6 +202,12 @@ int dma_set_mask(struct device *dev, u64 dma_mask)
|
|||
*dev->dma_mask = dma_mask;
|
||||
return 0;
|
||||
}
|
||||
int dma_set_mask(struct device *dev, u64 dma_mask)
|
||||
{
|
||||
if (ppc_md.dma_set_mask)
|
||||
return ppc_md.dma_set_mask(dev, dma_mask);
|
||||
return __dma_set_mask(dev, dma_mask);
|
||||
}
|
||||
EXPORT_SYMBOL(dma_set_mask);
|
||||
|
||||
u64 dma_get_required_mask(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/pci.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/rbtree.h>
|
||||
#include <linux/reboot.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/export.h>
|
||||
|
|
@ -89,7 +90,7 @@
|
|||
/* Platform dependent EEH operations */
|
||||
struct eeh_ops *eeh_ops = NULL;
|
||||
|
||||
int eeh_subsystem_enabled;
|
||||
bool eeh_subsystem_enabled = false;
|
||||
EXPORT_SYMBOL(eeh_subsystem_enabled);
|
||||
|
||||
/*
|
||||
|
|
@ -364,7 +365,7 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
|
|||
|
||||
eeh_stats.total_mmio_ffs++;
|
||||
|
||||
if (!eeh_subsystem_enabled)
|
||||
if (!eeh_enabled())
|
||||
return 0;
|
||||
|
||||
if (!edev) {
|
||||
|
|
@ -747,6 +748,17 @@ int __exit eeh_ops_unregister(const char *name)
|
|||
return -EEXIST;
|
||||
}
|
||||
|
||||
static int eeh_reboot_notifier(struct notifier_block *nb,
|
||||
unsigned long action, void *unused)
|
||||
{
|
||||
eeh_set_enable(false);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block eeh_reboot_nb = {
|
||||
.notifier_call = eeh_reboot_notifier,
|
||||
};
|
||||
|
||||
/**
|
||||
* eeh_init - EEH initialization
|
||||
*
|
||||
|
|
@ -778,6 +790,14 @@ int eeh_init(void)
|
|||
if (machine_is(powernv) && cnt++ <= 0)
|
||||
return ret;
|
||||
|
||||
/* Register reboot notifier */
|
||||
ret = register_reboot_notifier(&eeh_reboot_nb);
|
||||
if (ret) {
|
||||
pr_warn("%s: Failed to register notifier (%d)\n",
|
||||
__func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* call platform initialization function */
|
||||
if (!eeh_ops) {
|
||||
pr_warning("%s: Platform EEH operation not found\n",
|
||||
|
|
@ -822,7 +842,7 @@ int eeh_init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
if (eeh_subsystem_enabled)
|
||||
if (eeh_enabled())
|
||||
pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n");
|
||||
else
|
||||
pr_warning("EEH: No capable adapters found\n");
|
||||
|
|
@ -897,7 +917,7 @@ void eeh_add_device_late(struct pci_dev *dev)
|
|||
struct device_node *dn;
|
||||
struct eeh_dev *edev;
|
||||
|
||||
if (!dev || !eeh_subsystem_enabled)
|
||||
if (!dev || !eeh_enabled())
|
||||
return;
|
||||
|
||||
pr_debug("EEH: Adding device %s\n", pci_name(dev));
|
||||
|
|
@ -1005,7 +1025,7 @@ void eeh_remove_device(struct pci_dev *dev)
|
|||
{
|
||||
struct eeh_dev *edev;
|
||||
|
||||
if (!dev || !eeh_subsystem_enabled)
|
||||
if (!dev || !eeh_enabled())
|
||||
return;
|
||||
edev = pci_dev_to_eeh_dev(dev);
|
||||
|
||||
|
|
@ -1045,7 +1065,7 @@ void eeh_remove_device(struct pci_dev *dev)
|
|||
|
||||
static int proc_eeh_show(struct seq_file *m, void *v)
|
||||
{
|
||||
if (0 == eeh_subsystem_enabled) {
|
||||
if (!eeh_enabled()) {
|
||||
seq_printf(m, "EEH Subsystem is globally disabled\n");
|
||||
seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -362,9 +362,13 @@ static void *eeh_rmv_device(void *data, void *userdata)
|
|||
*/
|
||||
if (!dev || (dev->hdr_type & PCI_HEADER_TYPE_BRIDGE))
|
||||
return NULL;
|
||||
|
||||
driver = eeh_pcid_get(dev);
|
||||
if (driver && driver->err_handler)
|
||||
return NULL;
|
||||
if (driver) {
|
||||
eeh_pcid_put(dev);
|
||||
if (driver->err_handler)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Remove it from PCI subsystem */
|
||||
pr_debug("EEH: Removing %s without EEH sensitive driver\n",
|
||||
|
|
|
|||
|
|
@ -1088,6 +1088,14 @@ int iommu_take_ownership(struct iommu_table *tbl)
|
|||
memset(tbl->it_map, 0xff, sz);
|
||||
iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
|
||||
|
||||
/*
|
||||
* Disable iommu bypass, otherwise the user can DMA to all of
|
||||
* our physical memory via the bypass window instead of just
|
||||
* the pages that has been explicitly mapped into the iommu
|
||||
*/
|
||||
if (tbl->set_bypass)
|
||||
tbl->set_bypass(tbl, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_take_ownership);
|
||||
|
|
@ -1102,6 +1110,10 @@ void iommu_release_ownership(struct iommu_table *tbl)
|
|||
/* Restore bit#0 set by iommu_init_table() */
|
||||
if (tbl->it_offset == 0)
|
||||
set_bit(0, tbl->it_map);
|
||||
|
||||
/* The kernel owns the device now, we can restore the iommu bypass */
|
||||
if (tbl->set_bypass)
|
||||
tbl->set_bypass(tbl, true);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iommu_release_ownership);
|
||||
|
||||
|
|
|
|||
|
|
@ -559,8 +559,13 @@ void exc_lvl_ctx_init(void)
|
|||
#ifdef CONFIG_PPC64
|
||||
cpu_nr = i;
|
||||
#else
|
||||
#ifdef CONFIG_SMP
|
||||
cpu_nr = get_hard_smp_processor_id(i);
|
||||
#else
|
||||
cpu_nr = 0;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
memset((void *)critirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
||||
tp = critirq_ctx[cpu_nr];
|
||||
tp->cpu = cpu_nr;
|
||||
|
|
|
|||
|
|
@ -196,7 +196,9 @@ int overlaps_crashkernel(unsigned long start, unsigned long size)
|
|||
|
||||
/* Values we need to export to the second kernel via the device tree. */
|
||||
static phys_addr_t kernel_end;
|
||||
static phys_addr_t crashk_base;
|
||||
static phys_addr_t crashk_size;
|
||||
static unsigned long long mem_limit;
|
||||
|
||||
static struct property kernel_end_prop = {
|
||||
.name = "linux,kernel-end",
|
||||
|
|
@ -207,7 +209,7 @@ static struct property kernel_end_prop = {
|
|||
static struct property crashk_base_prop = {
|
||||
.name = "linux,crashkernel-base",
|
||||
.length = sizeof(phys_addr_t),
|
||||
.value = &crashk_res.start,
|
||||
.value = &crashk_base
|
||||
};
|
||||
|
||||
static struct property crashk_size_prop = {
|
||||
|
|
@ -219,9 +221,11 @@ static struct property crashk_size_prop = {
|
|||
static struct property memory_limit_prop = {
|
||||
.name = "linux,memory-limit",
|
||||
.length = sizeof(unsigned long long),
|
||||
.value = &memory_limit,
|
||||
.value = &mem_limit,
|
||||
};
|
||||
|
||||
#define cpu_to_be_ulong __PASTE(cpu_to_be, BITS_PER_LONG)
|
||||
|
||||
static void __init export_crashk_values(struct device_node *node)
|
||||
{
|
||||
struct property *prop;
|
||||
|
|
@ -237,8 +241,9 @@ static void __init export_crashk_values(struct device_node *node)
|
|||
of_remove_property(node, prop);
|
||||
|
||||
if (crashk_res.start != 0) {
|
||||
crashk_base = cpu_to_be_ulong(crashk_res.start),
|
||||
of_add_property(node, &crashk_base_prop);
|
||||
crashk_size = resource_size(&crashk_res);
|
||||
crashk_size = cpu_to_be_ulong(resource_size(&crashk_res));
|
||||
of_add_property(node, &crashk_size_prop);
|
||||
}
|
||||
|
||||
|
|
@ -246,6 +251,7 @@ static void __init export_crashk_values(struct device_node *node)
|
|||
* memory_limit is required by the kexec-tools to limit the
|
||||
* crash regions to the actual memory used.
|
||||
*/
|
||||
mem_limit = cpu_to_be_ulong(memory_limit);
|
||||
of_update_property(node, &memory_limit_prop);
|
||||
}
|
||||
|
||||
|
|
@ -264,7 +270,7 @@ static int __init kexec_setup(void)
|
|||
of_remove_property(node, prop);
|
||||
|
||||
/* information needed by userspace when using default_machine_kexec */
|
||||
kernel_end = __pa(_end);
|
||||
kernel_end = cpu_to_be_ulong(__pa(_end));
|
||||
of_add_property(node, &kernel_end_prop);
|
||||
|
||||
export_crashk_values(node);
|
||||
|
|
|
|||
|
|
@ -369,6 +369,7 @@ void default_machine_kexec(struct kimage *image)
|
|||
|
||||
/* Values we need to export to the second kernel via the device tree. */
|
||||
static unsigned long htab_base;
|
||||
static unsigned long htab_size;
|
||||
|
||||
static struct property htab_base_prop = {
|
||||
.name = "linux,htab-base",
|
||||
|
|
@ -379,7 +380,7 @@ static struct property htab_base_prop = {
|
|||
static struct property htab_size_prop = {
|
||||
.name = "linux,htab-size",
|
||||
.length = sizeof(unsigned long),
|
||||
.value = &htab_size_bytes,
|
||||
.value = &htab_size,
|
||||
};
|
||||
|
||||
static int __init export_htab_values(void)
|
||||
|
|
@ -403,8 +404,9 @@ static int __init export_htab_values(void)
|
|||
if (prop)
|
||||
of_remove_property(node, prop);
|
||||
|
||||
htab_base = __pa(htab_address);
|
||||
htab_base = cpu_to_be64(__pa(htab_address));
|
||||
of_add_property(node, &htab_base_prop);
|
||||
htab_size = cpu_to_be64(htab_size_bytes);
|
||||
of_add_property(node, &htab_size_prop);
|
||||
|
||||
of_node_put(node);
|
||||
|
|
|
|||
|
|
@ -57,11 +57,14 @@ _GLOBAL(call_do_softirq)
|
|||
mtlr r0
|
||||
blr
|
||||
|
||||
/*
|
||||
* void call_do_irq(struct pt_regs *regs, struct thread_info *irqtp);
|
||||
*/
|
||||
_GLOBAL(call_do_irq)
|
||||
mflr r0
|
||||
stw r0,4(r1)
|
||||
lwz r10,THREAD+KSP_LIMIT(r2)
|
||||
addi r11,r3,THREAD_INFO_GAP
|
||||
addi r11,r4,THREAD_INFO_GAP
|
||||
stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
|
||||
mr r1,r4
|
||||
stw r10,8(r1)
|
||||
|
|
|
|||
|
|
@ -69,8 +69,8 @@ _GLOBAL(relocate)
|
|||
* R_PPC64_RELATIVE ones.
|
||||
*/
|
||||
mtctr r8
|
||||
5: lwz r0,12(9) /* ELF64_R_TYPE(reloc->r_info) */
|
||||
cmpwi r0,R_PPC64_RELATIVE
|
||||
5: ld r0,8(9) /* ELF64_R_TYPE(reloc->r_info) */
|
||||
cmpdi r0,R_PPC64_RELATIVE
|
||||
bne 6f
|
||||
ld r6,0(r9) /* reloc->r_offset */
|
||||
ld r0,16(r9) /* reloc->r_addend */
|
||||
|
|
|
|||
|
|
@ -247,7 +247,12 @@ static void __init exc_lvl_early_init(void)
|
|||
/* interrupt stacks must be in lowmem, we get that for free on ppc32
|
||||
* as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
|
||||
for_each_possible_cpu(i) {
|
||||
#ifdef CONFIG_SMP
|
||||
hw_cpu = get_hard_smp_processor_id(i);
|
||||
#else
|
||||
hw_cpu = 0;
|
||||
#endif
|
||||
|
||||
critirq_ctx[hw_cpu] = (struct thread_info *)
|
||||
__va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
|
||||
#ifdef CONFIG_BOOKE
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
.globl vdso32_start, vdso32_end
|
||||
.balign PAGE_SIZE
|
||||
vdso32_start:
|
||||
.incbin "arch/powerpc/kernel/vdso32/vdso32.so"
|
||||
.incbin "arch/powerpc/kernel/vdso32/vdso32.so.dbg"
|
||||
.balign PAGE_SIZE
|
||||
vdso32_end:
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
.globl vdso64_start, vdso64_end
|
||||
.balign PAGE_SIZE
|
||||
vdso64_start:
|
||||
.incbin "arch/powerpc/kernel/vdso64/vdso64.so"
|
||||
.incbin "arch/powerpc/kernel/vdso64/vdso64.so.dbg"
|
||||
.balign PAGE_SIZE
|
||||
vdso64_end:
|
||||
|
||||
|
|
|
|||
|
|
@ -207,6 +207,20 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
|
|||
if (overlaps_kernel_text(vaddr, vaddr + step))
|
||||
tprot &= ~HPTE_R_N;
|
||||
|
||||
/*
|
||||
* If relocatable, check if it overlaps interrupt vectors that
|
||||
* are copied down to real 0. For relocatable kernel
|
||||
* (e.g. kdump case) we copy interrupt vectors down to real
|
||||
* address 0. Mark that region as executable. This is
|
||||
* because on p8 system with relocation on exception feature
|
||||
* enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
|
||||
* in order to execute the interrupt handlers in virtual
|
||||
* mode the vector region need to be marked as executable.
|
||||
*/
|
||||
if ((PHYSICAL_START > MEMORY_START) &&
|
||||
overlaps_interrupt_vector_text(vaddr, vaddr + step))
|
||||
tprot &= ~HPTE_R_N;
|
||||
|
||||
hash = hpt_hash(vpn, shift, ssize);
|
||||
hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
|
||||
|
||||
|
|
|
|||
|
|
@ -510,7 +510,8 @@ int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address,
|
|||
}
|
||||
|
||||
unsigned long pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
|
||||
pmd_t *pmdp, unsigned long clr)
|
||||
pmd_t *pmdp, unsigned long clr,
|
||||
unsigned long set)
|
||||
{
|
||||
|
||||
unsigned long old, tmp;
|
||||
|
|
@ -526,14 +527,15 @@ unsigned long pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
|
|||
andi. %1,%0,%6\n\
|
||||
bne- 1b \n\
|
||||
andc %1,%0,%4 \n\
|
||||
or %1,%1,%7\n\
|
||||
stdcx. %1,0,%3 \n\
|
||||
bne- 1b"
|
||||
: "=&r" (old), "=&r" (tmp), "=m" (*pmdp)
|
||||
: "r" (pmdp), "r" (clr), "m" (*pmdp), "i" (_PAGE_BUSY)
|
||||
: "r" (pmdp), "r" (clr), "m" (*pmdp), "i" (_PAGE_BUSY), "r" (set)
|
||||
: "cc" );
|
||||
#else
|
||||
old = pmd_val(*pmdp);
|
||||
*pmdp = __pmd(old & ~clr);
|
||||
*pmdp = __pmd((old & ~clr) | set);
|
||||
#endif
|
||||
if (old & _PAGE_HASHPTE)
|
||||
hpte_do_hugepage_flush(mm, addr, pmdp);
|
||||
|
|
@ -708,7 +710,7 @@ void set_pmd_at(struct mm_struct *mm, unsigned long addr,
|
|||
void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
|
||||
pmd_t *pmdp)
|
||||
{
|
||||
pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT);
|
||||
pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -835,7 +837,7 @@ pmd_t pmdp_get_and_clear(struct mm_struct *mm,
|
|||
unsigned long old;
|
||||
pgtable_t *pgtable_slot;
|
||||
|
||||
old = pmd_hugepage_update(mm, addr, pmdp, ~0UL);
|
||||
old = pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
|
||||
old_pmd = __pmd(old);
|
||||
/*
|
||||
* We have pmd == none and we are holding page_table_lock.
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ static void hpte_flush_range(struct mm_struct *mm, unsigned long addr,
|
|||
pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
|
||||
arch_enter_lazy_mmu_mode();
|
||||
for (; npages > 0; --npages) {
|
||||
pte_update(mm, addr, pte, 0, 0);
|
||||
pte_update(mm, addr, pte, 0, 0, 0);
|
||||
addr += PAGE_SIZE;
|
||||
++pte;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1147,6 +1147,9 @@ static void power_pmu_enable(struct pmu *pmu)
|
|||
mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
|
||||
|
||||
mb();
|
||||
if (cpuhw->bhrb_users)
|
||||
ppmu->config_bhrb(cpuhw->bhrb_filter);
|
||||
|
||||
write_mmcr0(cpuhw, mmcr0);
|
||||
|
||||
/*
|
||||
|
|
@ -1158,8 +1161,6 @@ static void power_pmu_enable(struct pmu *pmu)
|
|||
}
|
||||
|
||||
out:
|
||||
if (cpuhw->bhrb_users)
|
||||
ppmu->config_bhrb(cpuhw->bhrb_filter);
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,6 +25,37 @@
|
|||
#define PM_BRU_FIN 0x10068
|
||||
#define PM_BR_MPRED_CMPL 0x400f6
|
||||
|
||||
/* All L1 D cache load references counted at finish, gated by reject */
|
||||
#define PM_LD_REF_L1 0x100ee
|
||||
/* Load Missed L1 */
|
||||
#define PM_LD_MISS_L1 0x3e054
|
||||
/* Store Missed L1 */
|
||||
#define PM_ST_MISS_L1 0x300f0
|
||||
/* L1 cache data prefetches */
|
||||
#define PM_L1_PREF 0x0d8b8
|
||||
/* Instruction fetches from L1 */
|
||||
#define PM_INST_FROM_L1 0x04080
|
||||
/* Demand iCache Miss */
|
||||
#define PM_L1_ICACHE_MISS 0x200fd
|
||||
/* Instruction Demand sectors wriittent into IL1 */
|
||||
#define PM_L1_DEMAND_WRITE 0x0408c
|
||||
/* Instruction prefetch written into IL1 */
|
||||
#define PM_IC_PREF_WRITE 0x0408e
|
||||
/* The data cache was reloaded from local core's L3 due to a demand load */
|
||||
#define PM_DATA_FROM_L3 0x4c042
|
||||
/* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
|
||||
#define PM_DATA_FROM_L3MISS 0x300fe
|
||||
/* All successful D-side store dispatches for this thread */
|
||||
#define PM_L2_ST 0x17080
|
||||
/* All successful D-side store dispatches for this thread that were L2 Miss */
|
||||
#define PM_L2_ST_MISS 0x17082
|
||||
/* Total HW L3 prefetches(Load+store) */
|
||||
#define PM_L3_PREF_ALL 0x4e052
|
||||
/* Data PTEG reload */
|
||||
#define PM_DTLB_MISS 0x300fc
|
||||
/* ITLB Reloaded */
|
||||
#define PM_ITLB_MISS 0x400fc
|
||||
|
||||
|
||||
/*
|
||||
* Raw event encoding for POWER8:
|
||||
|
|
@ -557,6 +588,8 @@ static int power8_generic_events[] = {
|
|||
[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
|
||||
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
|
||||
[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
|
||||
[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
|
||||
[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
|
||||
};
|
||||
|
||||
static u64 power8_bhrb_filter_map(u64 branch_sample_type)
|
||||
|
|
@ -596,6 +629,116 @@ static void power8_config_bhrb(u64 pmu_bhrb_filter)
|
|||
mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
|
||||
}
|
||||
|
||||
#define C(x) PERF_COUNT_HW_CACHE_##x
|
||||
|
||||
/*
|
||||
* Table of generalized cache-related events.
|
||||
* 0 means not supported, -1 means nonsensical, other values
|
||||
* are event codes.
|
||||
*/
|
||||
static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
||||
[ C(L1D) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
|
||||
[ C(RESULT_MISS) ] = PM_LD_MISS_L1,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_L1_PREF,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(L1I) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
|
||||
[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(LL) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
|
||||
[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_L2_ST,
|
||||
[ C(RESULT_MISS) ] = PM_L2_ST_MISS,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
|
||||
[ C(RESULT_MISS) ] = 0,
|
||||
},
|
||||
},
|
||||
[ C(DTLB) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = PM_DTLB_MISS,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(ITLB) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = 0,
|
||||
[ C(RESULT_MISS) ] = PM_ITLB_MISS,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(BPU) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = PM_BRU_FIN,
|
||||
[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
[ C(NODE) ] = {
|
||||
[ C(OP_READ) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_WRITE) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
[ C(OP_PREFETCH) ] = {
|
||||
[ C(RESULT_ACCESS) ] = -1,
|
||||
[ C(RESULT_MISS) ] = -1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
#undef C
|
||||
|
||||
static struct power_pmu power8_pmu = {
|
||||
.name = "POWER8",
|
||||
.n_counter = 6,
|
||||
|
|
@ -611,6 +754,7 @@ static struct power_pmu power8_pmu = {
|
|||
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
|
||||
.n_generic = ARRAY_SIZE(power8_generic_events),
|
||||
.generic_events = power8_generic_events,
|
||||
.cache_events = &power8_cache_events,
|
||||
.attr_groups = power8_pmu_attr_groups,
|
||||
.bhrb_nr = 32,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -44,7 +44,8 @@ static int ioda_eeh_event(struct notifier_block *nb,
|
|||
|
||||
/* We simply send special EEH event */
|
||||
if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
|
||||
(events & OPAL_EVENT_PCI_ERROR))
|
||||
(events & OPAL_EVENT_PCI_ERROR) &&
|
||||
eeh_enabled())
|
||||
eeh_send_failure_event(NULL);
|
||||
|
||||
return 0;
|
||||
|
|
@ -489,8 +490,7 @@ static int ioda_eeh_bridge_reset(struct pci_controller *hose,
|
|||
static int ioda_eeh_reset(struct eeh_pe *pe, int option)
|
||||
{
|
||||
struct pci_controller *hose = pe->phb;
|
||||
struct eeh_dev *edev;
|
||||
struct pci_dev *dev;
|
||||
struct pci_bus *bus;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
|
|
@ -519,31 +519,11 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
|
|||
if (pe->type & EEH_PE_PHB) {
|
||||
ret = ioda_eeh_phb_reset(hose, option);
|
||||
} else {
|
||||
if (pe->type & EEH_PE_DEVICE) {
|
||||
/*
|
||||
* If it's device PE, we didn't refer to the parent
|
||||
* PCI bus yet. So we have to figure it out indirectly.
|
||||
*/
|
||||
edev = list_first_entry(&pe->edevs,
|
||||
struct eeh_dev, list);
|
||||
dev = eeh_dev_to_pci_dev(edev);
|
||||
dev = dev->bus->self;
|
||||
} else {
|
||||
/*
|
||||
* If it's bus PE, the parent PCI bus is already there
|
||||
* and just pick it up.
|
||||
*/
|
||||
dev = pe->bus->self;
|
||||
}
|
||||
|
||||
/*
|
||||
* Do reset based on the fact that the direct upstream bridge
|
||||
* is root bridge (port) or not.
|
||||
*/
|
||||
if (dev->bus->number == 0)
|
||||
bus = eeh_pe_bus_get(pe);
|
||||
if (pci_is_root_bus(bus))
|
||||
ret = ioda_eeh_root_reset(hose, option);
|
||||
else
|
||||
ret = ioda_eeh_bridge_reset(hose, dev, option);
|
||||
ret = ioda_eeh_bridge_reset(hose, bus->self, option);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
|
|||
* Enable EEH explicitly so that we will do EEH check
|
||||
* while accessing I/O stuff
|
||||
*/
|
||||
eeh_subsystem_enabled = 1;
|
||||
eeh_set_enable(true);
|
||||
|
||||
/* Save memory bars */
|
||||
eeh_save_bars(edev);
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/msi.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
#include <asm/sections.h>
|
||||
#include <asm/io.h>
|
||||
|
|
@ -460,9 +461,39 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
|
|||
return;
|
||||
|
||||
pe = &phb->ioda.pe_array[pdn->pe_number];
|
||||
WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
|
||||
set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
|
||||
}
|
||||
|
||||
static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
|
||||
struct pci_dev *pdev, u64 dma_mask)
|
||||
{
|
||||
struct pci_dn *pdn = pci_get_pdn(pdev);
|
||||
struct pnv_ioda_pe *pe;
|
||||
uint64_t top;
|
||||
bool bypass = false;
|
||||
|
||||
if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
|
||||
return -ENODEV;;
|
||||
|
||||
pe = &phb->ioda.pe_array[pdn->pe_number];
|
||||
if (pe->tce_bypass_enabled) {
|
||||
top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
|
||||
bypass = (dma_mask >= top);
|
||||
}
|
||||
|
||||
if (bypass) {
|
||||
dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
|
||||
set_dma_ops(&pdev->dev, &dma_direct_ops);
|
||||
set_dma_offset(&pdev->dev, pe->tce_bypass_base);
|
||||
} else {
|
||||
dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
|
||||
set_dma_ops(&pdev->dev, &dma_iommu_ops);
|
||||
set_iommu_table_base(&pdev->dev, &pe->tce32_table);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
|
|
@ -657,6 +688,56 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
|
|||
__free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
|
||||
}
|
||||
|
||||
static void pnv_pci_ioda2_set_bypass(struct iommu_table *tbl, bool enable)
|
||||
{
|
||||
struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
|
||||
tce32_table);
|
||||
uint16_t window_id = (pe->pe_number << 1 ) + 1;
|
||||
int64_t rc;
|
||||
|
||||
pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
|
||||
if (enable) {
|
||||
phys_addr_t top = memblock_end_of_DRAM();
|
||||
|
||||
top = roundup_pow_of_two(top);
|
||||
rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
|
||||
pe->pe_number,
|
||||
window_id,
|
||||
pe->tce_bypass_base,
|
||||
top);
|
||||
} else {
|
||||
rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
|
||||
pe->pe_number,
|
||||
window_id,
|
||||
pe->tce_bypass_base,
|
||||
0);
|
||||
|
||||
/*
|
||||
* We might want to reset the DMA ops of all devices on
|
||||
* this PE. However in theory, that shouldn't be necessary
|
||||
* as this is used for VFIO/KVM pass-through and the device
|
||||
* hasn't yet been returned to its kernel driver
|
||||
*/
|
||||
}
|
||||
if (rc)
|
||||
pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
|
||||
else
|
||||
pe->tce_bypass_enabled = enable;
|
||||
}
|
||||
|
||||
static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
|
||||
struct pnv_ioda_pe *pe)
|
||||
{
|
||||
/* TVE #1 is selected by PCI address bit 59 */
|
||||
pe->tce_bypass_base = 1ull << 59;
|
||||
|
||||
/* Install set_bypass callback for VFIO */
|
||||
pe->tce32_table.set_bypass = pnv_pci_ioda2_set_bypass;
|
||||
|
||||
/* Enable bypass by default */
|
||||
pnv_pci_ioda2_set_bypass(&pe->tce32_table, true);
|
||||
}
|
||||
|
||||
static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
|
||||
struct pnv_ioda_pe *pe)
|
||||
{
|
||||
|
|
@ -727,6 +808,8 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
|
|||
else
|
||||
pnv_ioda_setup_bus_dma(pe, pe->pbus);
|
||||
|
||||
/* Also create a bypass window */
|
||||
pnv_pci_ioda2_setup_bypass_pe(phb, pe);
|
||||
return;
|
||||
fail:
|
||||
if (pe->tce32_seg >= 0)
|
||||
|
|
@ -1286,6 +1369,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np,
|
|||
|
||||
/* Setup TCEs */
|
||||
phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
|
||||
phb->dma_set_mask = pnv_pci_ioda_dma_set_mask;
|
||||
|
||||
/* Setup shutdown function for kexec */
|
||||
phb->shutdown = pnv_pci_ioda_shutdown;
|
||||
|
|
|
|||
|
|
@ -634,6 +634,16 @@ static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
|
|||
pnv_pci_dma_fallback_setup(hose, pdev);
|
||||
}
|
||||
|
||||
int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(pdev->bus);
|
||||
struct pnv_phb *phb = hose->private_data;
|
||||
|
||||
if (phb && phb->dma_set_mask)
|
||||
return phb->dma_set_mask(phb, pdev, dma_mask);
|
||||
return __dma_set_mask(&pdev->dev, dma_mask);
|
||||
}
|
||||
|
||||
void pnv_pci_shutdown(void)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
|
|
|
|||
|
|
@ -54,7 +54,9 @@ struct pnv_ioda_pe {
|
|||
struct iommu_table tce32_table;
|
||||
phys_addr_t tce_inval_reg_phys;
|
||||
|
||||
/* XXX TODO: Add support for additional 64-bit iommus */
|
||||
/* 64-bit TCE bypass region */
|
||||
bool tce_bypass_enabled;
|
||||
uint64_t tce_bypass_base;
|
||||
|
||||
/* MSIs. MVE index is identical for for 32 and 64 bit MSI
|
||||
* and -1 if not supported. (It's actually identical to the
|
||||
|
|
@ -113,6 +115,8 @@ struct pnv_phb {
|
|||
unsigned int hwirq, unsigned int virq,
|
||||
unsigned int is_64, struct msi_msg *msg);
|
||||
void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
|
||||
int (*dma_set_mask)(struct pnv_phb *phb, struct pci_dev *pdev,
|
||||
u64 dma_mask);
|
||||
void (*fixup_phb)(struct pci_controller *hose);
|
||||
u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
|
||||
void (*shutdown)(struct pnv_phb *phb);
|
||||
|
|
|
|||
|
|
@ -7,12 +7,20 @@ extern void pnv_smp_init(void);
|
|||
static inline void pnv_smp_init(void) { }
|
||||
#endif
|
||||
|
||||
struct pci_dev;
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern void pnv_pci_init(void);
|
||||
extern void pnv_pci_shutdown(void);
|
||||
extern int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask);
|
||||
#else
|
||||
static inline void pnv_pci_init(void) { }
|
||||
static inline void pnv_pci_shutdown(void) { }
|
||||
|
||||
static inline int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
extern void pnv_lpc_init(void);
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/cpuidle.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/firmware.h>
|
||||
|
|
@ -141,6 +142,13 @@ static void pnv_progress(char *s, unsigned short hex)
|
|||
{
|
||||
}
|
||||
|
||||
static int pnv_dma_set_mask(struct device *dev, u64 dma_mask)
|
||||
{
|
||||
if (dev_is_pci(dev))
|
||||
return pnv_pci_dma_set_mask(to_pci_dev(dev), dma_mask);
|
||||
return __dma_set_mask(dev, dma_mask);
|
||||
}
|
||||
|
||||
static void pnv_shutdown(void)
|
||||
{
|
||||
/* Let the PCI code clear up IODA tables */
|
||||
|
|
@ -238,6 +246,7 @@ define_machine(powernv) {
|
|||
.machine_shutdown = pnv_shutdown,
|
||||
.power_save = powernv_idle,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.dma_set_mask = pnv_dma_set_mask,
|
||||
#ifdef CONFIG_KEXEC
|
||||
.kexec_cpu_down = pnv_kexec_cpu_down,
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ config PPC_PSERIES
|
|||
select PPC_DOORBELL
|
||||
select HAVE_CONTEXT_TRACKING
|
||||
select HOTPLUG_CPU if SMP
|
||||
select ARCH_RANDOM
|
||||
default y
|
||||
|
||||
config PPC_SPLPAR
|
||||
|
|
|
|||
|
|
@ -265,7 +265,7 @@ static void *pseries_eeh_of_probe(struct device_node *dn, void *flag)
|
|||
enable = 1;
|
||||
|
||||
if (enable) {
|
||||
eeh_subsystem_enabled = 1;
|
||||
eeh_set_enable(true);
|
||||
eeh_add_to_parent_pe(edev);
|
||||
|
||||
pr_debug("%s: EEH enabled on %s PHB#%d-PE#%x, config addr#%x\n",
|
||||
|
|
|
|||
|
|
@ -113,7 +113,8 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
|
|||
{
|
||||
struct device_node *dn, *pdn;
|
||||
struct pci_bus *bus;
|
||||
const __be32 *pcie_link_speed_stats;
|
||||
u32 pcie_link_speed_stats[2];
|
||||
int rc;
|
||||
|
||||
bus = bridge->bus;
|
||||
|
||||
|
|
@ -122,38 +123,45 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
|
|||
return 0;
|
||||
|
||||
for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
|
||||
pcie_link_speed_stats = of_get_property(pdn,
|
||||
"ibm,pcie-link-speed-stats", NULL);
|
||||
if (pcie_link_speed_stats)
|
||||
rc = of_property_read_u32_array(pdn,
|
||||
"ibm,pcie-link-speed-stats",
|
||||
&pcie_link_speed_stats[0], 2);
|
||||
if (!rc)
|
||||
break;
|
||||
}
|
||||
|
||||
of_node_put(pdn);
|
||||
|
||||
if (!pcie_link_speed_stats) {
|
||||
if (rc) {
|
||||
pr_err("no ibm,pcie-link-speed-stats property\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (be32_to_cpup(pcie_link_speed_stats)) {
|
||||
switch (pcie_link_speed_stats[0]) {
|
||||
case 0x01:
|
||||
bus->max_bus_speed = PCIE_SPEED_2_5GT;
|
||||
break;
|
||||
case 0x02:
|
||||
bus->max_bus_speed = PCIE_SPEED_5_0GT;
|
||||
break;
|
||||
case 0x04:
|
||||
bus->max_bus_speed = PCIE_SPEED_8_0GT;
|
||||
break;
|
||||
default:
|
||||
bus->max_bus_speed = PCI_SPEED_UNKNOWN;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (be32_to_cpup(pcie_link_speed_stats)) {
|
||||
switch (pcie_link_speed_stats[1]) {
|
||||
case 0x01:
|
||||
bus->cur_bus_speed = PCIE_SPEED_2_5GT;
|
||||
break;
|
||||
case 0x02:
|
||||
bus->cur_bus_speed = PCIE_SPEED_5_0GT;
|
||||
break;
|
||||
case 0x04:
|
||||
bus->cur_bus_speed = PCIE_SPEED_8_0GT;
|
||||
break;
|
||||
default:
|
||||
bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -430,8 +430,7 @@ static void pSeries_machine_kexec(struct kimage *image)
|
|||
{
|
||||
long rc;
|
||||
|
||||
if (firmware_has_feature(FW_FEATURE_SET_MODE) &&
|
||||
(image->type != KEXEC_TYPE_CRASH)) {
|
||||
if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
|
||||
rc = pSeries_disable_reloc_on_exc();
|
||||
if (rc != H_SUCCESS)
|
||||
pr_warning("Warning: Failed to disable relocation on "
|
||||
|
|
|
|||
|
|
@ -886,25 +886,25 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
|
|||
|
||||
/* Default: read HW settings */
|
||||
if (flow_type == IRQ_TYPE_DEFAULT) {
|
||||
switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
|
||||
MPIC_INFO(VECPRI_SENSE_MASK))) {
|
||||
case MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
|
||||
flow_type = IRQ_TYPE_EDGE_RISING;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
|
||||
flow_type = IRQ_TYPE_EDGE_FALLING;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
|
||||
flow_type = IRQ_TYPE_LEVEL_HIGH;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
break;
|
||||
}
|
||||
int vold_ps;
|
||||
|
||||
vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
|
||||
MPIC_INFO(VECPRI_SENSE_MASK));
|
||||
|
||||
if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
|
||||
flow_type = IRQ_TYPE_EDGE_RISING;
|
||||
else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
|
||||
flow_type = IRQ_TYPE_EDGE_FALLING;
|
||||
else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
|
||||
flow_type = IRQ_TYPE_LEVEL_HIGH;
|
||||
else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
else
|
||||
WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
|
||||
}
|
||||
|
||||
/* Apply to irq desc */
|
||||
|
|
|
|||
|
|
@ -309,16 +309,23 @@ static void get_output_lock(void)
|
|||
|
||||
if (xmon_speaker == me)
|
||||
return;
|
||||
|
||||
for (;;) {
|
||||
if (xmon_speaker == 0) {
|
||||
last_speaker = cmpxchg(&xmon_speaker, 0, me);
|
||||
if (last_speaker == 0)
|
||||
return;
|
||||
}
|
||||
timeout = 10000000;
|
||||
last_speaker = cmpxchg(&xmon_speaker, 0, me);
|
||||
if (last_speaker == 0)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Wait a full second for the lock, we might be on a slow
|
||||
* console, but check every 100us.
|
||||
*/
|
||||
timeout = 10000;
|
||||
while (xmon_speaker == last_speaker) {
|
||||
if (--timeout > 0)
|
||||
if (--timeout > 0) {
|
||||
udelay(100);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* hostile takeover */
|
||||
prev = cmpxchg(&xmon_speaker, last_speaker, me);
|
||||
if (prev == last_speaker)
|
||||
|
|
@ -397,7 +404,6 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
|
|||
}
|
||||
|
||||
xmon_fault_jmp[cpu] = recurse_jmp;
|
||||
cpumask_set_cpu(cpu, &cpus_in_xmon);
|
||||
|
||||
bp = NULL;
|
||||
if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT))
|
||||
|
|
@ -419,6 +425,8 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
|
|||
release_output_lock();
|
||||
}
|
||||
|
||||
cpumask_set_cpu(cpu, &cpus_in_xmon);
|
||||
|
||||
waiting:
|
||||
secondary = 1;
|
||||
while (secondary && !xmon_gate) {
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@ extern void __init efi_map_region_fixed(efi_memory_desc_t *md);
|
|||
extern void efi_sync_low_kernel_mappings(void);
|
||||
extern void efi_setup_page_tables(void);
|
||||
extern void __init old_map_region(efi_memory_desc_t *md);
|
||||
extern void __init runtime_code_page_mkexec(void);
|
||||
extern void __init efi_runtime_mkexec(void);
|
||||
|
||||
struct efi_setup_data {
|
||||
u64 fw_vendor;
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue