ARM: 5778/1: AT91: Add cpuidle support
This patch adds the support for cpuidle on AT91 SoCs, taken from the cpuidle support in mach-kirkwood. cpuidle needs sdram_selfrefresh_enable and _disable, so move their definition to a separate header file instead of duplicating the code already used in pm.c. Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -77,6 +77,7 @@ obj-y += leds.o
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# Power Management
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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ifeq ($(CONFIG_PM_DEBUG),y)
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CFLAGS_pm.o += -DDEBUG
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94
arch/arm/mach-at91/cpuidle.c
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94
arch/arm/mach-at91/cpuidle.c
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@ -0,0 +1,94 @@
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/*
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* based on arch/arm/mach-kirkwood/cpuidle.c
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*
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* CPU idle support for AT91 SoC
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The cpu idle uses wait-for-interrupt and RAM self refresh in order
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* to implement two idle states -
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* #1 wait-for-interrupt
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* #2 wait-for-interrupt and RAM self refresh
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/cpuidle.h>
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#include <asm/proc-fns.h>
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#include <linux/io.h>
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#include "pm.h"
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#define AT91_MAX_STATES 2
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static DEFINE_PER_CPU(struct cpuidle_device, at91_cpuidle_device);
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static struct cpuidle_driver at91_idle_driver = {
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.name = "at91_idle",
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.owner = THIS_MODULE,
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};
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/* Actual code that puts the SoC in different idle states */
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static int at91_enter_idle(struct cpuidle_device *dev,
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struct cpuidle_state *state)
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{
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struct timeval before, after;
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int idle_time;
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u32 saved_lpr;
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local_irq_disable();
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do_gettimeofday(&before);
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if (state == &dev->states[0])
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/* Wait for interrupt state */
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cpu_do_idle();
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else if (state == &dev->states[1]) {
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asm("b 1f; .align 5; 1:");
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asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
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saved_lpr = sdram_selfrefresh_enable();
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cpu_do_idle();
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sdram_selfrefresh_disable(saved_lpr);
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}
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do_gettimeofday(&after);
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local_irq_enable();
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idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
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(after.tv_usec - before.tv_usec);
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return idle_time;
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}
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/* Initialize CPU idle by registering the idle states */
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static int at91_init_cpuidle(void)
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{
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struct cpuidle_device *device;
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cpuidle_register_driver(&at91_idle_driver);
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device = &per_cpu(at91_cpuidle_device, smp_processor_id());
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device->state_count = AT91_MAX_STATES;
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/* Wait for interrupt state */
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device->states[0].enter = at91_enter_idle;
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device->states[0].exit_latency = 1;
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device->states[0].target_residency = 10000;
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device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
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strcpy(device->states[0].name, "WFI");
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strcpy(device->states[0].desc, "Wait for interrupt");
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/* Wait for interrupt and RAM self refresh state */
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device->states[1].enter = at91_enter_idle;
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device->states[1].exit_latency = 10;
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device->states[1].target_residency = 10000;
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device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
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strcpy(device->states[1].name, "RAM_SR");
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strcpy(device->states[1].desc, "WFI and RAM Self Refresh");
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if (cpuidle_register_device(device)) {
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printk(KERN_ERR "at91_init_cpuidle: Failed registering\n");
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return -EIO;
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}
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return 0;
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}
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device_initcall(at91_init_cpuidle);
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@ -29,62 +29,7 @@
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#include <mach/cpu.h>
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#include "generic.h"
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#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*/
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#define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1)
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#define sdram_selfrefresh_disable() do {} while (0)
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#elif defined(CONFIG_ARCH_AT91CAP9)
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#include <mach/at91cap9_ddrsdr.h>
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static u32 saved_lpr;
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static inline void sdram_selfrefresh_enable(void)
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{
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u32 lpr;
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saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
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lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
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at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
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}
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#define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
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#else
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#include <mach/at91sam9_sdramc.h>
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#ifdef CONFIG_ARCH_AT91SAM9263
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/*
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* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
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* handle those cases both here and in the Suspend-To-RAM support.
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*/
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#define AT91_SDRAMC AT91_SDRAMC0
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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static u32 saved_lpr;
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static inline void sdram_selfrefresh_enable(void)
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{
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u32 lpr;
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saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
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}
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#define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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#endif
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#include "pm.h"
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/*
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* Show the reason for the previous system reset.
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@ -260,6 +205,7 @@ extern u32 at91_slow_clock_sz;
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static int at91_pm_enter(suspend_state_t state)
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{
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u32 saved_lpr;
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at91_gpio_suspend();
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at91_irq_suspend();
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@ -315,9 +261,9 @@ static int at91_pm_enter(suspend_state_t state)
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*/
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asm("b 1f; .align 5; 1:");
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asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
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sdram_selfrefresh_enable();
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saved_lpr = sdram_selfrefresh_enable();
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asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
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sdram_selfrefresh_disable();
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sdram_selfrefresh_disable(saved_lpr);
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break;
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case PM_SUSPEND_ON:
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67
arch/arm/mach-at91/pm.h
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67
arch/arm/mach-at91/pm.h
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#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
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at91_sys_write(AT91_SDRAMC_LPR, 0);
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at91_sys_write(AT91_SDRAMC_SRR, 1);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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#elif defined(CONFIG_ARCH_AT91CAP9)
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#include <mach/at91cap9_ddrsdr.h>
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
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lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
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at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
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#else
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#include <mach/at91sam9_sdramc.h>
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#ifdef CONFIG_ARCH_AT91SAM9263
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/*
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* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
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* handle those cases both here and in the Suspend-To-RAM support.
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*/
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#define AT91_SDRAMC AT91_SDRAMC0
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#warning Assuming EB1 SDRAM controller is *NOT* used
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#endif
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static inline u32 sdram_selfrefresh_enable(void)
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{
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u32 saved_lpr, lpr;
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saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
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return saved_lpr;
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}
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#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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#endif
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