drm/i915: Use more atomic state in intel_color.c
crtc_state is already passed around, use it instead of crtc->config. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1470755054-32699-16-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -100,13 +100,14 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int i, pipe = intel_crtc->pipe;
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uint16_t coeffs[9] = { 0, };
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struct intel_crtc_state *intel_crtc_state = to_intel_crtc_state(crtc_state);
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if (crtc_state->ctm) {
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struct drm_color_ctm *ctm =
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(struct drm_color_ctm *)crtc_state->ctm->data;
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uint64_t input[9] = { 0, };
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if (intel_crtc->config->limited_color_range) {
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if (intel_crtc_state->limited_color_range) {
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ctm_mult_by_limited(input, ctm->matrix);
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} else {
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for (i = 0; i < ARRAY_SIZE(input); i++)
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@ -158,7 +159,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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* into consideration.
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*/
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for (i = 0; i < 3; i++) {
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if (intel_crtc->config->limited_color_range)
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if (intel_crtc_state->limited_color_range)
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coeffs[i * 3 + i] =
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I9XX_CSC_COEFF_LIMITED_RANGE;
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else
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@ -182,7 +183,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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if (INTEL_INFO(dev)->gen > 6) {
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uint16_t postoff = 0;
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if (intel_crtc->config->limited_color_range)
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if (intel_crtc_state->limited_color_range)
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postoff = (16 * (1 << 12) / 255) & 0x1fff;
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I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
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@ -193,7 +194,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state)
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} else {
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uint32_t mode = CSC_MODE_YUV_TO_RGB;
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if (intel_crtc->config->limited_color_range)
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if (intel_crtc_state->limited_color_range)
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mode |= CSC_BLACK_SCREEN_OFFSET;
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I915_WRITE(PIPE_CSC_MODE(pipe), mode);
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@ -263,7 +264,8 @@ void intel_color_set_csc(struct drm_crtc_state *crtc_state)
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/* Loads the legacy palette/gamma unit for the CRTC. */
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static void i9xx_load_luts_internal(struct drm_crtc *crtc,
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struct drm_property_blob *blob)
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struct drm_property_blob *blob,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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@ -272,7 +274,7 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
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int i;
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if (HAS_GMCH_DISPLAY(dev)) {
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if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI))
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
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assert_dsi_pll_enabled(dev_priv);
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else
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assert_pll_enabled(dev_priv, pipe);
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@ -305,7 +307,8 @@ static void i9xx_load_luts_internal(struct drm_crtc *crtc,
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static void i9xx_load_luts(struct drm_crtc_state *crtc_state)
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{
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i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut);
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i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut,
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to_intel_crtc_state(crtc_state));
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}
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/* Loads the legacy palette/gamma unit for the CRTC on Haswell. */
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@ -323,7 +326,7 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
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* Workaround : Do not read or write the pipe palette/gamma data while
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* GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
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*/
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if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
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if (IS_HASWELL(dev) && intel_crtc_state->ips_enabled &&
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(intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
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hsw_disable_ips(intel_crtc);
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reenable_ips = true;
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@ -436,7 +439,8 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
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/* Turn off degamma/gamma on CGM block. */
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I915_WRITE(CGM_PIPE_MODE(pipe),
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(state->ctm ? CGM_PIPE_MODE_CSC : 0));
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i9xx_load_luts_internal(crtc, state->gamma_lut);
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i9xx_load_luts_internal(crtc, state->gamma_lut,
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to_intel_crtc_state(state));
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return;
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}
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@ -479,7 +483,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
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* Also program a linear LUT in the legacy block (behind the
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* CGM block).
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*/
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i9xx_load_luts_internal(crtc, NULL);
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i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
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}
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void intel_color_load_luts(struct drm_crtc_state *crtc_state)
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