powerpc: Emulate load/store floating double pair instructions
This adds lfdp[x] and stfdp[x] to the set of instructions that analyse_instr() and emulate_step() understand. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>zero-colors
parent
e61ccc7b0c
commit
1f41fb7904
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@ -415,9 +415,9 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)
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int err;
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union {
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float f;
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double d;
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unsigned long l;
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u8 b[sizeof(double)];
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double d[2];
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unsigned long l[2];
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u8 b[2 * sizeof(double)];
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} u;
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if (!address_ok(regs, ea, nb))
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@ -427,11 +427,19 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)
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return err;
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preempt_disable();
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if (nb == 4)
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conv_sp_to_dp(&u.f, &u.d);
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conv_sp_to_dp(&u.f, &u.d[0]);
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if (regs->msr & MSR_FP)
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put_fpr(rn, &u.d);
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put_fpr(rn, &u.d[0]);
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else
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current->thread.TS_FPR(rn) = u.l;
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current->thread.TS_FPR(rn) = u.l[0];
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if (nb == 16) {
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/* lfdp */
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rn |= 1;
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if (regs->msr & MSR_FP)
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put_fpr(rn, &u.d[1]);
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else
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current->thread.TS_FPR(rn) = u.l[1];
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}
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preempt_enable();
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return 0;
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}
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@ -441,20 +449,27 @@ static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs)
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{
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union {
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float f;
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double d;
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unsigned long l;
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u8 b[sizeof(double)];
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double d[2];
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unsigned long l[2];
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u8 b[2 * sizeof(double)];
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} u;
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if (!address_ok(regs, ea, nb))
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return -EFAULT;
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preempt_disable();
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if (regs->msr & MSR_FP)
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get_fpr(rn, &u.d);
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get_fpr(rn, &u.d[0]);
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else
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u.l = current->thread.TS_FPR(rn);
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u.l[0] = current->thread.TS_FPR(rn);
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if (nb == 4)
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conv_dp_to_sp(&u.d, &u.f);
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conv_dp_to_sp(&u.d[0], &u.f);
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if (nb == 16) {
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rn |= 1;
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if (regs->msr & MSR_FP)
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get_fpr(rn, &u.d[1]);
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else
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u.l[1] = current->thread.TS_FPR(rn);
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}
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preempt_enable();
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return copy_mem_out(u.b, ea, nb);
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}
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@ -1938,7 +1953,17 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 759: /* stfdux */
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op->type = MKOP(STORE_FP, u, 8);
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break;
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#endif
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#ifdef __powerpc64__
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case 791: /* lfdpx */
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op->type = MKOP(LOAD_FP, 0, 16);
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break;
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case 919: /* stfdpx */
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op->type = MKOP(STORE_FP, 0, 16);
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break;
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#endif /* __powerpc64 */
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#endif /* CONFIG_PPC_FPU */
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#ifdef __powerpc64__
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case 660: /* stdbrx */
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@ -1956,7 +1981,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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op->val = byterev_4(regs->gpr[rd]);
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break;
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case 725:
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case 725: /* stswi */
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if (rb == 0)
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rb = 32; /* # bytes to store */
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op->type = MKOP(STORE_MULTI, 0, rb);
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@ -2246,9 +2271,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#endif
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#ifdef CONFIG_VSX
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case 57: /* lxsd, lxssp */
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case 57: /* lfdp, lxsd, lxssp */
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op->ea = dsform_ea(instr, regs);
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switch (instr & 3) {
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case 0: /* lfdp */
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if (rd & 1)
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break; /* reg must be even */
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op->type = MKOP(LOAD_FP, 0, 16);
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break;
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case 2: /* lxsd */
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op->reg = rd + 32;
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op->type = MKOP(LOAD_VSX, 0, 8);
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@ -2283,8 +2313,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#endif
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#ifdef CONFIG_VSX
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case 61: /* lxv, stxsd, stxssp, stxv */
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case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
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switch (instr & 7) {
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case 0: /* stfdp with LSB of DS field = 0 */
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case 4: /* stfdp with LSB of DS field = 1 */
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op->ea = dsform_ea(instr, regs);
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op->type = MKOP(STORE_FP, 0, 16);
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break;
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case 1: /* lxv */
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op->ea = dqform_ea(instr, regs);
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if (instr & 8)
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