ARM: imx6q: add spdif gate clock
It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -209,6 +209,7 @@ clocks and IDs.
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pll5_post_div 194
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pll5_video_div 195
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eim_slow 196
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spdif 197
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Examples:
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@ -239,7 +239,8 @@ enum mx6q_clks {
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pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
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ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
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sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
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usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
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usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
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spdif, clk_max
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};
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static struct clk *clk[clk_max];
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@ -521,6 +522,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
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clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
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clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
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clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
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clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
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clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
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clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
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