Merge branch 'samsung/devel' of git+ssh://git.linaro.org/home/arndbergmann/public_git/arm-soc into next/devel2
This commit is contained in:
commit
1faca4ced8
13
Documentation/ABI/testing/sysfs-class-scsi_host
Normal file
13
Documentation/ABI/testing/sysfs-class-scsi_host
Normal file
|
@ -0,0 +1,13 @@
|
|||
What: /sys/class/scsi_host/hostX/isci_id
|
||||
Date: June 2011
|
||||
Contact: Dave Jiang <dave.jiang@intel.com>
|
||||
Description:
|
||||
This file contains the enumerated host ID for the Intel
|
||||
SCU controller. The Intel(R) C600 Series Chipset SATA/SAS
|
||||
Storage Control Unit embeds up to two 4-port controllers in
|
||||
a single PCI device. The controllers are enumerated in order
|
||||
which usually means the lowest number scsi_host corresponds
|
||||
with the first controller, but this association is not
|
||||
guaranteed. The 'isci_id' attribute unambiguously identifies
|
||||
the controller index: '0' for the first controller,
|
||||
'1' for the second.
|
|
@ -380,7 +380,7 @@ will be charged as a new owner of it.
|
|||
|
||||
5.2 stat file
|
||||
|
||||
5.2.1 memory.stat file includes following statistics
|
||||
memory.stat file includes following statistics
|
||||
|
||||
# per-memory cgroup local status
|
||||
cache - # of bytes of page cache memory.
|
||||
|
@ -438,89 +438,6 @@ Note:
|
|||
file_mapped is accounted only when the memory cgroup is owner of page
|
||||
cache.)
|
||||
|
||||
5.2.2 memory.vmscan_stat
|
||||
|
||||
memory.vmscan_stat includes statistics information for memory scanning and
|
||||
freeing, reclaiming. The statistics shows memory scanning information since
|
||||
memory cgroup creation and can be reset to 0 by writing 0 as
|
||||
|
||||
#echo 0 > ../memory.vmscan_stat
|
||||
|
||||
This file contains following statistics.
|
||||
|
||||
[param]_[file_or_anon]_pages_by_[reason]_[under_heararchy]
|
||||
[param]_elapsed_ns_by_[reason]_[under_hierarchy]
|
||||
|
||||
For example,
|
||||
|
||||
scanned_file_pages_by_limit indicates the number of scanned
|
||||
file pages at vmscan.
|
||||
|
||||
Now, 3 parameters are supported
|
||||
|
||||
scanned - the number of pages scanned by vmscan
|
||||
rotated - the number of pages activated at vmscan
|
||||
freed - the number of pages freed by vmscan
|
||||
|
||||
If "rotated" is high against scanned/freed, the memcg seems busy.
|
||||
|
||||
Now, 2 reason are supported
|
||||
|
||||
limit - the memory cgroup's limit
|
||||
system - global memory pressure + softlimit
|
||||
(global memory pressure not under softlimit is not handled now)
|
||||
|
||||
When under_hierarchy is added in the tail, the number indicates the
|
||||
total memcg scan of its children and itself.
|
||||
|
||||
elapsed_ns is a elapsed time in nanosecond. This may include sleep time
|
||||
and not indicates CPU usage. So, please take this as just showing
|
||||
latency.
|
||||
|
||||
Here is an example.
|
||||
|
||||
# cat /cgroup/memory/A/memory.vmscan_stat
|
||||
scanned_pages_by_limit 9471864
|
||||
scanned_anon_pages_by_limit 6640629
|
||||
scanned_file_pages_by_limit 2831235
|
||||
rotated_pages_by_limit 4243974
|
||||
rotated_anon_pages_by_limit 3971968
|
||||
rotated_file_pages_by_limit 272006
|
||||
freed_pages_by_limit 2318492
|
||||
freed_anon_pages_by_limit 962052
|
||||
freed_file_pages_by_limit 1356440
|
||||
elapsed_ns_by_limit 351386416101
|
||||
scanned_pages_by_system 0
|
||||
scanned_anon_pages_by_system 0
|
||||
scanned_file_pages_by_system 0
|
||||
rotated_pages_by_system 0
|
||||
rotated_anon_pages_by_system 0
|
||||
rotated_file_pages_by_system 0
|
||||
freed_pages_by_system 0
|
||||
freed_anon_pages_by_system 0
|
||||
freed_file_pages_by_system 0
|
||||
elapsed_ns_by_system 0
|
||||
scanned_pages_by_limit_under_hierarchy 9471864
|
||||
scanned_anon_pages_by_limit_under_hierarchy 6640629
|
||||
scanned_file_pages_by_limit_under_hierarchy 2831235
|
||||
rotated_pages_by_limit_under_hierarchy 4243974
|
||||
rotated_anon_pages_by_limit_under_hierarchy 3971968
|
||||
rotated_file_pages_by_limit_under_hierarchy 272006
|
||||
freed_pages_by_limit_under_hierarchy 2318492
|
||||
freed_anon_pages_by_limit_under_hierarchy 962052
|
||||
freed_file_pages_by_limit_under_hierarchy 1356440
|
||||
elapsed_ns_by_limit_under_hierarchy 351386416101
|
||||
scanned_pages_by_system_under_hierarchy 0
|
||||
scanned_anon_pages_by_system_under_hierarchy 0
|
||||
scanned_file_pages_by_system_under_hierarchy 0
|
||||
rotated_pages_by_system_under_hierarchy 0
|
||||
rotated_anon_pages_by_system_under_hierarchy 0
|
||||
rotated_file_pages_by_system_under_hierarchy 0
|
||||
freed_pages_by_system_under_hierarchy 0
|
||||
freed_anon_pages_by_system_under_hierarchy 0
|
||||
freed_file_pages_by_system_under_hierarchy 0
|
||||
elapsed_ns_by_system_under_hierarchy 0
|
||||
|
||||
5.3 swappiness
|
||||
|
||||
Similar to /proc/sys/vm/swappiness, but affecting a hierarchy of groups only.
|
||||
|
|
|
@ -35,13 +35,6 @@ the Out-Of-Spec bit. Following table summarizes the exported sysfs files:
|
|||
All Sysfs entries are named with their core_id (represented here by 'X').
|
||||
tempX_input - Core temperature (in millidegrees Celsius).
|
||||
tempX_max - All cooling devices should be turned on (on Core2).
|
||||
Initialized with IA32_THERM_INTERRUPT. When the CPU
|
||||
temperature reaches this temperature, an interrupt is
|
||||
generated and tempX_max_alarm is set.
|
||||
tempX_max_hyst - If the CPU temperature falls below than temperature,
|
||||
an interrupt is generated and tempX_max_alarm is reset.
|
||||
tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max.
|
||||
Reset if the temperature drops to or below tempX_max_hyst.
|
||||
tempX_crit - Maximum junction temperature (in millidegrees Celsius).
|
||||
tempX_crit_alarm - Set when Out-of-spec bit is set, never clears.
|
||||
Correct CPU operation is no longer guaranteed.
|
||||
|
@ -49,9 +42,10 @@ tempX_label - Contains string "Core X", where X is processor
|
|||
number. For Package temp, this will be "Physical id Y",
|
||||
where Y is the package number.
|
||||
|
||||
The TjMax temperature is set to 85 degrees C if undocumented model specific
|
||||
register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as
|
||||
(sometimes) documented in processor datasheet.
|
||||
On CPU models which support it, TjMax is read from a model-specific register.
|
||||
On other models, it is set to an arbitrary value based on weak heuristics.
|
||||
If these heuristics don't work for you, you can pass the correct TjMax value
|
||||
as a module parameter (tjmax).
|
||||
|
||||
Appendix A. Known TjMax lists (TBD):
|
||||
Some information comes from ark.intel.com
|
||||
|
|
|
@ -2086,9 +2086,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
Override pmtimer IOPort with a hex value.
|
||||
e.g. pmtmr=0x508
|
||||
|
||||
pnp.debug [PNP]
|
||||
Enable PNP debug messages. This depends on the
|
||||
CONFIG_PNP_DEBUG_MESSAGES option.
|
||||
pnp.debug=1 [PNP]
|
||||
Enable PNP debug messages (depends on the
|
||||
CONFIG_PNP_DEBUG_MESSAGES option). Change at run-time
|
||||
via /sys/module/pnp/parameters/debug. We always show
|
||||
current resource usage; turning this on also shows
|
||||
possible settings and some assignment information.
|
||||
|
||||
pnpacpi= [ACPI]
|
||||
{ off }
|
||||
|
|
|
@ -1,3 +1,5 @@
|
|||
Note: This driver doesn't have a maintainer.
|
||||
|
||||
Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux.
|
||||
|
||||
This program is free software; you can redistribute it and/or
|
||||
|
@ -55,7 +57,6 @@ Test and make sure PCI latency is now correct for all cases.
|
|||
Authors:
|
||||
|
||||
Sten Wang <sten_wang@davicom.com.tw > : Original Author
|
||||
Tobias Ringstrom <tori@unhappy.mine.nu> : Current Maintainer
|
||||
|
||||
Contributors:
|
||||
|
||||
|
|
|
@ -123,10 +123,11 @@ be automatically shutdown if it's set to "never".
|
|||
khugepaged runs usually at low frequency so while one may not want to
|
||||
invoke defrag algorithms synchronously during the page faults, it
|
||||
should be worth invoking defrag at least in khugepaged. However it's
|
||||
also possible to disable defrag in khugepaged:
|
||||
also possible to disable defrag in khugepaged by writing 0 or enable
|
||||
defrag in khugepaged by writing 1:
|
||||
|
||||
echo yes >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo no >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo 0 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
echo 1 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag
|
||||
|
||||
You can also control how many pages khugepaged should scan at each
|
||||
pass:
|
||||
|
|
23
MAINTAINERS
23
MAINTAINERS
|
@ -1278,7 +1278,6 @@ F: drivers/input/misc/ati_remote2.c
|
|||
ATLX ETHERNET DRIVERS
|
||||
M: Jay Cliburn <jcliburn@gmail.com>
|
||||
M: Chris Snook <chris.snook@gmail.com>
|
||||
M: Jie Yang <jie.yang@atheros.com>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://sourceforge.net/projects/atl1
|
||||
W: http://atl1.sourceforge.net
|
||||
|
@ -1574,7 +1573,6 @@ F: drivers/scsi/bfa/
|
|||
|
||||
BROCADE BNA 10 GIGABIT ETHERNET DRIVER
|
||||
M: Rasesh Mody <rmody@brocade.com>
|
||||
M: Debashis Dutt <ddutt@brocade.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/net/bna/
|
||||
|
@ -1758,7 +1756,6 @@ F: Documentation/zh_CN/
|
|||
|
||||
CISCO VIC ETHERNET NIC DRIVER
|
||||
M: Christian Benvenuti <benve@cisco.com>
|
||||
M: Vasanthy Kolluri <vkolluri@cisco.com>
|
||||
M: Roopa Prabhu <roprabhu@cisco.com>
|
||||
M: David Wang <dwang2@cisco.com>
|
||||
S: Supported
|
||||
|
@ -3262,6 +3259,17 @@ F: Documentation/input/multi-touch-protocol.txt
|
|||
F: drivers/input/input-mt.c
|
||||
K: \b(ABS|SYN)_MT_
|
||||
|
||||
INTEL C600 SERIES SAS CONTROLLER DRIVER
|
||||
M: Intel SCU Linux support <intel-linux-scu@intel.com>
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
M: Ed Nadolski <edmund.nadolski@intel.com>
|
||||
L: linux-scsi@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git
|
||||
S: Maintained
|
||||
F: drivers/scsi/isci/
|
||||
F: firmware/isci/
|
||||
|
||||
INTEL IDLE DRIVER
|
||||
M: Len Brown <lenb@kernel.org>
|
||||
L: linux-pm@lists.linux-foundation.org
|
||||
|
@ -4404,7 +4412,8 @@ L: netfilter@vger.kernel.org
|
|||
L: coreteam@netfilter.org
|
||||
W: http://www.netfilter.org/
|
||||
W: http://www.iptables.org/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-2.6.git
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next-2.6.git
|
||||
S: Supported
|
||||
F: include/linux/netfilter*
|
||||
F: include/linux/netfilter/
|
||||
|
@ -4774,7 +4783,7 @@ F: drivers/net/wireless/orinoco/
|
|||
|
||||
OSD LIBRARY and FILESYSTEM
|
||||
M: Boaz Harrosh <bharrosh@panasas.com>
|
||||
M: Benny Halevy <bhalevy@panasas.com>
|
||||
M: Benny Halevy <bhalevy@tonian.com>
|
||||
L: osd-dev@open-osd.org
|
||||
W: http://open-osd.org
|
||||
T: git git://git.open-osd.org/open-osd.git
|
||||
|
@ -7200,6 +7209,9 @@ W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
|
|||
S: Supported
|
||||
F: Documentation/hwmon/wm83??
|
||||
F: drivers/leds/leds-wm83*.c
|
||||
F: drivers/input/misc/wm831x-on.c
|
||||
F: drivers/input/touchscreen/wm831x-ts.c
|
||||
F: drivers/input/touchscreen/wm97*.c
|
||||
F: drivers/mfd/wm8*.c
|
||||
F: drivers/power/wm83*.c
|
||||
F: drivers/rtc/rtc-wm83*.c
|
||||
|
@ -7209,6 +7221,7 @@ F: drivers/watchdog/wm83*_wdt.c
|
|||
F: include/linux/mfd/wm831x/
|
||||
F: include/linux/mfd/wm8350/
|
||||
F: include/linux/mfd/wm8400*
|
||||
F: include/linux/wm97xx.h
|
||||
F: include/sound/wm????.h
|
||||
F: sound/soc/codecs/wm*
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 1
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION = -rc8
|
||||
NAME = "Divemaster Edition"
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -51,7 +51,7 @@ config GENERIC_CMOS_UPDATE
|
|||
def_bool y
|
||||
|
||||
config GENERIC_GPIO
|
||||
def_bool y
|
||||
bool
|
||||
|
||||
config ZONE_DMA
|
||||
bool
|
||||
|
|
|
@ -725,9 +725,6 @@ config ARCH_S3C64XX
|
|||
select SAMSUNG_IRQ_VIC_TIMER
|
||||
select SAMSUNG_IRQ_UART
|
||||
select S3C_GPIO_TRACK
|
||||
select S3C_GPIO_PULL_UPDOWN
|
||||
select S3C_GPIO_CFG_S3C24XX
|
||||
select S3C_GPIO_CFG_S3C64XX
|
||||
select S3C_DEV_NAND
|
||||
select USB_ARCH_HAS_OHCI
|
||||
select SAMSUNG_GPIOLIB_4BIT
|
||||
|
@ -1284,6 +1281,20 @@ config ARM_ERRATA_364296
|
|||
processor into full low interrupt latency mode. ARM11MPCore
|
||||
is not affected.
|
||||
|
||||
config ARM_ERRATA_764369
|
||||
bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
|
||||
depends on CPU_V7 && SMP
|
||||
help
|
||||
This option enables the workaround for erratum 764369
|
||||
affecting Cortex-A9 MPCore with two or more processors (all
|
||||
current revisions). Under certain timing circumstances, a data
|
||||
cache line maintenance operation by MVA targeting an Inner
|
||||
Shareable memory region may fail to proceed up to either the
|
||||
Point of Coherency or to the Point of Unification of the
|
||||
system. This workaround adds a DSB instruction before the
|
||||
relevant cache maintenance functions and sets a specific bit
|
||||
in the diagnostic control register of the SCU.
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/arm/common/Kconfig"
|
||||
|
@ -2083,7 +2094,7 @@ menu "Power management options"
|
|||
source "kernel/power/Kconfig"
|
||||
|
||||
config ARCH_SUSPEND_POSSIBLE
|
||||
depends on !ARCH_S5P64X0 && !ARCH_S5PC100
|
||||
depends on !ARCH_S5PC100
|
||||
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
|
||||
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
|
||||
def_bool y
|
||||
|
|
|
@ -57,14 +57,14 @@
|
|||
};
|
||||
|
||||
sdhci@c8000200 {
|
||||
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
|
||||
<&gpio 57 0>, /* wp, gpio PH1 */
|
||||
<&gpio 155 0>; /* power, gpio PT3 */
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
gpios = <&gpio 58 0>, /* cd, gpio PH2 */
|
||||
<&gpio 59 0>, /* wp, gpio PH3 */
|
||||
<&gpio 70 0>; /* power, gpio PI6 */
|
||||
cd-gpios = <&gpio 58 0>; /* gpio PH2 */
|
||||
wp-gpios = <&gpio 59 0>; /* gpio PH3 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -21,8 +21,8 @@
|
|||
};
|
||||
|
||||
sdhci@c8000400 {
|
||||
gpios = <&gpio 69 0>, /* cd, gpio PI5 */
|
||||
<&gpio 57 0>, /* wp, gpio PH1 */
|
||||
<&gpio 70 0>; /* power, gpio PI6 */
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 70 0>; /* gpio PI6 */
|
||||
};
|
||||
};
|
||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y
|
|||
CONFIG_MACH_ARMLEX4210=y
|
||||
CONFIG_MACH_UNIVERSAL_C210=y
|
||||
CONFIG_MACH_NURI=y
|
||||
CONFIG_MACH_ORIGEN=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SMP=y
|
||||
|
|
|
@ -25,17 +25,17 @@
|
|||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"1: ldrex %1, [%2]\n" \
|
||||
"1: ldrex %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: strex %1, %0, [%2]\n" \
|
||||
" teq %1, #0\n" \
|
||||
"2: strex %2, %0, [%3]\n" \
|
||||
" teq %2, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%4") \
|
||||
: "=&r" (ret), "=&r" (oldval) \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
|
||||
|
@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
#include <linux/preempt.h>
|
||||
#include <asm/domain.h>
|
||||
|
||||
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(ldr) " %1, [%2]\n" \
|
||||
"1: " T(ldr) " %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: " T(str) " %0, [%2]\n" \
|
||||
"2: " T(str) " %0, [%3]\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%4") \
|
||||
: "=&r" (ret), "=&r" (oldval) \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
|
||||
: "cc", "memory")
|
||||
|
||||
|
@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
|||
int cmp = (encoded_op >> 24) & 15;
|
||||
int oparg = (encoded_op << 8) >> 20;
|
||||
int cmparg = (encoded_op << 20) >> 20;
|
||||
int oldval = 0, ret;
|
||||
int oldval = 0, ret, tmp;
|
||||
|
||||
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
|
||||
oparg = 1 << oparg;
|
||||
|
@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
|
|||
|
||||
switch (op) {
|
||||
case FUTEX_OP_SET:
|
||||
__futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_ADD:
|
||||
__futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_OR:
|
||||
__futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
case FUTEX_OP_ANDN:
|
||||
__futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg);
|
||||
__futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg);
|
||||
break;
|
||||
case FUTEX_OP_XOR:
|
||||
__futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg);
|
||||
__futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg);
|
||||
break;
|
||||
default:
|
||||
ret = -ENOSYS;
|
||||
|
|
|
@ -21,6 +21,9 @@
|
|||
* OneNAND features.
|
||||
*/
|
||||
|
||||
#ifndef ASM_PL080_H
|
||||
#define ASM_PL080_H
|
||||
|
||||
#define PL080_INT_STATUS (0x00)
|
||||
#define PL080_TC_STATUS (0x04)
|
||||
#define PL080_TC_CLEAR (0x08)
|
||||
|
@ -138,3 +141,4 @@ struct pl080s_lli {
|
|||
u32 control1;
|
||||
};
|
||||
|
||||
#endif /* ASM_PL080_H */
|
||||
|
|
|
@ -478,8 +478,8 @@
|
|||
/*
|
||||
* Unimplemented (or alternatively implemented) syscalls
|
||||
*/
|
||||
#define __IGNORE_fadvise64_64 1
|
||||
#define __IGNORE_migrate_pages 1
|
||||
#define __IGNORE_fadvise64_64
|
||||
#define __IGNORE_migrate_pages
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASM_ARM_UNISTD_H */
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
|
||||
#define SCU_CTRL 0x00
|
||||
#define SCU_CONFIG 0x04
|
||||
|
@ -37,6 +38,15 @@ void __init scu_enable(void __iomem *scu_base)
|
|||
{
|
||||
u32 scu_ctrl;
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_764369
|
||||
/* Cortex-A9 only */
|
||||
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
|
||||
scu_ctrl = __raw_readl(scu_base + 0x30);
|
||||
if (!(scu_ctrl & 1))
|
||||
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
|
||||
}
|
||||
#endif
|
||||
|
||||
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
|
||||
/* already enabled? */
|
||||
if (scu_ctrl & 1)
|
||||
|
|
|
@ -23,8 +23,10 @@
|
|||
|
||||
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
|
||||
#define ARM_EXIT_KEEP(x) x
|
||||
#define ARM_EXIT_DISCARD(x)
|
||||
#else
|
||||
#define ARM_EXIT_KEEP(x)
|
||||
#define ARM_EXIT_DISCARD(x) x
|
||||
#endif
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
|
@ -39,6 +41,11 @@ jiffies = jiffies_64 + 4;
|
|||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* XXX: The linker does not define how output sections are
|
||||
* assigned to input sections when there are multiple statements
|
||||
* matching the same input section name. There is no documented
|
||||
* order of matching.
|
||||
*
|
||||
* unwind exit sections must be discarded before the rest of the
|
||||
* unwind sections get included.
|
||||
*/
|
||||
|
@ -47,6 +54,9 @@ SECTIONS
|
|||
*(.ARM.extab.exit.text)
|
||||
ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
|
||||
ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
|
||||
ARM_EXIT_DISCARD(EXIT_TEXT)
|
||||
ARM_EXIT_DISCARD(EXIT_DATA)
|
||||
EXIT_CALL
|
||||
#ifndef CONFIG_HOTPLUG
|
||||
*(.ARM.exidx.devexit.text)
|
||||
*(.ARM.extab.devexit.text)
|
||||
|
@ -58,6 +68,8 @@ SECTIONS
|
|||
#ifndef CONFIG_SMP_ON_UP
|
||||
*(.alt.smp.init)
|
||||
#endif
|
||||
*(.discard)
|
||||
*(.discard.*)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
|
@ -279,9 +291,6 @@ SECTIONS
|
|||
|
||||
STABS_DEBUG
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* Default discards */
|
||||
DISCARDS
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -158,7 +158,7 @@ void __init dove_spi0_init(void)
|
|||
|
||||
void __init dove_spi1_init(void)
|
||||
{
|
||||
orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk());
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
|
|
@ -11,10 +11,24 @@ if ARCH_EXYNOS4
|
|||
|
||||
config CPU_EXYNOS4210
|
||||
bool
|
||||
select S3C_PL330_DMA
|
||||
select SAMSUNG_DMADEV
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
help
|
||||
Enable EXYNOS4210 CPU support
|
||||
|
||||
config SOC_EXYNOS4212
|
||||
bool
|
||||
select S5P_PM if PM
|
||||
select S5P_SLEEP if PM
|
||||
help
|
||||
Enable EXYNOS4212 SoC support
|
||||
|
||||
config SOC_EXYNOS4412
|
||||
bool
|
||||
help
|
||||
Enable EXYNOS4412 SoC support
|
||||
|
||||
config EXYNOS4_MCT
|
||||
bool
|
||||
default y
|
||||
|
@ -111,24 +125,11 @@ config EXYNOS4_SETUP_USB_PHY
|
|||
|
||||
menu "EXYNOS4 Machines"
|
||||
|
||||
comment "EXYNOS4210 Boards"
|
||||
|
||||
config MACH_SMDKC210
|
||||
bool "SMDKC210"
|
||||
select CPU_EXYNOS4210
|
||||
select S5P_DEV_FIMD0
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select EXYNOS4_DEV_PD
|
||||
select EXYNOS4_DEV_SYSMMU
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select MACH_SMDKV310
|
||||
help
|
||||
Machine support for Samsung SMDKC210
|
||||
|
||||
|
@ -139,6 +140,14 @@ config MACH_SMDKV310
|
|||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_I2C1
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_I2C_HDMIPHY
|
||||
select S5P_DEV_MFC
|
||||
select S5P_DEV_TV
|
||||
select S5P_DEV_USB_EHCI
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
|
@ -153,6 +162,7 @@ config MACH_SMDKV310
|
|||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_KEYPAD
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select EXYNOS4_SETUP_USB_PHY
|
||||
help
|
||||
Machine support for Samsung SMDKV310
|
||||
|
||||
|
@ -178,19 +188,26 @@ config MACH_UNIVERSAL_C210
|
|||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_CSIS0
|
||||
select S5P_DEV_FIMD0
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C3
|
||||
select S3C_DEV_I2C5
|
||||
select S5P_DEV_I2C_HDMIPHY
|
||||
select S5P_DEV_MFC
|
||||
select S5P_DEV_ONENAND
|
||||
select S5P_DEV_TV
|
||||
select EXYNOS4_DEV_PD
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C5
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select EXYNOS4_SETUP_FIMC
|
||||
select S5P_SETUP_MIPIPHY
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
|
@ -199,6 +216,8 @@ config MACH_NURI
|
|||
bool "Mobile NURI Board"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_RTC
|
||||
select S5P_DEV_FIMD0
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
|
@ -208,6 +227,7 @@ config MACH_NURI
|
|||
select S5P_DEV_MFC
|
||||
select S5P_DEV_USB_EHCI
|
||||
select EXYNOS4_DEV_PD
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C5
|
||||
|
@ -218,6 +238,62 @@ config MACH_NURI
|
|||
help
|
||||
Machine support for Samsung Mobile NURI Board.
|
||||
|
||||
config MACH_ORIGEN
|
||||
bool "ORIGEN"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_FIMD0
|
||||
select S5P_DEV_I2C_HDMIPHY
|
||||
select S5P_DEV_TV
|
||||
select S5P_DEV_USB_EHCI
|
||||
select EXYNOS4_DEV_PD
|
||||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select SAMSUNG_DEV_PWM
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select EXYNOS4_SETUP_USB_PHY
|
||||
help
|
||||
Machine support for ORIGEN based on Samsung EXYNOS4210
|
||||
|
||||
comment "EXYNOS4212 Boards"
|
||||
|
||||
config MACH_SMDK4212
|
||||
bool "SMDK4212"
|
||||
select SOC_EXYNOS4212
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C3
|
||||
select S3C_DEV_I2C7
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C7
|
||||
select EXYNOS4_SETUP_KEYPAD
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
help
|
||||
Machine support for Samsung SMDK4212
|
||||
|
||||
comment "EXYNOS4412 Boards"
|
||||
|
||||
config MACH_SMDK4412
|
||||
bool "SMDK4412"
|
||||
select SOC_EXYNOS4412
|
||||
select MACH_SMDK4212
|
||||
help
|
||||
Machine support for Samsung SMDK4412
|
||||
|
||||
endmenu
|
||||
|
||||
comment "Configuration for HSMMC bus width"
|
||||
|
|
|
@ -12,9 +12,11 @@ obj- :=
|
|||
|
||||
# Core support for EXYNOS4 system
|
||||
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
|
||||
obj-$(CONFIG_PM) += pm.o sleep.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
|
||||
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
|
||||
obj-$(CONFIG_PM) += pm.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
@ -25,11 +27,15 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
|||
|
||||
# machine support
|
||||
|
||||
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
|
||||
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o
|
||||
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
|
||||
obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
|
||||
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
|
||||
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
|
||||
obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
|
||||
|
||||
obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
|
||||
obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
|
||||
|
||||
# device support
|
||||
|
||||
|
|
139
arch/arm/mach-exynos4/clock-exynos4210.c
Normal file
139
arch/arm/mach-exynos4/clock-exynos4210.c
Normal file
|
@ -0,0 +1,139 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/clock-exynos4210.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
static struct sleep_save exynos4210_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD1),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
{
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_mout_corebus,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
{
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4210_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4210_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4210_clock_suspend NULL
|
||||
#define exynos4210_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4210_clock_syscore_ops = {
|
||||
.suspend = exynos4210_clock_suspend,
|
||||
.resume = exynos4210_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4210_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;
|
||||
clk_mout_mpll.reg_src.shift = 8;
|
||||
clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4210_clock_syscore_ops);
|
||||
}
|
118
arch/arm/mach-exynos4/clock-exynos4212.c
Normal file
118
arch/arm/mach-exynos4/clock-exynos4212.c
Normal file
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/clock-exynos4212.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4212 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
static struct sleep_save exynos4212_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),
|
||||
};
|
||||
|
||||
static struct clk *clk_src_mpll_user_list[] = {
|
||||
[0] = &clk_fin_mpll,
|
||||
[1] = &clk_mout_mpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clk_src_mpll_user = {
|
||||
.sources = clk_src_mpll_user_list,
|
||||
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_mpll_user = {
|
||||
.clk = {
|
||||
.name = "mout_mpll_user",
|
||||
},
|
||||
.sources = &clk_src_mpll_user,
|
||||
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
&clk_mout_mpll_user,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clksrcs[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4212_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4212_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4212_clock_suspend NULL
|
||||
#define exynos4212_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4212_clock_syscore_ops = {
|
||||
.suspend = exynos4212_clock_suspend,
|
||||
.resume = exynos4212_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4212_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
||||
/* usbphy1 is removed */
|
||||
clkset_group_list[4] = NULL;
|
||||
|
||||
/* mout_mpll_user is used */
|
||||
clkset_group_list[6] = &clk_mout_mpll_user.clk;
|
||||
clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
|
||||
|
||||
clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;
|
||||
clk_mout_mpll.reg_src.shift = 12;
|
||||
clk_mout_mpll.reg_src.size = 1;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4212_clock_syscore_ops);
|
||||
}
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/syscore_ops.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
|
@ -20,29 +21,101 @@
|
|||
#include <plat/pll.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/sysmmu.h>
|
||||
#include <mach/exynos4-clock.h>
|
||||
|
||||
static struct clk clk_sclk_hdmi27m = {
|
||||
static struct sleep_save exynos4_clock_save[] = {
|
||||
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
|
||||
SAVE_ITEM(S5P_CLKSRC_TOP0),
|
||||
SAVE_ITEM(S5P_CLKSRC_TOP1),
|
||||
SAVE_ITEM(S5P_CLKSRC_CAM),
|
||||
SAVE_ITEM(S5P_CLKSRC_TV),
|
||||
SAVE_ITEM(S5P_CLKSRC_MFC),
|
||||
SAVE_ITEM(S5P_CLKSRC_G3D),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKSRC_FSYS),
|
||||
SAVE_ITEM(S5P_CLKSRC_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKSRC_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV_CAM),
|
||||
SAVE_ITEM(S5P_CLKDIV_TV),
|
||||
SAVE_ITEM(S5P_CLKDIV_MFC),
|
||||
SAVE_ITEM(S5P_CLKDIV_G3D),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD0),
|
||||
SAVE_ITEM(S5P_CLKDIV_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS0),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS1),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS2),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS3),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL2),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL3),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL4),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL5),
|
||||
SAVE_ITEM(S5P_CLKDIV_TOP),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_TV),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV2_RATIO),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CAM),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_TV),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_MFC),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_G3D),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_GPS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
|
||||
SAVE_ITEM(S5P_CLKGATE_BLOCK),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
|
||||
SAVE_ITEM(S5P_CLKSRC_DMC),
|
||||
SAVE_ITEM(S5P_CLKDIV_DMC0),
|
||||
SAVE_ITEM(S5P_CLKDIV_DMC1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_DMC),
|
||||
SAVE_ITEM(S5P_CLKSRC_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
|
||||
};
|
||||
|
||||
struct clk clk_sclk_hdmi27m = {
|
||||
.name = "sclk_hdmi27m",
|
||||
.rate = 27000000,
|
||||
};
|
||||
|
||||
static struct clk clk_sclk_hdmiphy = {
|
||||
struct clk clk_sclk_hdmiphy = {
|
||||
.name = "sclk_hdmiphy",
|
||||
};
|
||||
|
||||
static struct clk clk_sclk_usbphy0 = {
|
||||
struct clk clk_sclk_usbphy0 = {
|
||||
.name = "sclk_usbphy0",
|
||||
.rate = 27000000,
|
||||
};
|
||||
|
||||
static struct clk clk_sclk_usbphy1 = {
|
||||
struct clk clk_sclk_usbphy1 = {
|
||||
.name = "sclk_usbphy1",
|
||||
};
|
||||
|
||||
static struct clk dummy_apb_pclk = {
|
||||
.name = "apb_pclk",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
|
||||
|
@ -58,12 +131,7 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
|
|||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
|
||||
int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
|
||||
}
|
||||
|
@ -83,6 +151,11 @@ static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
|
|||
return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
|
||||
|
@ -103,12 +176,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
|
|||
return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
|
||||
int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
|
||||
int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
|
||||
}
|
||||
|
@ -123,6 +196,16 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
|
|||
return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
|
||||
}
|
||||
|
||||
/* Core list of CMU_CPU side */
|
||||
|
||||
static struct clksrc_clk clk_mout_apll = {
|
||||
|
@ -133,7 +216,7 @@ static struct clksrc_clk clk_mout_apll = {
|
|||
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_apll = {
|
||||
struct clksrc_clk clk_sclk_apll = {
|
||||
.clk = {
|
||||
.name = "sclk_apll",
|
||||
.parent = &clk_mout_apll.clk,
|
||||
|
@ -141,7 +224,7 @@ static struct clksrc_clk clk_sclk_apll = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_epll = {
|
||||
struct clksrc_clk clk_mout_epll = {
|
||||
.clk = {
|
||||
.name = "mout_epll",
|
||||
},
|
||||
|
@ -149,12 +232,13 @@ static struct clksrc_clk clk_mout_epll = {
|
|||
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_mout_mpll = {
|
||||
struct clksrc_clk clk_mout_mpll = {
|
||||
.clk = {
|
||||
.name = "mout_mpll",
|
||||
},
|
||||
.sources = &clk_src_mpll,
|
||||
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
|
||||
|
||||
/* reg_src will be added in each SoCs' clock */
|
||||
};
|
||||
|
||||
static struct clk *clkset_moutcore_list[] = {
|
||||
|
@ -224,12 +308,12 @@ static struct clksrc_clk clk_periphclk = {
|
|||
|
||||
/* Core list of CMU_CORE side */
|
||||
|
||||
static struct clk *clkset_corebus_list[] = {
|
||||
struct clk *clkset_corebus_list[] = {
|
||||
[0] = &clk_mout_mpll.clk,
|
||||
[1] = &clk_sclk_apll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_mout_corebus = {
|
||||
struct clksrc_sources clkset_mout_corebus = {
|
||||
.sources = clkset_corebus_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_corebus_list),
|
||||
};
|
||||
|
@ -284,12 +368,12 @@ static struct clksrc_clk clk_pclk_acp = {
|
|||
|
||||
/* Core list of CMU_TOP side */
|
||||
|
||||
static struct clk *clkset_aclk_top_list[] = {
|
||||
struct clk *clkset_aclk_top_list[] = {
|
||||
[0] = &clk_mout_mpll.clk,
|
||||
[1] = &clk_sclk_apll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_aclk = {
|
||||
struct clksrc_sources clkset_aclk = {
|
||||
.sources = clkset_aclk_top_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
|
||||
};
|
||||
|
@ -321,7 +405,7 @@ static struct clksrc_clk clk_aclk_160 = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_aclk_133 = {
|
||||
struct clksrc_clk clk_aclk_133 = {
|
||||
.clk = {
|
||||
.name = "aclk_133",
|
||||
},
|
||||
|
@ -360,7 +444,7 @@ static struct clksrc_sources clkset_sclk_vpll = {
|
|||
.nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_vpll = {
|
||||
struct clksrc_clk clk_sclk_vpll = {
|
||||
.clk = {
|
||||
.name = "sclk_vpll",
|
||||
},
|
||||
|
@ -409,16 +493,6 @@ static struct clk init_clocks_off[] = {
|
|||
.devname = "exynos4-fb.0",
|
||||
.enable = exynos4_clk_ip_lcd0_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sataphy",
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
|
@ -448,19 +522,49 @@ static struct clk init_clocks_off[] = {
|
|||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 9),
|
||||
}, {
|
||||
.name = "dac",
|
||||
.devname = "s5p-sdo",
|
||||
.enable = exynos4_clk_ip_tv_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}, {
|
||||
.name = "mixer",
|
||||
.devname = "s5p-mixer",
|
||||
.enable = exynos4_clk_ip_tv_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "vp",
|
||||
.devname = "s5p-mixer",
|
||||
.enable = exynos4_clk_ip_tv_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "hdmi",
|
||||
.devname = "exynos4-hdmi",
|
||||
.enable = exynos4_clk_ip_tv_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "hdmiphy",
|
||||
.devname = "exynos4-hdmi",
|
||||
.enable = exynos4_clk_hdmiphy_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "dacphy",
|
||||
.devname = "s5p-sdo",
|
||||
.enable = exynos4_clk_dac_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.devname = "s3c-pl330.0",
|
||||
.name = "dma",
|
||||
.devname = "dma-pl330.0",
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.devname = "s3c-pl330.1",
|
||||
.name = "dma",
|
||||
.devname = "dma-pl330.1",
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
|
@ -580,6 +684,12 @@ static struct clk init_clocks_off[] = {
|
|||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.devname = "s3c2440-hdmiphy-i2c",
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 14),
|
||||
}, {
|
||||
.name = "SYSMMU_MDMA",
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
|
@ -673,7 +783,7 @@ static struct clk init_clocks[] = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct clk *clkset_group_list[] = {
|
||||
struct clk *clkset_group_list[] = {
|
||||
[0] = &clk_ext_xtal_mux,
|
||||
[1] = &clk_xusbxti,
|
||||
[2] = &clk_sclk_hdmi27m,
|
||||
|
@ -685,7 +795,7 @@ static struct clk *clkset_group_list[] = {
|
|||
[8] = &clk_sclk_vpll.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_group = {
|
||||
struct clksrc_sources clkset_group = {
|
||||
.sources = clkset_group_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_group_list),
|
||||
};
|
||||
|
@ -782,6 +892,81 @@ static struct clksrc_sources clkset_mout_mfc = {
|
|||
.nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
|
||||
};
|
||||
|
||||
static struct clk *clkset_sclk_dac_list[] = {
|
||||
[0] = &clk_sclk_vpll.clk,
|
||||
[1] = &clk_sclk_hdmiphy,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_sclk_dac = {
|
||||
.sources = clkset_sclk_dac_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_dac = {
|
||||
.clk = {
|
||||
.name = "sclk_dac",
|
||||
.enable = exynos4_clksrc_mask_tv_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
.sources = &clkset_sclk_dac,
|
||||
.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_pixel = {
|
||||
.clk = {
|
||||
.name = "sclk_pixel",
|
||||
.parent = &clk_sclk_vpll.clk,
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
|
||||
};
|
||||
|
||||
static struct clk *clkset_sclk_hdmi_list[] = {
|
||||
[0] = &clk_sclk_pixel.clk,
|
||||
[1] = &clk_sclk_hdmiphy,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_sclk_hdmi = {
|
||||
.sources = clkset_sclk_hdmi_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_hdmi = {
|
||||
.clk = {
|
||||
.name = "sclk_hdmi",
|
||||
.enable = exynos4_clksrc_mask_tv_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_sclk_hdmi,
|
||||
.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clk *clkset_sclk_mixer_list[] = {
|
||||
[0] = &clk_sclk_dac.clk,
|
||||
[1] = &clk_sclk_hdmi.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_sources clkset_sclk_mixer = {
|
||||
.sources = clkset_sclk_mixer_list,
|
||||
.nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_sclk_mixer = {
|
||||
.clk = {
|
||||
.name = "sclk_mixer",
|
||||
.enable = exynos4_clksrc_mask_tv_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
.sources = &clkset_sclk_mixer,
|
||||
.reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk *sclk_tv[] = {
|
||||
&clk_sclk_dac,
|
||||
&clk_sclk_pixel,
|
||||
&clk_sclk_hdmi,
|
||||
&clk_sclk_mixer,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_dout_mmc0 = {
|
||||
.clk = {
|
||||
.name = "dout_mmc0",
|
||||
|
@ -899,8 +1084,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "exynos4-fimc.0",
|
||||
.name = "sclk_cam0",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
|
@ -909,8 +1093,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.devname = "exynos4-fimc.1",
|
||||
.name = "sclk_cam1",
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
|
@ -967,25 +1150,6 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.devname = "exynos4-fb.1",
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_mout_corebus,
|
||||
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
|
@ -1116,20 +1280,91 @@ static int xtal_rate;
|
|||
|
||||
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
|
||||
{
|
||||
return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
|
||||
if (soc_is_exynos4210())
|
||||
return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
|
||||
pll_4508);
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops exynos4_fout_apll_ops = {
|
||||
.get_rate = exynos4_fout_apll_get_rate,
|
||||
};
|
||||
|
||||
static u32 vpll_div[][8] = {
|
||||
{ 54000000, 3, 53, 3, 1024, 0, 17, 0 },
|
||||
{ 108000000, 3, 53, 2, 1024, 0, 17, 0 },
|
||||
};
|
||||
|
||||
static unsigned long exynos4_vpll_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk->rate;
|
||||
}
|
||||
|
||||
static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
|
||||
{
|
||||
unsigned int vpll_con0, vpll_con1 = 0;
|
||||
unsigned int i;
|
||||
|
||||
/* Return if nothing changed */
|
||||
if (clk->rate == rate)
|
||||
return 0;
|
||||
|
||||
vpll_con0 = __raw_readl(S5P_VPLL_CON0);
|
||||
vpll_con0 &= ~(0x1 << 27 | \
|
||||
PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
|
||||
PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
|
||||
PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
|
||||
|
||||
vpll_con1 = __raw_readl(S5P_VPLL_CON1);
|
||||
vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
|
||||
PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
|
||||
PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
|
||||
if (vpll_div[i][0] == rate) {
|
||||
vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
|
||||
vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
|
||||
vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
|
||||
vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
|
||||
vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
|
||||
vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
|
||||
vpll_con0 |= vpll_div[i][7] << 27;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == ARRAY_SIZE(vpll_div)) {
|
||||
printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
|
||||
__func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
__raw_writel(vpll_con0, S5P_VPLL_CON0);
|
||||
__raw_writel(vpll_con1, S5P_VPLL_CON1);
|
||||
|
||||
/* Wait for VPLL lock */
|
||||
while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
|
||||
continue;
|
||||
|
||||
clk->rate = rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk_ops exynos4_vpll_ops = {
|
||||
.get_rate = exynos4_vpll_get_rate,
|
||||
.set_rate = exynos4_vpll_set_rate,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq exynos4_setup_clocks(void)
|
||||
{
|
||||
struct clk *xtal_clk;
|
||||
unsigned long apll;
|
||||
unsigned long mpll;
|
||||
unsigned long epll;
|
||||
unsigned long vpll;
|
||||
unsigned long apll = 0;
|
||||
unsigned long mpll = 0;
|
||||
unsigned long epll = 0;
|
||||
unsigned long vpll = 0;
|
||||
unsigned long vpllsrc;
|
||||
unsigned long xtal;
|
||||
unsigned long armclk;
|
||||
|
@ -1153,18 +1388,34 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
|
|||
|
||||
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
|
||||
|
||||
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
|
||||
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
|
||||
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
|
||||
__raw_readl(S5P_EPLL_CON1), pll_4600);
|
||||
if (soc_is_exynos4210()) {
|
||||
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
|
||||
pll_4508);
|
||||
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
|
||||
pll_4508);
|
||||
epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
|
||||
__raw_readl(S5P_EPLL_CON1), pll_4600);
|
||||
|
||||
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
||||
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650);
|
||||
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
||||
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650c);
|
||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
|
||||
mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
|
||||
epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
|
||||
__raw_readl(S5P_EPLL_CON1));
|
||||
|
||||
vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
|
||||
vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
||||
__raw_readl(S5P_VPLL_CON1));
|
||||
} else {
|
||||
/* nothing */
|
||||
}
|
||||
|
||||
clk_fout_apll.ops = &exynos4_fout_apll_ops;
|
||||
clk_fout_mpll.rate = mpll;
|
||||
clk_fout_epll.rate = epll;
|
||||
clk_fout_vpll.ops = &exynos4_vpll_ops;
|
||||
clk_fout_vpll.rate = vpll;
|
||||
|
||||
printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
|
||||
|
@ -1192,7 +1443,32 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
|
|||
}
|
||||
|
||||
static struct clk *clks[] __initdata = {
|
||||
/* Nothing here yet */
|
||||
&clk_sclk_hdmi27m,
|
||||
&clk_sclk_hdmiphy,
|
||||
&clk_sclk_usbphy0,
|
||||
&clk_sclk_usbphy1,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int exynos4_clock_suspend(void)
|
||||
{
|
||||
s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4_clock_resume(void)
|
||||
{
|
||||
s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
|
||||
}
|
||||
|
||||
#else
|
||||
#define exynos4_clock_suspend NULL
|
||||
#define exynos4_clock_resume NULL
|
||||
#endif
|
||||
|
||||
struct syscore_ops exynos4_clock_syscore_ops = {
|
||||
.suspend = exynos4_clock_suspend,
|
||||
.resume = exynos4_clock_resume,
|
||||
};
|
||||
|
||||
void __init exynos4_register_clocks(void)
|
||||
|
@ -1204,11 +1480,17 @@ void __init exynos4_register_clocks(void)
|
|||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
|
||||
s3c_register_clksrc(sclk_tv[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
||||
|
||||
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
|
||||
|
||||
register_syscore_ops(&exynos4_clock_syscore_ops);
|
||||
s3c24xx_register_clock(&dummy_apb_pclk);
|
||||
|
||||
s3c_pwmclk_init();
|
||||
}
|
||||
|
|
|
@ -28,10 +28,13 @@
|
|||
#include <plat/fimc-core.h>
|
||||
#include <plat/iic-core.h>
|
||||
#include <plat/reset.h>
|
||||
#include <plat/tv-core.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
unsigned int gic_bank_offset __read_mostly;
|
||||
|
||||
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
|
||||
unsigned int irq_start);
|
||||
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
|
||||
|
@ -43,11 +46,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_CMU,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
|
||||
|
@ -121,6 +119,24 @@ static struct map_desc exynos4_iodesc[] __initdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos4_iodesc0[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc exynos4_iodesc1[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static void exynos4_idle(void)
|
||||
{
|
||||
if (!need_resched())
|
||||
|
@ -143,6 +159,11 @@ void __init exynos4_map_io(void)
|
|||
{
|
||||
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
|
||||
|
||||
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
|
||||
iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
|
||||
else
|
||||
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
|
||||
|
||||
/* initialize device information early */
|
||||
exynos4_default_sdhci0();
|
||||
exynos4_default_sdhci1();
|
||||
|
@ -162,6 +183,7 @@ void __init exynos4_map_io(void)
|
|||
s3c_i2c2_setname("s3c2440-i2c");
|
||||
|
||||
s5p_fb_setname(0, "exynos4-fb");
|
||||
s5p_hdmi_setname("exynos4-hdmi");
|
||||
}
|
||||
|
||||
void __init exynos4_init_clocks(int xtal)
|
||||
|
@ -170,24 +192,37 @@ void __init exynos4_init_clocks(int xtal)
|
|||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
exynos4210_register_clocks();
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
exynos4212_register_clocks();
|
||||
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
static void exynos4_gic_irq_eoi(struct irq_data *d)
|
||||
static void exynos4_gic_irq_fix_base(struct irq_data *d)
|
||||
{
|
||||
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
|
||||
|
||||
gic_data->cpu_base = S5P_VA_GIC_CPU +
|
||||
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
|
||||
(gic_bank_offset * smp_processor_id());
|
||||
|
||||
gic_data->dist_base = S5P_VA_GIC_DIST +
|
||||
(gic_bank_offset * smp_processor_id());
|
||||
}
|
||||
|
||||
void __init exynos4_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
|
||||
gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
|
||||
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
|
||||
|
||||
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
|
||||
gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
|
||||
gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
|
||||
gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
|
||||
|
||||
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
|
||||
|
||||
|
@ -223,7 +258,11 @@ static int __init exynos4_l2x0_cache_init(void)
|
|||
{
|
||||
/* TAG, Data Latency Control: 2cycle */
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
||||
else if (soc_is_exynos4212() || soc_is_exynos4412())
|
||||
__raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
|
||||
|
||||
/* L2X0 Prefetch Control */
|
||||
__raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
|
||||
|
|
|
@ -21,151 +21,229 @@
|
|||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl330.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/irqs.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/s3c-pl330-pdata.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct resource exynos4_pdma0_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_PDMA0,
|
||||
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_PDMA0,
|
||||
.end = IRQ_PDMA0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
struct dma_pl330_peri pdma0_peri[28] = {
|
||||
{
|
||||
.peri_id = (u8)DMACH_PCM0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_PCM0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_PCM2_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_PCM2_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_MSM_REQ0,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_MSM_REQ2,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SPI0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SPI0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SPI2_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SPI2_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S0S_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART2_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART2_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART4_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART4_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS2_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS2_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS4_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS4_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_AC97_MICIN,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_AC97_PCMIN,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_AC97_PCMOUT,
|
||||
.rqtype = MEMTODEV,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
|
||||
.peri = {
|
||||
[0] = DMACH_PCM0_RX,
|
||||
[1] = DMACH_PCM0_TX,
|
||||
[2] = DMACH_PCM2_RX,
|
||||
[3] = DMACH_PCM2_TX,
|
||||
[4] = DMACH_MSM_REQ0,
|
||||
[5] = DMACH_MSM_REQ2,
|
||||
[6] = DMACH_SPI0_RX,
|
||||
[7] = DMACH_SPI0_TX,
|
||||
[8] = DMACH_SPI2_RX,
|
||||
[9] = DMACH_SPI2_TX,
|
||||
[10] = DMACH_I2S0S_TX,
|
||||
[11] = DMACH_I2S0_RX,
|
||||
[12] = DMACH_I2S0_TX,
|
||||
[13] = DMACH_I2S2_RX,
|
||||
[14] = DMACH_I2S2_TX,
|
||||
[15] = DMACH_UART0_RX,
|
||||
[16] = DMACH_UART0_TX,
|
||||
[17] = DMACH_UART2_RX,
|
||||
[18] = DMACH_UART2_TX,
|
||||
[19] = DMACH_UART4_RX,
|
||||
[20] = DMACH_UART4_TX,
|
||||
[21] = DMACH_SLIMBUS0_RX,
|
||||
[22] = DMACH_SLIMBUS0_TX,
|
||||
[23] = DMACH_SLIMBUS2_RX,
|
||||
[24] = DMACH_SLIMBUS2_TX,
|
||||
[25] = DMACH_SLIMBUS4_RX,
|
||||
[26] = DMACH_SLIMBUS4_TX,
|
||||
[27] = DMACH_AC97_MICIN,
|
||||
[28] = DMACH_AC97_PCMIN,
|
||||
[29] = DMACH_AC97_PCMOUT,
|
||||
[30] = DMACH_MAX,
|
||||
[31] = DMACH_MAX,
|
||||
},
|
||||
struct dma_pl330_platdata exynos4_pdma0_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma0_peri),
|
||||
.peri = pdma0_peri,
|
||||
};
|
||||
|
||||
static struct platform_device exynos4_device_pdma0 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
|
||||
.resource = exynos4_pdma0_resource,
|
||||
.dev = {
|
||||
struct amba_device exynos4_device_pdma0 = {
|
||||
.dev = {
|
||||
.init_name = "dma-pl330.0",
|
||||
.dma_mask = &dma_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &exynos4_pdma0_pdata,
|
||||
},
|
||||
.res = {
|
||||
.start = EXYNOS4_PA_PDMA0,
|
||||
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = {IRQ_PDMA0, NO_IRQ},
|
||||
.periphid = 0x00041330,
|
||||
};
|
||||
|
||||
static struct resource exynos4_pdma1_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_PDMA1,
|
||||
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_PDMA1,
|
||||
.end = IRQ_PDMA1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
struct dma_pl330_peri pdma1_peri[25] = {
|
||||
{
|
||||
.peri_id = (u8)DMACH_PCM0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_PCM0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_PCM1_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_PCM1_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_MSM_REQ1,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_MSM_REQ3,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SPI1_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SPI1_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S0S_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S1_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_I2S1_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART0_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART0_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART1_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART1_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART3_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_UART3_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS1_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS1_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS3_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS3_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS5_RX,
|
||||
.rqtype = DEVTOMEM,
|
||||
}, {
|
||||
.peri_id = (u8)DMACH_SLIMBUS5_TX,
|
||||
.rqtype = MEMTODEV,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
|
||||
.peri = {
|
||||
[0] = DMACH_PCM0_RX,
|
||||
[1] = DMACH_PCM0_TX,
|
||||
[2] = DMACH_PCM1_RX,
|
||||
[3] = DMACH_PCM1_TX,
|
||||
[4] = DMACH_MSM_REQ1,
|
||||
[5] = DMACH_MSM_REQ3,
|
||||
[6] = DMACH_SPI1_RX,
|
||||
[7] = DMACH_SPI1_TX,
|
||||
[8] = DMACH_I2S0S_TX,
|
||||
[9] = DMACH_I2S0_RX,
|
||||
[10] = DMACH_I2S0_TX,
|
||||
[11] = DMACH_I2S1_RX,
|
||||
[12] = DMACH_I2S1_TX,
|
||||
[13] = DMACH_UART0_RX,
|
||||
[14] = DMACH_UART0_TX,
|
||||
[15] = DMACH_UART1_RX,
|
||||
[16] = DMACH_UART1_TX,
|
||||
[17] = DMACH_UART3_RX,
|
||||
[18] = DMACH_UART3_TX,
|
||||
[19] = DMACH_SLIMBUS1_RX,
|
||||
[20] = DMACH_SLIMBUS1_TX,
|
||||
[21] = DMACH_SLIMBUS3_RX,
|
||||
[22] = DMACH_SLIMBUS3_TX,
|
||||
[23] = DMACH_SLIMBUS5_RX,
|
||||
[24] = DMACH_SLIMBUS5_TX,
|
||||
[25] = DMACH_SLIMBUS0AUX_RX,
|
||||
[26] = DMACH_SLIMBUS0AUX_TX,
|
||||
[27] = DMACH_SPDIF,
|
||||
[28] = DMACH_MAX,
|
||||
[29] = DMACH_MAX,
|
||||
[30] = DMACH_MAX,
|
||||
[31] = DMACH_MAX,
|
||||
},
|
||||
struct dma_pl330_platdata exynos4_pdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(pdma1_peri),
|
||||
.peri = pdma1_peri,
|
||||
};
|
||||
|
||||
static struct platform_device exynos4_device_pdma1 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
|
||||
.resource = exynos4_pdma1_resource,
|
||||
.dev = {
|
||||
struct amba_device exynos4_device_pdma1 = {
|
||||
.dev = {
|
||||
.init_name = "dma-pl330.1",
|
||||
.dma_mask = &dma_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &exynos4_pdma1_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *exynos4_dmacs[] __initdata = {
|
||||
&exynos4_device_pdma0,
|
||||
&exynos4_device_pdma1,
|
||||
.res = {
|
||||
.start = EXYNOS4_PA_PDMA1,
|
||||
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
.irq = {IRQ_PDMA1, NO_IRQ},
|
||||
.periphid = 0x00041330,
|
||||
};
|
||||
|
||||
static int __init exynos4_dma_init(void)
|
||||
{
|
||||
platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
|
||||
amba_device_register(&exynos4_device_pdma0, &iomem_resource);
|
||||
amba_device_register(&exynos4_device_pdma1, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef __MACH_CLKDEV_H__
|
||||
#define __MACH_CLKDEV_H__
|
||||
|
||||
#define __clk_get(clk) ({ 1; })
|
||||
#define __clk_put(clk) do {} while (0)
|
||||
|
||||
#endif
|
|
@ -20,7 +20,7 @@
|
|||
#ifndef __MACH_DMA_H
|
||||
#define __MACH_DMA_H
|
||||
|
||||
/* This platform uses the common S3C DMA API driver for PL330 */
|
||||
#include <plat/s3c-dma-pl330.h>
|
||||
/* This platform uses the common DMA API driver for PL330 */
|
||||
#include <plat/dma-pl330.h>
|
||||
|
||||
#endif /* __MACH_DMA_H */
|
||||
|
|
|
@ -17,12 +17,25 @@
|
|||
.endm
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
ldr \base, =gic_cpu_base_addr
|
||||
mov \tmp, #0
|
||||
|
||||
mrc p15, 0, \base, c0, c0, 5
|
||||
and \base, \base, #3
|
||||
cmp \base, #0
|
||||
beq 1f
|
||||
|
||||
ldr \tmp, =gic_bank_offset
|
||||
ldr \tmp, [\tmp]
|
||||
cmp \base, #1
|
||||
beq 1f
|
||||
|
||||
cmp \base, #2
|
||||
addeq \tmp, \tmp, \tmp
|
||||
addne \tmp, \tmp, \tmp, LSL #1
|
||||
|
||||
1: ldr \base, =gic_cpu_base_addr
|
||||
ldr \base, [\base]
|
||||
mrc p15, 0, \tmp, c0, c0, 5
|
||||
and \tmp, \tmp, #3
|
||||
cmp \tmp, #1
|
||||
addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
|
||||
add \base, \base, \tmp
|
||||
.endm
|
||||
|
||||
.macro arch_ret_to_user, tmp1, tmp2
|
||||
|
@ -80,4 +93,10 @@
|
|||
/* As above, this assumes that irqstat and base are preserved.. */
|
||||
|
||||
.macro test_for_ltirq, irqnr, irqstat, base, tmp
|
||||
bic \irqnr, \irqstat, #0x1c00
|
||||
mov \tmp, #0
|
||||
cmp \irqnr, #28
|
||||
moveq \tmp, #1
|
||||
streq \irqstat, [\base, #GIC_CPU_EOI]
|
||||
cmp \tmp, #0
|
||||
.endm
|
||||
|
|
43
arch/arm/mach-exynos4/include/mach/exynos4-clock.h
Normal file
43
arch/arm/mach-exynos4/include/mach/exynos4-clock.h
Normal file
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Header file for exynos4 clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H __FILE__
|
||||
|
||||
#include <linux/clk.h>
|
||||
|
||||
extern struct clk clk_sclk_hdmi27m;
|
||||
extern struct clk clk_sclk_usbphy0;
|
||||
extern struct clk clk_sclk_usbphy1;
|
||||
extern struct clk clk_sclk_hdmiphy;
|
||||
|
||||
extern struct clksrc_clk clk_sclk_apll;
|
||||
extern struct clksrc_clk clk_mout_mpll;
|
||||
extern struct clksrc_clk clk_aclk_133;
|
||||
extern struct clksrc_clk clk_mout_epll;
|
||||
extern struct clksrc_clk clk_sclk_vpll;
|
||||
|
||||
extern struct clk *clkset_corebus_list[];
|
||||
extern struct clksrc_sources clkset_mout_corebus;
|
||||
|
||||
extern struct clk *clkset_aclk_top_list[];
|
||||
extern struct clksrc_sources clkset_aclk;
|
||||
|
||||
extern struct clk *clkset_group_list[];
|
||||
extern struct clksrc_sources clkset_group;
|
||||
|
||||
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
|
||||
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
16
arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
Normal file
16
arch/arm/mach-exynos4/include/mach/i2c-hdmiphy.h
Normal file
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* S5P series i2c hdmiphy helper definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef PLAT_S5P_I2C_HDMIPHY_H_
|
||||
#define PLAT_S5P_I2C_HDMIPHY_H_
|
||||
|
||||
#define S5P_I2C_HDMIPHY_BUS_NUM (8)
|
||||
|
||||
#endif
|
|
@ -19,6 +19,8 @@
|
|||
|
||||
#define IRQ_PPI(x) S5P_IRQ(x+16)
|
||||
|
||||
#define IRQ_MCT_LOCALTIMER IRQ_PPI(12)
|
||||
|
||||
/* SPI: Shared Peripheral Interrupt */
|
||||
|
||||
#define IRQ_SPI(x) S5P_IRQ(x+32)
|
||||
|
@ -93,7 +95,11 @@
|
|||
#define IRQ_2D IRQ_SPI(89)
|
||||
#define IRQ_PCIE IRQ_SPI(90)
|
||||
|
||||
#define IRQ_MIXER IRQ_SPI(91)
|
||||
#define IRQ_HDMI IRQ_SPI(92)
|
||||
#define IRQ_IIC_HDMIPHY IRQ_SPI(93)
|
||||
#define IRQ_MFC IRQ_SPI(94)
|
||||
#define IRQ_SDO IRQ_SPI(95)
|
||||
|
||||
#define IRQ_AUDIO_SS IRQ_SPI(96)
|
||||
#define IRQ_I2S0 IRQ_SPI(97)
|
||||
|
|
|
@ -23,7 +23,8 @@
|
|||
|
||||
#include <plat/map-s5p.h>
|
||||
|
||||
#define EXYNOS4_PA_SYSRAM 0x02020000
|
||||
#define EXYNOS4_PA_SYSRAM0 0x02025000
|
||||
#define EXYNOS4_PA_SYSRAM1 0x02020000
|
||||
|
||||
#define EXYNOS4_PA_FIMC0 0x11800000
|
||||
#define EXYNOS4_PA_FIMC1 0x11810000
|
||||
|
@ -61,7 +62,6 @@
|
|||
|
||||
#define EXYNOS4_PA_GIC_CPU 0x10480000
|
||||
#define EXYNOS4_PA_GIC_DIST 0x10490000
|
||||
#define EXYNOS4_GIC_BANK_OFFSET 0x8000
|
||||
|
||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||
#define EXYNOS4_PA_TWD 0x10500600
|
||||
|
@ -112,6 +112,12 @@
|
|||
|
||||
#define EXYNOS4_PA_UART 0x13800000
|
||||
|
||||
#define EXYNOS4_PA_VP 0x12C00000
|
||||
#define EXYNOS4_PA_MIXER 0x12C10000
|
||||
#define EXYNOS4_PA_SDO 0x12C20000
|
||||
#define EXYNOS4_PA_HDMI 0x12D00000
|
||||
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
|
||||
|
||||
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_ADC 0x13910000
|
||||
|
@ -161,6 +167,12 @@
|
|||
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
|
||||
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
|
||||
|
||||
#define S5P_PA_SDO EXYNOS4_PA_SDO
|
||||
#define S5P_PA_VP EXYNOS4_PA_VP
|
||||
#define S5P_PA_MIXER EXYNOS4_PA_MIXER
|
||||
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
|
||||
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
|
||||
|
||||
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
|
||||
|
||||
/* UART */
|
||||
|
|
|
@ -14,6 +14,10 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_PM_CORE_H
|
||||
#define __ASM_ARCH_PM_CORE_H __FILE__
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
static inline void s3c_pm_debug_init_uart(void)
|
||||
|
@ -53,7 +57,9 @@ static inline void s3c_pm_restored_gpios(void)
|
|||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_saved_gpios(void)
|
||||
static inline void samsung_pm_saved_gpios(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_PM_CORE_H */
|
||||
|
|
|
@ -13,6 +13,8 @@
|
|||
#ifndef __ASM_ARCH_PMU_H
|
||||
#define __ASM_ARCH_PMU_H __FILE__
|
||||
|
||||
#define PMU_TABLE_END NULL
|
||||
|
||||
enum sys_powerdown {
|
||||
SYS_AFTR,
|
||||
SYS_LPA,
|
||||
|
@ -20,6 +22,11 @@ enum sys_powerdown {
|
|||
NUM_SYS_POWERDOWN,
|
||||
};
|
||||
|
||||
struct exynos4_pmu_conf {
|
||||
void __iomem *reg;
|
||||
unsigned int val[NUM_SYS_POWERDOWN];
|
||||
};
|
||||
|
||||
extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
|
||||
|
||||
#endif /* __ASM_ARCH_PMU_H */
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#ifndef __ASM_ARCH_REGS_CLOCK_H
|
||||
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
|
||||
|
@ -41,12 +42,20 @@
|
|||
#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
|
||||
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
|
||||
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
|
||||
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
|
||||
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
|
||||
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
|
||||
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
|
||||
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
|
||||
|
||||
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
|
||||
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
|
||||
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
|
||||
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
|
||||
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
|
||||
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
|
||||
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
|
||||
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
|
||||
|
||||
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
|
||||
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
|
||||
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
|
||||
|
@ -54,7 +63,6 @@
|
|||
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
|
||||
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
|
||||
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
|
||||
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
|
||||
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
|
||||
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
|
||||
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
|
||||
|
@ -68,16 +76,6 @@
|
|||
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
|
||||
#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
|
||||
|
||||
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
|
||||
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
|
||||
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
|
||||
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
|
||||
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
|
||||
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
|
||||
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
|
||||
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
|
||||
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
|
||||
|
||||
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
|
||||
|
||||
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
|
||||
|
@ -85,13 +83,20 @@
|
|||
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
|
||||
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
|
||||
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
|
||||
#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
|
||||
#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x0C930) : \
|
||||
S5P_CLKREG(0x04930))
|
||||
#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930)
|
||||
#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930)
|
||||
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
|
||||
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
|
||||
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
|
||||
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
|
||||
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
|
||||
#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
|
||||
#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x0C960) : \
|
||||
S5P_CLKREG(0x08960))
|
||||
#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960)
|
||||
#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960)
|
||||
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
|
||||
|
||||
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
|
||||
|
@ -102,11 +107,17 @@
|
|||
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
|
||||
|
||||
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
|
||||
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
|
||||
#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x14004) : \
|
||||
S5P_CLKREG(0x10008))
|
||||
#define S5P_APLL_CON0 S5P_CLKREG(0x14100)
|
||||
#define S5P_APLL_CON1 S5P_CLKREG(0x14104)
|
||||
#define S5P_MPLL_CON0 S5P_CLKREG(0x14108)
|
||||
#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C)
|
||||
#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x14108) : \
|
||||
S5P_CLKREG(0x10108))
|
||||
#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \
|
||||
S5P_CLKREG(0x1410C) : \
|
||||
S5P_CLKREG(0x1010C))
|
||||
|
||||
#define S5P_CLKSRC_CPU S5P_CLKREG(0x14200)
|
||||
#define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400)
|
||||
|
@ -183,6 +194,13 @@
|
|||
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
|
||||
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
|
||||
|
||||
/* Only for EXYNOS4210 */
|
||||
|
||||
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
|
||||
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
|
||||
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
|
||||
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
|
||||
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
|
|
@ -31,8 +31,9 @@
|
|||
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
|
||||
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
|
||||
|
||||
#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
|
||||
#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
|
||||
#define EXYNOS4_MCT_L_MASK (0xffffff00)
|
||||
|
||||
#define MCT_L_TCNTB_OFFSET (0x00)
|
||||
#define MCT_L_ICNTB_OFFSET (0x08)
|
||||
|
|
|
@ -25,9 +25,10 @@
|
|||
|
||||
#define S5P_USE_STANDBY_WFI0 (1 << 16)
|
||||
#define S5P_USE_STANDBY_WFI1 (1 << 17)
|
||||
#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18)
|
||||
#define S5P_USE_STANDBY_WFE0 (1 << 24)
|
||||
#define S5P_USE_STANDBY_WFE1 (1 << 25)
|
||||
#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
|
||||
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
|
||||
|
||||
#define S5P_SWRESET S5P_PMUREG(0x0400)
|
||||
|
||||
|
@ -35,15 +36,17 @@
|
|||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
|
||||
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
|
||||
|
||||
#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
|
||||
#define S5P_USBHOST_PHY_ENABLE (1 << 0)
|
||||
#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700)
|
||||
#define S5P_HDMI_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C)
|
||||
#define S5P_DAC_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
|
||||
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
|
||||
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
|
||||
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
|
||||
#define S5P_INFORM0 S5P_PMUREG(0x0800)
|
||||
#define S5P_INFORM1 S5P_PMUREG(0x0804)
|
||||
#define S5P_INFORM2 S5P_PMUREG(0x0808)
|
||||
|
@ -76,7 +79,6 @@
|
|||
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
|
||||
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
|
||||
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
|
||||
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
|
||||
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
|
||||
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
|
||||
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
|
||||
|
@ -84,7 +86,6 @@
|
|||
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
|
||||
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
|
||||
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
|
||||
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
|
||||
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
|
||||
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
|
||||
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
|
||||
|
@ -92,14 +93,11 @@
|
|||
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
|
||||
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
|
||||
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
|
||||
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
|
||||
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
|
||||
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
|
||||
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
|
||||
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
|
||||
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
|
||||
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
|
||||
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
|
||||
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
|
||||
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
|
||||
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
|
||||
|
@ -120,7 +118,6 @@
|
|||
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
|
||||
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
|
||||
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
|
||||
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
|
||||
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
|
||||
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
|
||||
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
|
||||
|
@ -156,7 +153,6 @@
|
|||
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
|
||||
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
|
||||
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
|
||||
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
|
||||
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
|
||||
|
@ -165,4 +161,60 @@
|
|||
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
|
||||
/* Only for EXYNOS4210 */
|
||||
#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
|
||||
#define S5P_USBHOST_PHY_ENABLE (1 << 0)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
|
||||
|
||||
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
|
||||
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
|
||||
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
|
||||
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
|
||||
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
|
||||
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
|
||||
|
||||
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
|
||||
|
||||
/* Only for EXYNOS4212 */
|
||||
#define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050)
|
||||
#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054)
|
||||
#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058)
|
||||
#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110)
|
||||
#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114)
|
||||
#define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C)
|
||||
#define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130)
|
||||
#define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154)
|
||||
#define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174)
|
||||
#define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190)
|
||||
#define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194)
|
||||
#define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198)
|
||||
#define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4)
|
||||
#define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0)
|
||||
#define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4)
|
||||
#define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4)
|
||||
#define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC)
|
||||
#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C)
|
||||
#define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250)
|
||||
#define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320)
|
||||
#define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344)
|
||||
#define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348)
|
||||
#define S5P_ISP_LOWPWR S5P_PMUREG(0x1394)
|
||||
#define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0)
|
||||
#define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4)
|
||||
#define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8)
|
||||
#define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC)
|
||||
#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0)
|
||||
|
||||
#define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608)
|
||||
#define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628)
|
||||
#define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08)
|
||||
#define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28)
|
||||
#define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48)
|
||||
#define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68)
|
||||
#define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88)
|
||||
#define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8)
|
||||
#define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8)
|
||||
#define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_PMU_H */
|
||||
|
|
|
@ -32,10 +32,12 @@
|
|||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/adc.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/ehci.h>
|
||||
#include <plat/clock.h>
|
||||
|
@ -199,6 +201,33 @@ static struct platform_device nuri_gpio_keys = {
|
|||
},
|
||||
};
|
||||
|
||||
/* Frame Buffer */
|
||||
static struct s3c_fb_pd_win nuri_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 64,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 64,
|
||||
.lower_margin = 1,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1280,
|
||||
.yres = 800,
|
||||
.refresh = 60,
|
||||
},
|
||||
.max_bpp = 24,
|
||||
.default_bpp = 16,
|
||||
.virtual_x = 1280,
|
||||
.virtual_y = 800,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
|
||||
.win[0] = &nuri_fb_win0,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
|
||||
VIDCON0_CLKSEL_LCD,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
|
||||
{
|
||||
int gpio = EXYNOS4_GPE1(5);
|
||||
|
@ -1092,6 +1121,7 @@ static struct platform_device *nuri_devices[] __initdata = {
|
|||
/* Samsung Platform Devices */
|
||||
&s3c_device_i2c5, /* PMIC should initialize first */
|
||||
&emmc_fixed_voltage,
|
||||
&s5p_device_fimd0,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
|
@ -1106,6 +1136,7 @@ static struct platform_device *nuri_devices[] __initdata = {
|
|||
&s5p_device_mfc_l,
|
||||
&s5p_device_mfc_r,
|
||||
&exynos4_device_pd[PD_MFC],
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
|
||||
/* NURI Devices */
|
||||
&nuri_gpio_keys,
|
||||
|
@ -1142,12 +1173,15 @@ static void __init nuri_machine_init(void)
|
|||
i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
|
||||
i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
|
||||
|
||||
s5p_fimd0_set_platdata(&nuri_fb_pdata);
|
||||
|
||||
nuri_ehci_init();
|
||||
clk_xusbxti.rate = 24000000;
|
||||
|
||||
/* Last */
|
||||
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
|
||||
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
|
||||
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
|
||||
}
|
||||
|
||||
MACHINE_START(NURI, "NURI")
|
||||
|
|
679
arch/arm/mach-exynos4/mach-origen.c
Normal file
679
arch/arm/mach-exynos4/mach-origen.c
Normal file
|
@ -0,0 +1,679 @@
|
|||
/* linux/arch/arm/mach-exynos4/mach-origen.c
|
||||
*
|
||||
* Copyright (c) 2011 Insignal Co., Ltd.
|
||||
* http://www.insignal.co.kr/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/mfd/max8997.h>
|
||||
#include <linux/lcd.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/ehci.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/backlight.h>
|
||||
#include <plat/pd.h>
|
||||
#include <plat/fb.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG4 | \
|
||||
S5PV210_UFCON_RXTRIG4)
|
||||
|
||||
static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = ORIGEN_UCON_DEFAULT,
|
||||
.ulcon = ORIGEN_ULCON_DEFAULT,
|
||||
.ufcon = ORIGEN_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = ORIGEN_UCON_DEFAULT,
|
||||
.ulcon = ORIGEN_ULCON_DEFAULT,
|
||||
.ufcon = ORIGEN_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = ORIGEN_UCON_DEFAULT,
|
||||
.ulcon = ORIGEN_ULCON_DEFAULT,
|
||||
.ufcon = ORIGEN_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.flags = 0,
|
||||
.ucon = ORIGEN_UCON_DEFAULT,
|
||||
.ulcon = ORIGEN_ULCON_DEFAULT,
|
||||
.ufcon = ORIGEN_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
|
||||
REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
|
||||
REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
|
||||
REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
|
||||
REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata buck1_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata buck2_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata buck3_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
|
||||
};
|
||||
static struct regulator_consumer_supply __initdata buck7_consumer[] = {
|
||||
REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo1_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_ABB_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_ALIVE_1.1V",
|
||||
.min_uV = 1100000,
|
||||
.max_uV = 1100000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo3_data = {
|
||||
.constraints = {
|
||||
.name = "VMIPI_1.1V",
|
||||
.min_uV = 1100000,
|
||||
.max_uV = 1100000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo3_consumer),
|
||||
.consumer_supplies = ldo3_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo4_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_RTC_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo6_data = {
|
||||
.constraints = {
|
||||
.name = "VMIPI_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo6_consumer),
|
||||
.consumer_supplies = ldo6_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo7_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_AUD_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo7_consumer),
|
||||
.consumer_supplies = ldo7_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo8_data = {
|
||||
.constraints = {
|
||||
.name = "VADC_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo8_consumer),
|
||||
.consumer_supplies = ldo8_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo9_data = {
|
||||
.constraints = {
|
||||
.name = "DVDD_SWB_2.8V",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo9_consumer),
|
||||
.consumer_supplies = ldo9_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo10_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_PLL_1.1V",
|
||||
.min_uV = 1100000,
|
||||
.max_uV = 1100000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo11_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_AUD_3V",
|
||||
.min_uV = 3000000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo11_consumer),
|
||||
.consumer_supplies = ldo11_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo14_data = {
|
||||
.constraints = {
|
||||
.name = "AVDD18_SWB_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo14_consumer),
|
||||
.consumer_supplies = ldo14_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo17_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_SWB_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(ldo17_consumer),
|
||||
.consumer_supplies = ldo17_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_ldo21_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_MIF_1.2V",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_buck1_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_ARM_1.2V",
|
||||
.min_uV = 950000,
|
||||
.max_uV = 1350000,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
|
||||
.consumer_supplies = buck1_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_buck2_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_INT_1.1V",
|
||||
.min_uV = 900000,
|
||||
.max_uV = 1100000,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
|
||||
.consumer_supplies = buck2_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_buck3_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_G3D_1.1V",
|
||||
.min_uV = 900000,
|
||||
.max_uV = 1100000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck3_consumer),
|
||||
.consumer_supplies = buck3_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_buck5_data = {
|
||||
.constraints = {
|
||||
.name = "VDDQ_M1M2_1.2V",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data __initdata max8997_buck7_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_LCD_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.boot_on = 1,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck7_consumer),
|
||||
.consumer_supplies = buck7_consumer,
|
||||
};
|
||||
|
||||
static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
|
||||
{ MAX8997_LDO1, &max8997_ldo1_data },
|
||||
{ MAX8997_LDO2, &max8997_ldo2_data },
|
||||
{ MAX8997_LDO3, &max8997_ldo3_data },
|
||||
{ MAX8997_LDO4, &max8997_ldo4_data },
|
||||
{ MAX8997_LDO6, &max8997_ldo6_data },
|
||||
{ MAX8997_LDO7, &max8997_ldo7_data },
|
||||
{ MAX8997_LDO8, &max8997_ldo8_data },
|
||||
{ MAX8997_LDO9, &max8997_ldo9_data },
|
||||
{ MAX8997_LDO10, &max8997_ldo10_data },
|
||||
{ MAX8997_LDO11, &max8997_ldo11_data },
|
||||
{ MAX8997_LDO14, &max8997_ldo14_data },
|
||||
{ MAX8997_LDO17, &max8997_ldo17_data },
|
||||
{ MAX8997_LDO21, &max8997_ldo21_data },
|
||||
{ MAX8997_BUCK1, &max8997_buck1_data },
|
||||
{ MAX8997_BUCK2, &max8997_buck2_data },
|
||||
{ MAX8997_BUCK3, &max8997_buck3_data },
|
||||
{ MAX8997_BUCK5, &max8997_buck5_data },
|
||||
{ MAX8997_BUCK7, &max8997_buck7_data },
|
||||
};
|
||||
|
||||
struct max8997_platform_data __initdata origen_max8997_pdata = {
|
||||
.num_regulators = ARRAY_SIZE(origen_max8997_regulators),
|
||||
.regulators = origen_max8997_regulators,
|
||||
|
||||
.wakeup = true,
|
||||
.buck1_gpiodvs = false,
|
||||
.buck2_gpiodvs = false,
|
||||
.buck5_gpiodvs = false,
|
||||
.irq_base = IRQ_GPIO_END + 1,
|
||||
|
||||
.ignore_gpiodvs_side_effect = true,
|
||||
.buck125_default_idx = 0x0,
|
||||
|
||||
.buck125_gpios[0] = EXYNOS4_GPX0(0),
|
||||
.buck125_gpios[1] = EXYNOS4_GPX0(1),
|
||||
.buck125_gpios[2] = EXYNOS4_GPX0(2),
|
||||
|
||||
.buck1_voltage[0] = 1350000,
|
||||
.buck1_voltage[1] = 1300000,
|
||||
.buck1_voltage[2] = 1250000,
|
||||
.buck1_voltage[3] = 1200000,
|
||||
.buck1_voltage[4] = 1150000,
|
||||
.buck1_voltage[5] = 1100000,
|
||||
.buck1_voltage[6] = 1000000,
|
||||
.buck1_voltage[7] = 950000,
|
||||
|
||||
.buck2_voltage[0] = 1100000,
|
||||
.buck2_voltage[1] = 1100000,
|
||||
.buck2_voltage[2] = 1100000,
|
||||
.buck2_voltage[3] = 1100000,
|
||||
.buck2_voltage[4] = 1000000,
|
||||
.buck2_voltage[5] = 1000000,
|
||||
.buck2_voltage[6] = 1000000,
|
||||
.buck2_voltage[7] = 1000000,
|
||||
|
||||
.buck5_voltage[0] = 1200000,
|
||||
.buck5_voltage[1] = 1200000,
|
||||
.buck5_voltage[2] = 1200000,
|
||||
.buck5_voltage[3] = 1200000,
|
||||
.buck5_voltage[4] = 1200000,
|
||||
.buck5_voltage[5] = 1200000,
|
||||
.buck5_voltage[6] = 1200000,
|
||||
.buck5_voltage[7] = 1200000,
|
||||
};
|
||||
|
||||
/* I2C0 */
|
||||
static struct i2c_board_info i2c0_devs[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("max8997", (0xCC >> 1)),
|
||||
.platform_data = &origen_max8997_pdata,
|
||||
.irq = IRQ_EINT(4),
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_INTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_INTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
/* USB EHCI */
|
||||
static struct s5p_ehci_platdata origen_ehci_pdata;
|
||||
|
||||
static void __init origen_ehci_init(void)
|
||||
{
|
||||
struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
|
||||
|
||||
s5p_ehci_set_platdata(pdata);
|
||||
}
|
||||
|
||||
static struct gpio_keys_button origen_gpio_keys_table[] = {
|
||||
{
|
||||
.code = KEY_MENU,
|
||||
.gpio = EXYNOS4_GPX1(5),
|
||||
.desc = "gpio-keys: KEY_MENU",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_HOME,
|
||||
.gpio = EXYNOS4_GPX1(6),
|
||||
.desc = "gpio-keys: KEY_HOME",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_BACK,
|
||||
.gpio = EXYNOS4_GPX1(7),
|
||||
.desc = "gpio-keys: KEY_BACK",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_UP,
|
||||
.gpio = EXYNOS4_GPX2(0),
|
||||
.desc = "gpio-keys: KEY_UP",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_DOWN,
|
||||
.gpio = EXYNOS4_GPX2(1),
|
||||
.desc = "gpio-keys: KEY_DOWN",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
.debounce_interval = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data origen_gpio_keys_data = {
|
||||
.buttons = origen_gpio_keys_table,
|
||||
.nbuttons = ARRAY_SIZE(origen_gpio_keys_table),
|
||||
};
|
||||
|
||||
static struct platform_device origen_device_gpiokeys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &origen_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
|
||||
static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (power)
|
||||
ret = gpio_request_one(EXYNOS4_GPE3(4),
|
||||
GPIOF_OUT_INIT_HIGH, "GPE3_4");
|
||||
else
|
||||
ret = gpio_request_one(EXYNOS4_GPE3(4),
|
||||
GPIOF_OUT_INIT_LOW, "GPE3_4");
|
||||
|
||||
gpio_free(EXYNOS4_GPE3(4));
|
||||
|
||||
if (ret)
|
||||
pr_err("failed to request gpio for LCD power: %d\n", ret);
|
||||
}
|
||||
|
||||
static struct plat_lcd_data origen_lcd_hv070wsa_data = {
|
||||
.set_power = lcd_hv070wsa_set_power,
|
||||
};
|
||||
|
||||
static struct platform_device origen_lcd_hv070wsa = {
|
||||
.name = "platform-lcd",
|
||||
.dev.parent = &s5p_device_fimd0.dev,
|
||||
.dev.platform_data = &origen_lcd_hv070wsa_data,
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win origen_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 64,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 64,
|
||||
.lower_margin = 16,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.xres = 1024,
|
||||
.yres = 600,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 24,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
|
||||
.win[0] = &origen_fb_win0,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static struct platform_device *origen_devices[] __initdata = {
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_i2c0,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&s5p_device_ehci,
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
&s5p_device_fimc3,
|
||||
&s5p_device_fimd0,
|
||||
&s5p_device_hdmi,
|
||||
&s5p_device_i2c_hdmiphy,
|
||||
&s5p_device_mixer,
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
&exynos4_device_pd[PD_TV],
|
||||
&origen_device_gpiokeys,
|
||||
&origen_lcd_hv070wsa,
|
||||
};
|
||||
|
||||
/* LCD Backlight data */
|
||||
static struct samsung_bl_gpio_info origen_bl_gpio_info = {
|
||||
.no = EXYNOS4_GPD0(0),
|
||||
.func = S3C_GPIO_SFN(2),
|
||||
};
|
||||
|
||||
static struct platform_pwm_backlight_data origen_bl_data = {
|
||||
.pwm_id = 0,
|
||||
.pwm_period_ns = 1000,
|
||||
};
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
{
|
||||
/* Direct HPD to HDMI chip */
|
||||
gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
static void __init origen_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init origen_power_init(void)
|
||||
{
|
||||
gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
|
||||
}
|
||||
|
||||
static void __init origen_machine_init(void)
|
||||
{
|
||||
origen_power_init();
|
||||
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
|
||||
|
||||
/*
|
||||
* Since sdhci instance 2 can contain a bootable media,
|
||||
* sdhci instance 0 is registered after instance 2.
|
||||
*/
|
||||
s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
|
||||
s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
|
||||
|
||||
origen_ehci_init();
|
||||
clk_xusbxti.rate = 24000000;
|
||||
|
||||
s5p_tv_setup();
|
||||
s5p_i2c_hdmiphy_set_platdata(NULL);
|
||||
|
||||
s5p_fimd0_set_platdata(&origen_lcd_pdata);
|
||||
|
||||
platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
|
||||
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
|
||||
|
||||
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
|
||||
samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
|
||||
}
|
||||
|
||||
MACHINE_START(ORIGEN, "ORIGEN")
|
||||
/* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = origen_map_io,
|
||||
.init_machine = origen_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
302
arch/arm/mach-exynos4/mach-smdk4x12.c
Normal file
302
arch/arm/mach-exynos4/mach-smdk4x12.c
Normal file
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/mach-smdk4x12.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/max8997.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/serial_core.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/backlight.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define SMDK4X12_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define SMDK4X12_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define SMDK4X12_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG4 | \
|
||||
S5PV210_UFCON_RXTRIG4)
|
||||
|
||||
static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = SMDK4X12_UCON_DEFAULT,
|
||||
.ulcon = SMDK4X12_ULCON_DEFAULT,
|
||||
.ufcon = SMDK4X12_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = SMDK4X12_UCON_DEFAULT,
|
||||
.ulcon = SMDK4X12_ULCON_DEFAULT,
|
||||
.ufcon = SMDK4X12_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = SMDK4X12_UCON_DEFAULT,
|
||||
.ulcon = SMDK4X12_ULCON_DEFAULT,
|
||||
.ufcon = SMDK4X12_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.flags = 0,
|
||||
.ucon = SMDK4X12_UCON_DEFAULT,
|
||||
.ulcon = SMDK4X12_ULCON_DEFAULT,
|
||||
.ufcon = SMDK4X12_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_INTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_INTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply max8997_buck1 =
|
||||
REGULATOR_SUPPLY("vdd_arm", NULL);
|
||||
|
||||
static struct regulator_consumer_supply max8997_buck2 =
|
||||
REGULATOR_SUPPLY("vdd_int", NULL);
|
||||
|
||||
static struct regulator_consumer_supply max8997_buck3 =
|
||||
REGULATOR_SUPPLY("vdd_g3d", NULL);
|
||||
|
||||
static struct regulator_init_data max8997_buck1_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_ARM_SMDK4X12",
|
||||
.min_uV = 925000,
|
||||
.max_uV = 1350000,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &max8997_buck1,
|
||||
};
|
||||
|
||||
static struct regulator_init_data max8997_buck2_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_INT_SMDK4X12",
|
||||
.min_uV = 950000,
|
||||
.max_uV = 1150000,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &max8997_buck2,
|
||||
};
|
||||
|
||||
static struct regulator_init_data max8997_buck3_data = {
|
||||
.constraints = {
|
||||
.name = "VDD_G3D_SMDK4X12",
|
||||
.min_uV = 950000,
|
||||
.max_uV = 1150000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &max8997_buck3,
|
||||
};
|
||||
|
||||
static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
|
||||
{ MAX8997_BUCK1, &max8997_buck1_data },
|
||||
{ MAX8997_BUCK2, &max8997_buck2_data },
|
||||
{ MAX8997_BUCK3, &max8997_buck3_data },
|
||||
};
|
||||
|
||||
static struct max8997_platform_data smdk4x12_max8997_pdata = {
|
||||
.num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
|
||||
.regulators = smdk4x12_max8997_regulators,
|
||||
|
||||
.buck1_voltage[0] = 1100000, /* 1.1V */
|
||||
.buck1_voltage[1] = 1100000, /* 1.1V */
|
||||
.buck1_voltage[2] = 1100000, /* 1.1V */
|
||||
.buck1_voltage[3] = 1100000, /* 1.1V */
|
||||
.buck1_voltage[4] = 1100000, /* 1.1V */
|
||||
.buck1_voltage[5] = 1100000, /* 1.1V */
|
||||
.buck1_voltage[6] = 1000000, /* 1.0V */
|
||||
.buck1_voltage[7] = 950000, /* 0.95V */
|
||||
|
||||
.buck2_voltage[0] = 1100000, /* 1.1V */
|
||||
.buck2_voltage[1] = 1000000, /* 1.0V */
|
||||
.buck2_voltage[2] = 950000, /* 0.95V */
|
||||
.buck2_voltage[3] = 900000, /* 0.9V */
|
||||
.buck2_voltage[4] = 1100000, /* 1.1V */
|
||||
.buck2_voltage[5] = 1000000, /* 1.0V */
|
||||
.buck2_voltage[6] = 950000, /* 0.95V */
|
||||
.buck2_voltage[7] = 900000, /* 0.9V */
|
||||
|
||||
.buck5_voltage[0] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[1] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[2] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[3] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[4] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[5] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[6] = 1100000, /* 1.1V */
|
||||
.buck5_voltage[7] = 1100000, /* 1.1V */
|
||||
};
|
||||
|
||||
static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("max8997", 0x66),
|
||||
.platform_data = &smdk4x12_max8997_pdata,
|
||||
}
|
||||
};
|
||||
|
||||
static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
|
||||
{ I2C_BOARD_INFO("wm8994", 0x1a), }
|
||||
};
|
||||
|
||||
static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
|
||||
/* nothing here yet */
|
||||
};
|
||||
|
||||
static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
|
||||
.no = EXYNOS4_GPD0(1),
|
||||
.func = S3C_GPIO_SFN(2),
|
||||
};
|
||||
|
||||
static struct platform_pwm_backlight_data smdk4x12_bl_data = {
|
||||
.pwm_id = 1,
|
||||
.pwm_period_ns = 1000,
|
||||
};
|
||||
|
||||
static uint32_t smdk4x12_keymap[] __initdata = {
|
||||
/* KEY(row, col, keycode) */
|
||||
KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
|
||||
KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
|
||||
.keymap = smdk4x12_keymap,
|
||||
.keymap_size = ARRAY_SIZE(smdk4x12_keymap),
|
||||
};
|
||||
|
||||
static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
|
||||
.keymap_data = &smdk4x12_keymap_data,
|
||||
.rows = 2,
|
||||
.cols = 5,
|
||||
};
|
||||
|
||||
static struct platform_device *smdk4x12_devices[] __initdata = {
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_i2c0,
|
||||
&s3c_device_i2c1,
|
||||
&s3c_device_i2c3,
|
||||
&s3c_device_i2c7,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&samsung_device_keypad,
|
||||
};
|
||||
|
||||
static void __init smdk4x12_map_io(void)
|
||||
{
|
||||
clk_xusbxti.rate = 24000000;
|
||||
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(clk_xusbxti.rate);
|
||||
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init smdk4x12_machine_init(void)
|
||||
{
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
i2c_register_board_info(0, smdk4x12_i2c_devs0,
|
||||
ARRAY_SIZE(smdk4x12_i2c_devs0));
|
||||
|
||||
s3c_i2c1_set_platdata(NULL);
|
||||
i2c_register_board_info(1, smdk4x12_i2c_devs1,
|
||||
ARRAY_SIZE(smdk4x12_i2c_devs1));
|
||||
|
||||
s3c_i2c3_set_platdata(NULL);
|
||||
i2c_register_board_info(3, smdk4x12_i2c_devs3,
|
||||
ARRAY_SIZE(smdk4x12_i2c_devs3));
|
||||
|
||||
s3c_i2c7_set_platdata(NULL);
|
||||
i2c_register_board_info(7, smdk4x12_i2c_devs7,
|
||||
ARRAY_SIZE(smdk4x12_i2c_devs7));
|
||||
|
||||
samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
|
||||
|
||||
samsung_keypad_set_platdata(&smdk4x12_keypad_data);
|
||||
|
||||
s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
|
||||
s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
|
||||
|
||||
platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(SMDK4212, "SMDK4212")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
||||
|
||||
MACHINE_START(SMDK4412, "SMDK4412")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdk4x12_map_io,
|
||||
.init_machine = smdk4x12_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
|
@ -1,309 +0,0 @@
|
|||
/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/lcd.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/pd.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/backlight.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG4 | \
|
||||
S5PV210_UFCON_RXTRIG4)
|
||||
|
||||
static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = SMDKC210_UCON_DEFAULT,
|
||||
.ulcon = SMDKC210_ULCON_DEFAULT,
|
||||
.ufcon = SMDKC210_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = SMDKC210_UCON_DEFAULT,
|
||||
.ulcon = SMDKC210_ULCON_DEFAULT,
|
||||
.ufcon = SMDKC210_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = SMDKC210_UCON_DEFAULT,
|
||||
.ulcon = SMDKC210_ULCON_DEFAULT,
|
||||
.ufcon = SMDKC210_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.flags = 0,
|
||||
.ucon = SMDKC210_UCON_DEFAULT,
|
||||
.ulcon = SMDKC210_ULCON_DEFAULT,
|
||||
.ufcon = SMDKC210_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
|
||||
unsigned int power)
|
||||
{
|
||||
if (power) {
|
||||
#if !defined(CONFIG_BACKLIGHT_PWM)
|
||||
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
|
||||
gpio_free(EXYNOS4_GPD0(1));
|
||||
#endif
|
||||
/* fire nRESET on power up */
|
||||
gpio_request(EXYNOS4_GPX0(6), "GPX0");
|
||||
|
||||
gpio_direction_output(EXYNOS4_GPX0(6), 1);
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(EXYNOS4_GPX0(6), 0);
|
||||
mdelay(10);
|
||||
|
||||
gpio_set_value(EXYNOS4_GPX0(6), 1);
|
||||
mdelay(10);
|
||||
|
||||
gpio_free(EXYNOS4_GPX0(6));
|
||||
} else {
|
||||
#if !defined(CONFIG_BACKLIGHT_PWM)
|
||||
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
|
||||
gpio_free(EXYNOS4_GPD0(1));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
|
||||
.set_power = lcd_lte480wv_set_power,
|
||||
};
|
||||
|
||||
static struct platform_device smdkc210_lcd_lte480wv = {
|
||||
.name = "platform-lcd",
|
||||
.dev.parent = &s5p_device_fimd0.dev,
|
||||
.dev.platform_data = &smdkc210_lcd_lte480wv_data,
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win smdkc210_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 13,
|
||||
.right_margin = 8,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 24,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
|
||||
.win[0] = &smdkc210_fb_win0,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static struct resource smdkc210_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SROM_BANK(1),
|
||||
.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_EINT(5),
|
||||
.end = IRQ_EINT(5),
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc9215_config = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
|
||||
};
|
||||
|
||||
static struct platform_device smdkc210_smsc911x = {
|
||||
.name = "smsc911x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
|
||||
.resource = smdkc210_smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc9215_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_devs1[] __initdata = {
|
||||
{I2C_BOARD_INFO("wm8994", 0x1a),},
|
||||
};
|
||||
|
||||
static struct platform_device *smdkc210_devices[] __initdata = {
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_i2c1,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&exynos4_device_ac97,
|
||||
&exynos4_device_i2s0,
|
||||
&exynos4_device_pd[PD_MFC],
|
||||
&exynos4_device_pd[PD_G3D],
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
&exynos4_device_pd[PD_LCD1],
|
||||
&exynos4_device_pd[PD_CAM],
|
||||
&exynos4_device_pd[PD_TV],
|
||||
&exynos4_device_pd[PD_GPS],
|
||||
&exynos4_device_sysmmu,
|
||||
&samsung_asoc_dma,
|
||||
&s5p_device_fimd0,
|
||||
&smdkc210_lcd_lte480wv,
|
||||
&smdkc210_smsc911x,
|
||||
};
|
||||
|
||||
static void __init smdkc210_smsc911x_init(void)
|
||||
{
|
||||
u32 cs1;
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
cs1 = __raw_readl(S5P_SROM_BW) &
|
||||
~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
|
||||
cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
|
||||
(1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
|
||||
(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
|
||||
S5P_SROM_BW__NCS1__SHIFT;
|
||||
__raw_writel(cs1, S5P_SROM_BW);
|
||||
|
||||
/* set timing for nCS1 suitable for ethernet chip */
|
||||
__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
|
||||
(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
|
||||
(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
|
||||
(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
|
||||
}
|
||||
|
||||
/* LCD Backlight data */
|
||||
static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
|
||||
.no = EXYNOS4_GPD0(1),
|
||||
.func = S3C_GPIO_SFN(2),
|
||||
};
|
||||
|
||||
static struct platform_pwm_backlight_data smdkc210_bl_data = {
|
||||
.pwm_id = 1,
|
||||
.pwm_period_ns = 1000,
|
||||
};
|
||||
|
||||
static void __init smdkc210_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init smdkc210_machine_init(void)
|
||||
{
|
||||
s3c_i2c1_set_platdata(NULL);
|
||||
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
|
||||
|
||||
smdkc210_smsc911x_init();
|
||||
|
||||
s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
|
||||
s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
|
||||
s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
|
||||
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
|
||||
|
||||
samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
|
||||
s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
|
||||
|
||||
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(SMDKC210, "SMDKC210")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkc210_map_io,
|
||||
.init_machine = smdkc210_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
|
@ -9,7 +9,9 @@
|
|||
*/
|
||||
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/lcd.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
@ -21,17 +23,23 @@
|
|||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/pd.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/backlight.h>
|
||||
#include <plat/mfc.h>
|
||||
#include <plat/ehci.h>
|
||||
#include <plat/clock.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
|
@ -112,6 +120,67 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
|
|||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
|
||||
unsigned int power)
|
||||
{
|
||||
if (power) {
|
||||
#if !defined(CONFIG_BACKLIGHT_PWM)
|
||||
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
|
||||
gpio_free(EXYNOS4_GPD0(1));
|
||||
#endif
|
||||
/* fire nRESET on power up */
|
||||
gpio_request(EXYNOS4_GPX0(6), "GPX0");
|
||||
|
||||
gpio_direction_output(EXYNOS4_GPX0(6), 1);
|
||||
mdelay(100);
|
||||
|
||||
gpio_set_value(EXYNOS4_GPX0(6), 0);
|
||||
mdelay(10);
|
||||
|
||||
gpio_set_value(EXYNOS4_GPX0(6), 1);
|
||||
mdelay(10);
|
||||
|
||||
gpio_free(EXYNOS4_GPX0(6));
|
||||
} else {
|
||||
#if !defined(CONFIG_BACKLIGHT_PWM)
|
||||
gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
|
||||
gpio_free(EXYNOS4_GPD0(1));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
|
||||
.set_power = lcd_lte480wv_set_power,
|
||||
};
|
||||
|
||||
static struct platform_device smdkv310_lcd_lte480wv = {
|
||||
.name = "platform-lcd",
|
||||
.dev.parent = &s5p_device_fimd0.dev,
|
||||
.dev.platform_data = &smdkv310_lcd_lte480wv_data,
|
||||
};
|
||||
|
||||
static struct s3c_fb_pd_win smdkv310_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 13,
|
||||
.right_margin = 8,
|
||||
.upper_margin = 7,
|
||||
.lower_margin = 5,
|
||||
.hsync_len = 3,
|
||||
.vsync_len = 1,
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 24,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
|
||||
.win[0] = &smdkv310_fb_win0,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
|
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static struct resource smdkv310_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SROM_BANK(1),
|
||||
|
@ -166,17 +235,36 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
|
|||
{I2C_BOARD_INFO("wm8994", 0x1a),},
|
||||
};
|
||||
|
||||
/* USB EHCI */
|
||||
static struct s5p_ehci_platdata smdkv310_ehci_pdata;
|
||||
|
||||
static void __init smdkv310_ehci_init(void)
|
||||
{
|
||||
struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
|
||||
|
||||
s5p_ehci_set_platdata(pdata);
|
||||
}
|
||||
|
||||
static struct platform_device *smdkv310_devices[] __initdata = {
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc1,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_i2c1,
|
||||
&s5p_device_i2c_hdmiphy,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&s5p_device_ehci,
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
&s5p_device_fimc3,
|
||||
&exynos4_device_ac97,
|
||||
&exynos4_device_i2s0,
|
||||
&samsung_device_keypad,
|
||||
&s5p_device_mfc,
|
||||
&s5p_device_mfc_l,
|
||||
&s5p_device_mfc_r,
|
||||
&exynos4_device_pd[PD_MFC],
|
||||
&exynos4_device_pd[PD_G3D],
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
|
@ -188,8 +276,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
|
|||
&exynos4_device_sysmmu,
|
||||
&samsung_asoc_dma,
|
||||
&samsung_asoc_idma,
|
||||
&s5p_device_fimd0,
|
||||
&smdkv310_lcd_lte480wv,
|
||||
&smdkv310_smsc911x,
|
||||
&exynos4_device_ahci,
|
||||
&s5p_device_hdmi,
|
||||
&s5p_device_mixer,
|
||||
};
|
||||
|
||||
static void __init smdkv310_smsc911x_init(void)
|
||||
|
@ -226,6 +318,18 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
|
|||
.pwm_period_ns = 1000,
|
||||
};
|
||||
|
||||
static void s5p_tv_setup(void)
|
||||
{
|
||||
/* direct HPD to HDMI chip */
|
||||
WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
|
||||
|
||||
/* setup dependencies between TV devices */
|
||||
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
}
|
||||
|
||||
static void __init smdkv310_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
|
@ -233,6 +337,11 @@ static void __init smdkv310_map_io(void)
|
|||
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init smdkv310_reserve(void)
|
||||
{
|
||||
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
|
||||
}
|
||||
|
||||
static void __init smdkv310_machine_init(void)
|
||||
{
|
||||
s3c_i2c1_set_platdata(NULL);
|
||||
|
@ -245,17 +354,35 @@ static void __init smdkv310_machine_init(void)
|
|||
s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
|
||||
s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
|
||||
|
||||
s5p_tv_setup();
|
||||
s5p_i2c_hdmiphy_set_platdata(NULL);
|
||||
|
||||
samsung_keypad_set_platdata(&smdkv310_keypad_data);
|
||||
|
||||
samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
|
||||
s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
|
||||
|
||||
smdkv310_ehci_init();
|
||||
clk_xusbxti.rate = 24000000;
|
||||
|
||||
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
|
||||
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
|
||||
}
|
||||
|
||||
MACHINE_START(SMDKV310, "SMDKV310")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
.reserve = &smdkv310_reserve,
|
||||
MACHINE_END
|
||||
|
||||
MACHINE_START(SMDKC210, "SMDKC210")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/i2c.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/mfd/max8998.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
|
@ -31,12 +32,21 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/mfc.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/pd.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/camport.h>
|
||||
#include <plat/mipi_csis.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <media/v4l2-mediabus.h>
|
||||
#include <media/s5p_fimc.h>
|
||||
#include <media/m5mols.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
|
@ -110,6 +120,9 @@ static struct regulator_consumer_supply lp3974_buck1_consumer =
|
|||
static struct regulator_consumer_supply lp3974_buck2_consumer =
|
||||
REGULATOR_SUPPLY("vddg3d", NULL);
|
||||
|
||||
static struct regulator_consumer_supply lp3974_buck3_consumer =
|
||||
REGULATOR_SUPPLY("vdet", "s5p-sdo");
|
||||
|
||||
static struct regulator_init_data lp3974_buck1_data = {
|
||||
.constraints = {
|
||||
.name = "VINT_1.1V",
|
||||
|
@ -153,6 +166,8 @@ static struct regulator_init_data lp3974_buck3_data = {
|
|||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &lp3974_buck3_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_buck4_data = {
|
||||
|
@ -181,6 +196,12 @@ static struct regulator_init_data lp3974_ldo2_data = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
|
||||
REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
|
||||
REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo3_data = {
|
||||
.constraints = {
|
||||
.name = "VUSB+MIPI_1.1V",
|
||||
|
@ -192,6 +213,12 @@ static struct regulator_init_data lp3974_ldo3_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
|
||||
.consumer_supplies = lp3974_ldo3_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo4_data = {
|
||||
|
@ -205,6 +232,8 @@ static struct regulator_init_data lp3974_ldo4_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
|
||||
.consumer_supplies = lp3974_ldo4_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo5_data = {
|
||||
|
@ -233,6 +262,10 @@ static struct regulator_init_data lp3974_ldo6_data = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo7_data = {
|
||||
.constraints = {
|
||||
.name = "VLCD+VMIPI_1.8V",
|
||||
|
@ -244,6 +277,12 @@ static struct regulator_init_data lp3974_ldo7_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo7_consumer),
|
||||
.consumer_supplies = lp3974_ldo7_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
|
||||
REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo8_data = {
|
||||
|
@ -257,6 +296,8 @@ static struct regulator_init_data lp3974_ldo8_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
|
||||
.consumer_supplies = lp3974_ldo8_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo9_data = {
|
||||
|
@ -286,6 +327,9 @@ static struct regulator_init_data lp3974_ldo10_data = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo11_consumer =
|
||||
REGULATOR_SUPPLY("dig_28", "0-001f");
|
||||
|
||||
static struct regulator_init_data lp3974_ldo11_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_AF_3.3V",
|
||||
|
@ -297,6 +341,8 @@ static struct regulator_init_data lp3974_ldo11_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &lp3974_ldo11_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo12_data = {
|
||||
|
@ -325,6 +371,9 @@ static struct regulator_init_data lp3974_ldo13_data = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo14_consumer =
|
||||
REGULATOR_SUPPLY("dig_18", "0-001f");
|
||||
|
||||
static struct regulator_init_data lp3974_ldo14_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_I_HOST_1.8V",
|
||||
|
@ -336,8 +385,14 @@ static struct regulator_init_data lp3974_ldo14_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &lp3974_ldo14_consumer,
|
||||
};
|
||||
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo15_consumer =
|
||||
REGULATOR_SUPPLY("dig_12", "0-001f");
|
||||
|
||||
static struct regulator_init_data lp3974_ldo15_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_S_DIG+FM33_CORE_1.2V",
|
||||
|
@ -349,6 +404,12 @@ static struct regulator_init_data lp3974_ldo15_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &lp3974_ldo15_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
|
||||
REGULATOR_SUPPLY("a_sensor", "0-001f"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo16_data = {
|
||||
|
@ -362,6 +423,8 @@ static struct regulator_init_data lp3974_ldo16_data = {
|
|||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(lp3974_ldo16_consumer),
|
||||
.consumer_supplies = lp3974_ldo16_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo17_data = {
|
||||
|
@ -472,6 +535,43 @@ static struct max8998_platform_data universal_lp3974_pdata = {
|
|||
.wakeup = true,
|
||||
};
|
||||
|
||||
|
||||
enum fixed_regulator_id {
|
||||
FIXED_REG_ID_MMC0,
|
||||
FIXED_REG_ID_HDMI_5V,
|
||||
FIXED_REG_ID_CAM_S_IF,
|
||||
FIXED_REG_ID_CAM_I_CORE,
|
||||
FIXED_REG_ID_CAM_VT_DIO,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply hdmi_fixed_consumer =
|
||||
REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
|
||||
|
||||
static struct regulator_init_data hdmi_fixed_voltage_init_data = {
|
||||
.constraints = {
|
||||
.name = "HDMI_5V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &hdmi_fixed_consumer,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config hdmi_fixed_voltage_config = {
|
||||
.supply_name = "HDMI_EN1",
|
||||
.microvolts = 5000000,
|
||||
.gpio = EXYNOS4_GPE0(1),
|
||||
.enable_high = true,
|
||||
.init_data = &hdmi_fixed_voltage_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device hdmi_fixed_voltage = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = FIXED_REG_ID_HDMI_5V,
|
||||
.dev = {
|
||||
.platform_data = &hdmi_fixed_voltage_config,
|
||||
},
|
||||
};
|
||||
|
||||
/* GPIO I2C 5 (PMIC) */
|
||||
static struct i2c_board_info i2c5_devs[] __initdata = {
|
||||
{
|
||||
|
@ -573,6 +673,11 @@ static void __init universal_touchkey_init(void)
|
|||
gpio_direction_output(gpio, 1);
|
||||
}
|
||||
|
||||
static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
|
||||
.frequency = 300 * 1000,
|
||||
.sda_delay = 200,
|
||||
};
|
||||
|
||||
/* GPIO KEYS */
|
||||
static struct gpio_keys_button universal_gpio_keys_tables[] = {
|
||||
{
|
||||
|
@ -658,7 +763,7 @@ static struct fixed_voltage_config mmc0_fixed_voltage_config = {
|
|||
|
||||
static struct platform_device mmc0_fixed_voltage = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.id = FIXED_REG_ID_MMC0,
|
||||
.dev = {
|
||||
.platform_data = &mmc0_fixed_voltage_config,
|
||||
},
|
||||
|
@ -692,18 +797,170 @@ static void __init universal_sdhci_init(void)
|
|||
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
|
||||
}
|
||||
|
||||
/* I2C0 */
|
||||
static struct i2c_board_info i2c0_devs[] __initdata = {
|
||||
/* Camera, To be updated */
|
||||
};
|
||||
|
||||
/* I2C1 */
|
||||
static struct i2c_board_info i2c1_devs[] __initdata = {
|
||||
/* Gyro, To be updated */
|
||||
};
|
||||
|
||||
/* Frame Buffer */
|
||||
static struct s3c_fb_pd_win universal_fb_win0 = {
|
||||
.win_mode = {
|
||||
.left_margin = 16,
|
||||
.right_margin = 16,
|
||||
.upper_margin = 2,
|
||||
.lower_margin = 28,
|
||||
.hsync_len = 2,
|
||||
.vsync_len = 1,
|
||||
.xres = 480,
|
||||
.yres = 800,
|
||||
.refresh = 55,
|
||||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
|
||||
.win[0] = &universal_fb_win0,
|
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
|
||||
VIDCON0_CLKSEL_LCD,
|
||||
.vidcon1 = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
|
||||
| VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
|
||||
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply cam_i_core_supply =
|
||||
REGULATOR_SUPPLY("core", "0-001f");
|
||||
|
||||
static struct regulator_init_data cam_i_core_reg_init_data = {
|
||||
.constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &cam_i_core_supply,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
|
||||
.supply_name = "CAM_I_CORE_1.2V",
|
||||
.microvolts = 1200000,
|
||||
.gpio = EXYNOS4_GPE2(2), /* CAM_8M_CORE_EN */
|
||||
.enable_high = 1,
|
||||
.init_data = &cam_i_core_reg_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device cam_i_core_fixed_reg_dev = {
|
||||
.name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
|
||||
.dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply cam_s_if_supply =
|
||||
REGULATOR_SUPPLY("d_sensor", "0-001f");
|
||||
|
||||
static struct regulator_init_data cam_s_if_reg_init_data = {
|
||||
.constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &cam_s_if_supply,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
|
||||
.supply_name = "CAM_S_IF_1.8V",
|
||||
.microvolts = 1800000,
|
||||
.gpio = EXYNOS4_GPE3(0), /* CAM_PWR_EN1 */
|
||||
.enable_high = 1,
|
||||
.init_data = &cam_s_if_reg_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device cam_s_if_fixed_reg_dev = {
|
||||
.name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
|
||||
.dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
|
||||
};
|
||||
|
||||
static struct s5p_platform_mipi_csis mipi_csis_platdata = {
|
||||
.clk_rate = 166000000UL,
|
||||
.lanes = 2,
|
||||
.alignment = 32,
|
||||
.hs_settle = 12,
|
||||
.phy_enable = s5p_csis_phy_enable,
|
||||
};
|
||||
|
||||
#define GPIO_CAM_LEVEL_EN(n) EXYNOS4_GPE4(n + 3)
|
||||
#define GPIO_CAM_8M_ISP_INT EXYNOS4_GPX1(5) /* XEINT_13 */
|
||||
#define GPIO_CAM_MEGA_nRST EXYNOS4_GPE2(5)
|
||||
|
||||
static int m5mols_set_power(struct device *dev, int on)
|
||||
{
|
||||
gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
|
||||
gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct m5mols_platform_data m5mols_platdata = {
|
||||
.gpio_reset = GPIO_CAM_MEGA_nRST,
|
||||
.reset_polarity = 0,
|
||||
.set_power = m5mols_set_power,
|
||||
};
|
||||
|
||||
static struct i2c_board_info m5mols_board_info = {
|
||||
I2C_BOARD_INFO("M5MOLS", 0x1F),
|
||||
.platform_data = &m5mols_platdata,
|
||||
};
|
||||
|
||||
static struct s5p_fimc_isp_info universal_camera_sensors[] = {
|
||||
{
|
||||
.mux_id = 0,
|
||||
.flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
|
||||
V4L2_MBUS_VSYNC_ACTIVE_LOW,
|
||||
.bus_type = FIMC_MIPI_CSI2,
|
||||
.board_info = &m5mols_board_info,
|
||||
.i2c_bus_num = 0,
|
||||
.clk_frequency = 21600000UL,
|
||||
.csi_data_align = 32,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s5p_platform_fimc fimc_md_platdata = {
|
||||
.isp_info = universal_camera_sensors,
|
||||
.num_clients = ARRAY_SIZE(universal_camera_sensors),
|
||||
};
|
||||
|
||||
struct platform_device s5p_device_fimc_md = {
|
||||
.name = "s5p-fimc-md",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct gpio universal_camera_gpios[] = {
|
||||
{ GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
|
||||
{ GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW, "CAM_LVL_EN2" },
|
||||
{ GPIO_CAM_8M_ISP_INT, GPIOF_IN, "8M_ISP_INT" },
|
||||
{ GPIO_CAM_MEGA_nRST, GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
|
||||
};
|
||||
|
||||
static void universal_camera_init(void)
|
||||
{
|
||||
s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
|
||||
&s5p_device_mipi_csis0);
|
||||
s3c_set_platdata(&fimc_md_platdata, sizeof(fimc_md_platdata),
|
||||
&s5p_device_fimc_md);
|
||||
|
||||
if (gpio_request_array(universal_camera_gpios,
|
||||
ARRAY_SIZE(universal_camera_gpios))) {
|
||||
pr_err("%s: GPIO request failed\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
|
||||
m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
|
||||
else
|
||||
pr_err("Failed to configure 8M_ISP_INT GPIO\n");
|
||||
|
||||
/* Free GPIOs controlled directly by the sensor drivers. */
|
||||
gpio_free(GPIO_CAM_MEGA_nRST);
|
||||
gpio_free(GPIO_CAM_8M_ISP_INT);
|
||||
|
||||
if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
|
||||
pr_err("Camera port A setup failed\n");
|
||||
}
|
||||
|
||||
static struct platform_device *universal_devices[] __initdata = {
|
||||
/* Samsung Platform Devices */
|
||||
&s5p_device_mipi_csis0,
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
|
@ -712,17 +969,30 @@ static struct platform_device *universal_devices[] __initdata = {
|
|||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_i2c0,
|
||||
&s3c_device_i2c3,
|
||||
&s3c_device_i2c5,
|
||||
&s5p_device_i2c_hdmiphy,
|
||||
&hdmi_fixed_voltage,
|
||||
&exynos4_device_pd[PD_TV],
|
||||
&s5p_device_hdmi,
|
||||
&s5p_device_sdo,
|
||||
&s5p_device_mixer,
|
||||
|
||||
/* Universal Devices */
|
||||
&i2c_gpio12,
|
||||
&universal_gpio_keys,
|
||||
&s5p_device_onenand,
|
||||
&s5p_device_fimd0,
|
||||
&s5p_device_mfc,
|
||||
&s5p_device_mfc_l,
|
||||
&s5p_device_mfc_r,
|
||||
&exynos4_device_pd[PD_MFC],
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
&exynos4_device_pd[PD_CAM],
|
||||
&cam_i_core_fixed_reg_dev,
|
||||
&cam_s_if_fixed_reg_dev,
|
||||
&s5p_device_fimc_md,
|
||||
};
|
||||
|
||||
static void __init universal_map_io(void)
|
||||
|
@ -732,6 +1002,20 @@ static void __init universal_map_io(void)
|
|||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
}
|
||||
|
||||
void s5p_tv_setup(void)
|
||||
{
|
||||
/* direct HPD to HDMI chip */
|
||||
gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
|
||||
|
||||
gpio_direction_input(EXYNOS4_GPX3(7));
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
|
||||
|
||||
/* setup dependencies between TV devices */
|
||||
s5p_device_hdmi.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
s5p_device_mixer.dev.parent = &exynos4_device_pd[PD_TV].dev;
|
||||
}
|
||||
|
||||
static void __init universal_reserve(void)
|
||||
{
|
||||
s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
|
||||
|
@ -740,8 +1024,9 @@ static void __init universal_reserve(void)
|
|||
static void __init universal_machine_init(void)
|
||||
{
|
||||
universal_sdhci_init();
|
||||
s5p_tv_setup();
|
||||
|
||||
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
|
||||
s3c_i2c0_set_platdata(&universal_i2c0_platdata);
|
||||
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
|
||||
|
||||
universal_tsp_init();
|
||||
|
@ -749,15 +1034,28 @@ static void __init universal_machine_init(void)
|
|||
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
|
||||
|
||||
s3c_i2c5_set_platdata(NULL);
|
||||
s5p_i2c_hdmiphy_set_platdata(NULL);
|
||||
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
|
||||
|
||||
s5p_fimd0_set_platdata(&universal_lcd_pdata);
|
||||
|
||||
universal_touchkey_init();
|
||||
i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
|
||||
ARRAY_SIZE(i2c_gpio12_devs));
|
||||
|
||||
universal_camera_init();
|
||||
|
||||
/* Last */
|
||||
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
|
||||
|
||||
s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
|
||||
s5p_device_fimd0.dev.parent = &exynos4_device_pd[PD_LCD0].dev;
|
||||
|
||||
s5p_device_fimc0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
|
||||
s5p_device_fimc1.dev.parent = &exynos4_device_pd[PD_CAM].dev;
|
||||
s5p_device_fimc2.dev.parent = &exynos4_device_pd[PD_CAM].dev;
|
||||
s5p_device_fimc3.dev.parent = &exynos4_device_pd[PD_CAM].dev;
|
||||
s5p_device_mipi_csis0.dev.parent = &exynos4_device_pd[PD_CAM].dev;
|
||||
}
|
||||
|
||||
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
||||
|
|
|
@ -20,19 +20,31 @@
|
|||
#include <linux/delay.h>
|
||||
#include <linux/percpu.h>
|
||||
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/regs-mct.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
enum {
|
||||
MCT_INT_SPI,
|
||||
MCT_INT_PPI
|
||||
};
|
||||
|
||||
static unsigned long clk_cnt_per_tick;
|
||||
static unsigned long clk_rate;
|
||||
static unsigned int mct_int_type;
|
||||
|
||||
struct mct_clock_event_device {
|
||||
struct clock_event_device *evt;
|
||||
void __iomem *base;
|
||||
char name[10];
|
||||
};
|
||||
|
||||
struct mct_clock_event_device mct_tick[2];
|
||||
struct mct_clock_event_device mct_tick[NR_CPUS];
|
||||
|
||||
static void exynos4_mct_write(unsigned int value, void *addr)
|
||||
{
|
||||
|
@ -42,57 +54,53 @@ static void exynos4_mct_write(unsigned int value, void *addr)
|
|||
|
||||
__raw_writel(value, addr);
|
||||
|
||||
switch ((u32) addr) {
|
||||
case (u32) EXYNOS4_MCT_G_TCON:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 16; /* G_TCON write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_L:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 0; /* G_COMP0_L write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_U:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 1; /* G_COMP0_U write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_CNT_L:
|
||||
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
|
||||
mask = 1 << 0; /* G_CNT_L write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_CNT_U:
|
||||
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
|
||||
mask = 1 << 1; /* G_CNT_U write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 3; /* L0_TCON write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 3; /* L1_TCON write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 0; /* L0_TCNTB write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 0; /* L1_TCNTB write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 1; /* L0_ICNTB write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 1; /* L1_ICNTB write status */
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
|
||||
u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
|
||||
switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
|
||||
case (u32) MCT_L_TCON_OFFSET:
|
||||
stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 3; /* L_TCON write status */
|
||||
break;
|
||||
case (u32) MCT_L_ICNTB_OFFSET:
|
||||
stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 1; /* L_ICNTB write status */
|
||||
break;
|
||||
case (u32) MCT_L_TCNTB_OFFSET:
|
||||
stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 0; /* L_TCNTB write status */
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
switch ((u32) addr) {
|
||||
case (u32) EXYNOS4_MCT_G_TCON:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 16; /* G_TCON write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_L:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 0; /* G_COMP0_L write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_U:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 1; /* G_COMP0_U write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_CNT_L:
|
||||
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
|
||||
mask = 1 << 0; /* G_CNT_L write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_CNT_U:
|
||||
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
|
||||
mask = 1 << 1; /* G_CNT_U write status */
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Wait maximum 1 ms until written values are applied */
|
||||
|
@ -132,12 +140,18 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
|
|||
return ((cycle_t)hi << 32) | lo;
|
||||
}
|
||||
|
||||
static void exynos4_frc_resume(struct clocksource *cs)
|
||||
{
|
||||
exynos4_mct_frc_start(0, 0);
|
||||
}
|
||||
|
||||
struct clocksource mct_frc = {
|
||||
.name = "mct-frc",
|
||||
.rating = 400,
|
||||
.read = exynos4_frc_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
.resume = exynos4_frc_resume,
|
||||
};
|
||||
|
||||
static void __init exynos4_clocksource_init(void)
|
||||
|
@ -315,9 +329,8 @@ static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
|
|||
}
|
||||
}
|
||||
|
||||
static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
|
||||
static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
|
||||
{
|
||||
struct mct_clock_event_device *mevt = dev_id;
|
||||
struct clock_event_device *evt = mevt->evt;
|
||||
|
||||
/*
|
||||
|
@ -329,7 +342,20 @@ static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
|
|||
exynos4_mct_tick_stop(mevt);
|
||||
|
||||
/* Clear the MCT tick interrupt */
|
||||
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
|
||||
if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
|
||||
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct mct_clock_event_device *mevt = dev_id;
|
||||
struct clock_event_device *evt = mevt->evt;
|
||||
|
||||
exynos4_mct_tick_clear(mevt);
|
||||
|
||||
evt->event_handler(evt);
|
||||
|
||||
|
@ -354,14 +380,10 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
|
|||
|
||||
mct_tick[cpu].evt = evt;
|
||||
|
||||
if (cpu == 0) {
|
||||
mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
|
||||
evt->name = "mct_tick0";
|
||||
} else {
|
||||
mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
|
||||
evt->name = "mct_tick1";
|
||||
}
|
||||
mct_tick[cpu].base = EXYNOS4_MCT_L_BASE(cpu);
|
||||
sprintf(mct_tick[cpu].name, "mct_tick%d", cpu);
|
||||
|
||||
evt->name = mct_tick[cpu].name;
|
||||
evt->cpumask = cpumask_of(cpu);
|
||||
evt->set_next_event = exynos4_tick_set_next_event;
|
||||
evt->set_mode = exynos4_tick_set_mode;
|
||||
|
@ -378,25 +400,34 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
|
|||
|
||||
exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
|
||||
|
||||
if (cpu == 0) {
|
||||
mct_tick0_event_irq.dev_id = &mct_tick[cpu];
|
||||
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
|
||||
if (mct_int_type == MCT_INT_SPI) {
|
||||
if (cpu == 0) {
|
||||
mct_tick0_event_irq.dev_id = &mct_tick[cpu];
|
||||
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
|
||||
} else {
|
||||
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
|
||||
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
|
||||
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
|
||||
}
|
||||
} else {
|
||||
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
|
||||
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
|
||||
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
|
||||
gic_enable_ppi(IRQ_MCT_LOCALTIMER);
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup the local clock events for a CPU */
|
||||
void __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
int __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
{
|
||||
exynos4_mct_tick_init(evt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int local_timer_ack(void)
|
||||
{
|
||||
return 0;
|
||||
unsigned int cpu = smp_processor_id();
|
||||
struct mct_clock_event_device *mevt = &mct_tick[cpu];
|
||||
|
||||
return exynos4_mct_tick_clear(mevt);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
|
@ -411,6 +442,11 @@ static void __init exynos4_timer_resources(void)
|
|||
|
||||
static void __init exynos4_timer_init(void)
|
||||
{
|
||||
if (soc_is_exynos4210())
|
||||
mct_int_type = MCT_INT_SPI;
|
||||
else
|
||||
mct_int_type = MCT_INT_PPI;
|
||||
|
||||
exynos4_timer_resources();
|
||||
exynos4_clocksource_init();
|
||||
exynos4_clockevent_init();
|
||||
|
|
|
@ -30,9 +30,13 @@
|
|||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
extern unsigned int gic_bank_offset;
|
||||
extern void exynos4_secondary_startup(void);
|
||||
|
||||
#define CPU1_BOOT_REG S5P_VA_SYSRAM
|
||||
#define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
|
||||
S5P_INFORM5 : S5P_VA_SYSRAM)
|
||||
|
||||
/*
|
||||
* control for which core is the next to come out of the secondary
|
||||
|
@ -64,9 +68,9 @@ static DEFINE_SPINLOCK(boot_lock);
|
|||
static void __cpuinit exynos4_gic_secondary_init(void)
|
||||
{
|
||||
void __iomem *dist_base = S5P_VA_GIC_DIST +
|
||||
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
|
||||
(gic_bank_offset * smp_processor_id());
|
||||
void __iomem *cpu_base = S5P_VA_GIC_CPU +
|
||||
(EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
|
||||
(gic_bank_offset * smp_processor_id());
|
||||
int i;
|
||||
|
||||
/*
|
||||
|
@ -106,6 +110,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
|||
*/
|
||||
spin_lock(&boot_lock);
|
||||
spin_unlock(&boot_lock);
|
||||
|
||||
set_cpu_online(cpu, true);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
|
@ -216,5 +222,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
|
|||
* until it receives a soft interrupt, and then the
|
||||
* secondary CPU branches to this address.
|
||||
*/
|
||||
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
|
||||
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
|
||||
CPU1_BOOT_REG);
|
||||
}
|
||||
|
|
|
@ -41,7 +41,6 @@ static struct sleep_save exynos4_set_clksrc[] = {
|
|||
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
|
||||
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
|
||||
|
@ -49,6 +48,10 @@ static struct sleep_save exynos4_set_clksrc[] = {
|
|||
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4210_set_clksrc[] = {
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_epll_save[] = {
|
||||
SAVE_ITEM(S5P_EPLL_CON0),
|
||||
SAVE_ITEM(S5P_EPLL_CON1),
|
||||
|
@ -60,77 +63,6 @@ static struct sleep_save exynos4_vpll_save[] = {
|
|||
};
|
||||
|
||||
static struct sleep_save exynos4_core_save[] = {
|
||||
/* CMU side */
|
||||
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
|
||||
SAVE_ITEM(S5P_CLKSRC_TOP0),
|
||||
SAVE_ITEM(S5P_CLKSRC_TOP1),
|
||||
SAVE_ITEM(S5P_CLKSRC_CAM),
|
||||
SAVE_ITEM(S5P_CLKSRC_TV),
|
||||
SAVE_ITEM(S5P_CLKSRC_MFC),
|
||||
SAVE_ITEM(S5P_CLKSRC_G3D),
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD0),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKSRC_FSYS),
|
||||
SAVE_ITEM(S5P_CLKSRC_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKSRC_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV_CAM),
|
||||
SAVE_ITEM(S5P_CLKDIV_TV),
|
||||
SAVE_ITEM(S5P_CLKDIV_MFC),
|
||||
SAVE_ITEM(S5P_CLKDIV_G3D),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD0),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD1),
|
||||
SAVE_ITEM(S5P_CLKDIV_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS0),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS1),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS2),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS3),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL2),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL3),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL4),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL5),
|
||||
SAVE_ITEM(S5P_CLKDIV_TOP),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_TV),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV2_RATIO),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CAM),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_TV),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_MFC),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_G3D),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_GPS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
|
||||
SAVE_ITEM(S5P_CLKGATE_BLOCK),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
|
||||
SAVE_ITEM(S5P_CLKSRC_DMC),
|
||||
SAVE_ITEM(S5P_CLKDIV_DMC0),
|
||||
SAVE_ITEM(S5P_CLKDIV_DMC1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_DMC),
|
||||
SAVE_ITEM(S5P_CLKSRC_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
|
||||
|
||||
/* GIC side */
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
|
||||
|
@ -268,6 +200,9 @@ static void exynos4_pm_prepare(void)
|
|||
|
||||
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
|
||||
|
||||
if (soc_is_exynos4210())
|
||||
s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
|
||||
|
||||
}
|
||||
|
||||
static int exynos4_pm_add(struct sys_device *sysdev)
|
||||
|
@ -404,6 +339,13 @@ static int exynos4_pm_suspend(void)
|
|||
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
|
||||
if (soc_is_exynos4212()) {
|
||||
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
|
||||
tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
|
||||
S5P_USE_STANDBYWFE_ISP_ARM);
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
|
||||
}
|
||||
|
||||
/* Save Power control register */
|
||||
asm ("mrc p15, 0, %0, c15, c0, 0"
|
||||
: "=r" (tmp) : : "cc");
|
||||
|
|
|
@ -16,160 +16,215 @@
|
|||
#include <mach/regs-clock.h>
|
||||
#include <mach/pmu.h>
|
||||
|
||||
static void __iomem *sys_powerdown_reg[] = {
|
||||
S5P_ARM_CORE0_LOWPWR,
|
||||
S5P_DIS_IRQ_CORE0,
|
||||
S5P_DIS_IRQ_CENTRAL0,
|
||||
S5P_ARM_CORE1_LOWPWR,
|
||||
S5P_DIS_IRQ_CORE1,
|
||||
S5P_DIS_IRQ_CENTRAL1,
|
||||
S5P_ARM_COMMON_LOWPWR,
|
||||
S5P_L2_0_LOWPWR,
|
||||
S5P_L2_1_LOWPWR,
|
||||
S5P_CMU_ACLKSTOP_LOWPWR,
|
||||
S5P_CMU_SCLKSTOP_LOWPWR,
|
||||
S5P_CMU_RESET_LOWPWR,
|
||||
S5P_APLL_SYSCLK_LOWPWR,
|
||||
S5P_MPLL_SYSCLK_LOWPWR,
|
||||
S5P_VPLL_SYSCLK_LOWPWR,
|
||||
S5P_EPLL_SYSCLK_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
|
||||
S5P_CMU_RESET_GPSALIVE_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_CAM_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_TV_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_MFC_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_G3D_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_LCD0_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_LCD1_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
|
||||
S5P_CMU_CLKSTOP_GPS_LOWPWR,
|
||||
S5P_CMU_RESET_CAM_LOWPWR,
|
||||
S5P_CMU_RESET_TV_LOWPWR,
|
||||
S5P_CMU_RESET_MFC_LOWPWR,
|
||||
S5P_CMU_RESET_G3D_LOWPWR,
|
||||
S5P_CMU_RESET_LCD0_LOWPWR,
|
||||
S5P_CMU_RESET_LCD1_LOWPWR,
|
||||
S5P_CMU_RESET_MAUDIO_LOWPWR,
|
||||
S5P_CMU_RESET_GPS_LOWPWR,
|
||||
S5P_TOP_BUS_LOWPWR,
|
||||
S5P_TOP_RETENTION_LOWPWR,
|
||||
S5P_TOP_PWR_LOWPWR,
|
||||
S5P_LOGIC_RESET_LOWPWR,
|
||||
S5P_ONENAND_MEM_LOWPWR,
|
||||
S5P_MODIMIF_MEM_LOWPWR,
|
||||
S5P_G2D_ACP_MEM_LOWPWR,
|
||||
S5P_USBOTG_MEM_LOWPWR,
|
||||
S5P_HSMMC_MEM_LOWPWR,
|
||||
S5P_CSSYS_MEM_LOWPWR,
|
||||
S5P_SECSS_MEM_LOWPWR,
|
||||
S5P_PCIE_MEM_LOWPWR,
|
||||
S5P_SATA_MEM_LOWPWR,
|
||||
S5P_PAD_RETENTION_DRAM_LOWPWR,
|
||||
S5P_PAD_RETENTION_MAUDIO_LOWPWR,
|
||||
S5P_PAD_RETENTION_GPIO_LOWPWR,
|
||||
S5P_PAD_RETENTION_UART_LOWPWR,
|
||||
S5P_PAD_RETENTION_MMCA_LOWPWR,
|
||||
S5P_PAD_RETENTION_MMCB_LOWPWR,
|
||||
S5P_PAD_RETENTION_EBIA_LOWPWR,
|
||||
S5P_PAD_RETENTION_EBIB_LOWPWR,
|
||||
S5P_PAD_RETENTION_ISOLATION_LOWPWR,
|
||||
S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
|
||||
S5P_XUSBXTI_LOWPWR,
|
||||
S5P_XXTI_LOWPWR,
|
||||
S5P_EXT_REGULATOR_LOWPWR,
|
||||
S5P_GPIO_MODE_LOWPWR,
|
||||
S5P_GPIO_MODE_MAUDIO_LOWPWR,
|
||||
S5P_CAM_LOWPWR,
|
||||
S5P_TV_LOWPWR,
|
||||
S5P_MFC_LOWPWR,
|
||||
S5P_G3D_LOWPWR,
|
||||
S5P_LCD0_LOWPWR,
|
||||
S5P_LCD1_LOWPWR,
|
||||
S5P_MAUDIO_LOWPWR,
|
||||
S5P_GPS_LOWPWR,
|
||||
S5P_GPS_ALIVE_LOWPWR,
|
||||
static struct exynos4_pmu_conf *exynos4_pmu_config;
|
||||
|
||||
static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
|
||||
/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
|
||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } },
|
||||
{ S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } },
|
||||
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
||||
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
|
||||
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
|
||||
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ PMU_TABLE_END,},
|
||||
};
|
||||
|
||||
static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
|
||||
/* { AFTR, LPA, SLEEP }*/
|
||||
{ 0, 0, 2 }, /* ARM_CORE0 */
|
||||
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
|
||||
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
|
||||
{ 0, 0, 2 }, /* ARM_CORE1 */
|
||||
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
|
||||
{ 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
|
||||
{ 0, 0, 2 }, /* ARM_COMMON */
|
||||
{ 2, 2, 3 }, /* ARM_CPU_L2_0 */
|
||||
{ 2, 2, 3 }, /* ARM_CPU_L2_1 */
|
||||
{ 1, 0, 0 }, /* CMU_ACLKSTOP */
|
||||
{ 1, 0, 0 }, /* CMU_SCLKSTOP */
|
||||
{ 1, 1, 0 }, /* CMU_RESET */
|
||||
{ 1, 0, 0 }, /* APLL_SYSCLK */
|
||||
{ 1, 0, 0 }, /* MPLL_SYSCLK */
|
||||
{ 1, 0, 0 }, /* VPLL_SYSCLK */
|
||||
{ 1, 1, 0 }, /* EPLL_SYSCLK */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_TV */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
|
||||
{ 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_CAM */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_TV */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_MFC */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_G3D */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_LCD0 */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_LCD1 */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_MAUDIO */
|
||||
{ 1, 1, 0 }, /* CMU_RESET_GPS */
|
||||
{ 3, 0, 0 }, /* TOP_BUS */
|
||||
{ 1, 0, 1 }, /* TOP_RETENTION */
|
||||
{ 3, 0, 3 }, /* TOP_PWR */
|
||||
{ 1, 1, 0 }, /* LOGIC_RESET */
|
||||
{ 3, 0, 0 }, /* ONENAND_MEM */
|
||||
{ 3, 0, 0 }, /* MODIMIF_MEM */
|
||||
{ 3, 0, 0 }, /* G2D_ACP_MEM */
|
||||
{ 3, 0, 0 }, /* USBOTG_MEM */
|
||||
{ 3, 0, 0 }, /* HSMMC_MEM */
|
||||
{ 3, 0, 0 }, /* CSSYS_MEM */
|
||||
{ 3, 0, 0 }, /* SECSS_MEM */
|
||||
{ 3, 0, 0 }, /* PCIE_MEM */
|
||||
{ 3, 0, 0 }, /* SATA_MEM */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_DRAM */
|
||||
{ 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_GPIO */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_UART */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_MMCA */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_MMCB */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_EBIA */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_EBIB */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
|
||||
{ 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
|
||||
{ 1, 1, 0 }, /* XUSBXTI */
|
||||
{ 1, 1, 0 }, /* XXTI */
|
||||
{ 1, 1, 0 }, /* EXT_REGULATOR */
|
||||
{ 1, 0, 0 }, /* GPIO_MODE */
|
||||
{ 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
|
||||
{ 7, 0, 0 }, /* CAM */
|
||||
{ 7, 0, 0 }, /* TV */
|
||||
{ 7, 0, 0 }, /* MFC */
|
||||
{ 7, 0, 0 }, /* G3D */
|
||||
{ 7, 0, 0 }, /* LCD0 */
|
||||
{ 7, 0, 0 }, /* LCD1 */
|
||||
{ 7, 7, 0 }, /* MAUDIO */
|
||||
{ 7, 0, 0 }, /* GPS */
|
||||
{ 7, 0, 0 }, /* GPS_ALIVE */
|
||||
static struct exynos4_pmu_conf exynos4212_pmu_config[] = {
|
||||
{ S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } },
|
||||
{ S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } },
|
||||
{ S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } },
|
||||
/* XXX_OPTION register should be set other field */
|
||||
{ S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } },
|
||||
{ S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } },
|
||||
{ S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } },
|
||||
{ S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } },
|
||||
{ S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
||||
{ S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } },
|
||||
{ S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
|
||||
{ S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } },
|
||||
{ S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } },
|
||||
{ S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } },
|
||||
{ S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } },
|
||||
{ S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } },
|
||||
{ S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } },
|
||||
{ S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } },
|
||||
{ S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } },
|
||||
{ S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } },
|
||||
{ S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } },
|
||||
{ PMU_TABLE_END,},
|
||||
};
|
||||
|
||||
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
|
||||
{
|
||||
unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
|
||||
unsigned int i;
|
||||
|
||||
for (; count > 0; count--)
|
||||
__raw_writel(sys_powerdown_val[count - 1][mode],
|
||||
sys_powerdown_reg[count - 1]);
|
||||
for (i = 0; (exynos4_pmu_config[i].reg != PMU_TABLE_END) ; i++)
|
||||
__raw_writel(exynos4_pmu_config[i].val[mode],
|
||||
exynos4_pmu_config[i].reg);
|
||||
}
|
||||
|
||||
static int __init exynos4_pmu_init(void)
|
||||
{
|
||||
exynos4_pmu_config = exynos4210_pmu_config;
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
exynos4_pmu_config = exynos4210_pmu_config;
|
||||
pr_info("EXYNOS4210 PMU Initialize\n");
|
||||
} else if (soc_is_exynos4212()) {
|
||||
exynos4_pmu_config = exynos4212_pmu_config;
|
||||
pr_info("EXYNOS4212 PMU Initialize\n");
|
||||
} else {
|
||||
pr_info("EXYNOS4: PMU not supported\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos4_pmu_init);
|
||||
|
|
|
@ -19,15 +19,16 @@ void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
|||
|
||||
if (rows > 8) {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[0~7] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
|
||||
S3C_GPIO_PULL_UP);
|
||||
|
||||
/* Set all the necessary GPX3 pins: KP_ROW[8~] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
} else {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[x] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
|
||||
S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
|
||||
S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
/* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
|
||||
|
|
|
@ -10,16 +10,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include <plat/regs-sdhci.h>
|
||||
|
||||
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
|
||||
|
||||
|
@ -29,41 +20,3 @@ char *exynos4_hsmmc_clksrcs[4] = {
|
|||
[2] = "sclk_mmc", /* mmc_bus */
|
||||
[3] = NULL,
|
||||
};
|
||||
|
||||
void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
|
||||
struct mmc_ios *ios, struct mmc_card *card)
|
||||
{
|
||||
u32 ctrl2, ctrl3;
|
||||
|
||||
/* don't need to alter anything according to card-type */
|
||||
|
||||
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
|
||||
|
||||
/* select base clock source to HCLK */
|
||||
|
||||
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
|
||||
|
||||
/*
|
||||
* clear async mode, enable conflict mask, rx feedback ctrl, SD
|
||||
* clk hold and no use debounce count
|
||||
*/
|
||||
|
||||
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
|
||||
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
|
||||
S3C_SDHCI_CTRL2_ENFBCLKRX |
|
||||
S3C_SDHCI_CTRL2_DFCNT_NONE |
|
||||
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
|
||||
|
||||
/* Tx and Rx feedback clock delay control */
|
||||
|
||||
if (ios->clock < 25 * 1000000)
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
|
||||
S3C_SDHCI_CTRL3_FCSEL2 |
|
||||
S3C_SDHCI_CTRL3_FCSEL1 |
|
||||
S3C_SDHCI_CTRL3_FCSEL0);
|
||||
else
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
|
||||
|
||||
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
|
||||
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
|
||||
}
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
@ -154,6 +155,7 @@ static struct map_desc ap_io_desc[] __initdata = {
|
|||
static void __init ap_map_io(void)
|
||||
{
|
||||
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
|
||||
vga_base = PCI_MEMORY_VADDR;
|
||||
}
|
||||
|
||||
#define INTEGRATOR_SC_VALID_INT 0x003fffff
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <video/vga.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/platform.h>
|
||||
|
@ -505,7 +504,6 @@ void __init pci_v3_preinit(void)
|
|||
|
||||
pcibios_min_io = 0x6000;
|
||||
pcibios_min_mem = 0x00100000;
|
||||
vga_base = PCI_MEMORY_VADDR;
|
||||
|
||||
/*
|
||||
* Hook in our fault handler for PCI errors
|
||||
|
|
|
@ -6,9 +6,7 @@ config CPU_S3C2410
|
|||
bool
|
||||
depends on ARCH_S3C2410
|
||||
select CPU_ARM920T
|
||||
select S3C_GPIO_PULL_UP
|
||||
select S3C2410_CLOCK
|
||||
select S3C2410_GPIO
|
||||
select CPU_LLSERIAL_S3C2410
|
||||
select S3C2410_PM if PM
|
||||
select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
|
||||
|
@ -28,11 +26,6 @@ config S3C2410_PM
|
|||
help
|
||||
Power Management code common to S3C2410 and better
|
||||
|
||||
config S3C2410_GPIO
|
||||
bool
|
||||
help
|
||||
GPIO code for S3C2410 and similar processors
|
||||
|
||||
config SIMTEC_NOR
|
||||
bool
|
||||
help
|
||||
|
|
|
@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
|
|||
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
|
||||
obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o
|
||||
obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o
|
||||
obj-$(CONFIG_S3C2410_GPIO) += gpio.o
|
||||
obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o
|
||||
obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o
|
||||
|
||||
|
|
|
@ -47,38 +47,26 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
|
|||
.channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
|
||||
.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_SPI0] = {
|
||||
.name = "spi0",
|
||||
.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_SPI1] = {
|
||||
.name = "spi1",
|
||||
.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
|
@ -90,12 +78,10 @@ static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
|
|||
.name = "i2s-sdi",
|
||||
.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
|
||||
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_USB_EP1] = {
|
||||
.name = "usb-ep1",
|
||||
|
|
|
@ -1,72 +0,0 @@
|
|||
/* linux/arch/arm/mach-s3c2410/gpio.c
|
||||
*
|
||||
* Copyright (c) 2004-2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2410 GPIO support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/gpio-fns.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
|
||||
unsigned int config)
|
||||
{
|
||||
void __iomem *reg = S3C24XX_EINFLT0;
|
||||
unsigned long flags;
|
||||
unsigned long val;
|
||||
|
||||
if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15))
|
||||
return -EINVAL;
|
||||
|
||||
config &= 0xff;
|
||||
|
||||
pin -= S3C2410_GPG(8);
|
||||
reg += pin & ~3;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* update filter width and clock source */
|
||||
|
||||
val = __raw_readl(reg);
|
||||
val &= ~(0xff << ((pin & 3) * 8));
|
||||
val |= config << ((pin & 3) * 8);
|
||||
__raw_writel(val, reg);
|
||||
|
||||
/* update filter enable */
|
||||
|
||||
val = __raw_readl(S3C24XX_EXTINT2);
|
||||
val &= ~(1 << ((pin * 4) + 3));
|
||||
val |= on << ((pin * 4) + 3);
|
||||
__raw_writel(val, S3C24XX_EXTINT2);
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
|
|
@ -13,7 +13,6 @@
|
|||
#ifndef __ASM_ARCH_DMA_H
|
||||
#define __ASM_ARCH_DMA_H __FILE__
|
||||
|
||||
#include <plat/dma.h>
|
||||
#include <linux/sysdev.h>
|
||||
|
||||
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
|
||||
|
@ -51,6 +50,18 @@ enum dma_ch {
|
|||
DMACH_MAX, /* the end entry */
|
||||
};
|
||||
|
||||
static inline bool samsung_dma_has_circular(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool samsung_dma_is_dmadev(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#include <plat/dma.h>
|
||||
|
||||
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
|
||||
|
||||
/* we have 4 dma channels */
|
||||
|
@ -163,7 +174,7 @@ struct s3c2410_dma_chan {
|
|||
struct s3c2410_dma_client *client;
|
||||
|
||||
/* channel configuration */
|
||||
enum s3c2410_dmasrc source;
|
||||
enum dma_data_direction source;
|
||||
enum dma_ch req_ch;
|
||||
unsigned long dev_addr;
|
||||
unsigned long load_timeout;
|
||||
|
@ -196,9 +207,4 @@ struct s3c2410_dma_chan {
|
|||
|
||||
typedef unsigned long dma_device_t;
|
||||
|
||||
static inline bool s3c_dma_has_circular(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif /* __ASM_ARCH_DMA_H */
|
||||
|
|
|
@ -1,98 +1 @@
|
|||
/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
|
||||
*
|
||||
* Copyright (c) 2003-2009 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* S3C2410 - hardware
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_GPIO_FNS_H
|
||||
#define __MACH_GPIO_FNS_H __FILE__
|
||||
|
||||
/* These functions are in the to-be-removed category and it is strongly
|
||||
* encouraged not to use these in new code. They will be marked deprecated
|
||||
* very soon.
|
||||
*
|
||||
* Most of the functionality can be either replaced by the gpiocfg calls
|
||||
* for the s3c platform or by the generic GPIOlib API.
|
||||
*
|
||||
* As of 2.6.35-rc, these will be removed, with the few drivers using them
|
||||
* either replaced or given a wrapper until the calls can be removed.
|
||||
*/
|
||||
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
|
||||
{
|
||||
/* 1:1 mapping between cfgpin and setcfg calls at the moment */
|
||||
s3c_gpio_cfgpin(pin, cfg);
|
||||
}
|
||||
|
||||
/* external functions for GPIO support
|
||||
*
|
||||
* These allow various different clients to access the same GPIO
|
||||
* registers without conflicting. If your driver only owns the entire
|
||||
* GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
|
||||
*/
|
||||
|
||||
extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
|
||||
|
||||
/* s3c2410_gpio_getirq
|
||||
*
|
||||
* turn the given pin number into the corresponding IRQ number
|
||||
*
|
||||
* returns:
|
||||
* < 0 = no interrupt for this pin
|
||||
* >=0 = interrupt number for the pin
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_getirq(unsigned int pin);
|
||||
|
||||
/* s3c2410_gpio_irqfilter
|
||||
*
|
||||
* set the irq filtering on the given pin
|
||||
*
|
||||
* on = 0 => disable filtering
|
||||
* 1 => enable filtering
|
||||
*
|
||||
* config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
|
||||
* width of filter (0 through 63)
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
|
||||
unsigned int config);
|
||||
|
||||
/* s3c2410_gpio_pullup
|
||||
*
|
||||
* This call should be replaced with s3c_gpio_setpull().
|
||||
*
|
||||
* As a note, there is currently no distinction between pull-up and pull-down
|
||||
* in the s3c24xx series devices with only an on/off configuration.
|
||||
*/
|
||||
|
||||
/* s3c2410_gpio_pullup
|
||||
*
|
||||
* configure the pull-up control on the given pin
|
||||
*
|
||||
* to = 1 => disable the pull-up
|
||||
* 0 => enable the pull-up
|
||||
*
|
||||
* eg;
|
||||
*
|
||||
* s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
|
||||
* s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
|
||||
*/
|
||||
|
||||
extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
|
||||
|
||||
extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
|
||||
|
||||
extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
|
||||
|
||||
#endif /* __MACH_GPIO_FNS_H */
|
||||
#include <plat/gpio-fns.h>
|
||||
|
|
|
@ -17,11 +17,11 @@
|
|||
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
extern struct s3c_gpio_chip s3c24xx_gpios[];
|
||||
extern struct samsung_gpio_chip s3c24xx_gpios[];
|
||||
|
||||
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
|
||||
static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin)
|
||||
{
|
||||
struct s3c_gpio_chip *chip;
|
||||
struct samsung_gpio_chip *chip;
|
||||
|
||||
if (pin > S3C_GPIO_END)
|
||||
return NULL;
|
||||
|
|
|
@ -14,9 +14,53 @@
|
|||
#define __ASM_ARCH_MAP_H
|
||||
|
||||
#include <plat/map-base.h>
|
||||
#include <plat/map.h>
|
||||
|
||||
#define S3C2410_ADDR(x) S3C_ADDR(x)
|
||||
/*
|
||||
* S3C2410 UART offset is 0x4000 but the other SoCs are 0x400.
|
||||
* So need to define it, and here is to avoid redefinition warning.
|
||||
*/
|
||||
#define S3C_UART_OFFSET (0x4000)
|
||||
|
||||
#include <plat/map-s3c.h>
|
||||
|
||||
/*
|
||||
* interrupt controller is the first thing we put in, to make
|
||||
* the assembly code for the irq detection easier
|
||||
*/
|
||||
#define S3C2410_PA_IRQ (0x4A000000)
|
||||
#define S3C24XX_SZ_IRQ SZ_1M
|
||||
|
||||
/* memory controller registers */
|
||||
#define S3C2410_PA_MEMCTRL (0x48000000)
|
||||
#define S3C24XX_SZ_MEMCTRL SZ_1M
|
||||
|
||||
/* UARTs */
|
||||
#define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET)))
|
||||
|
||||
/* Timers */
|
||||
#define S3C2410_PA_TIMER (0x51000000)
|
||||
#define S3C24XX_SZ_TIMER SZ_1M
|
||||
|
||||
/* Clock and Power management */
|
||||
#define S3C24XX_SZ_CLKPWR SZ_1M
|
||||
|
||||
/* USB Device port */
|
||||
#define S3C2410_PA_USBDEV (0x52000000)
|
||||
#define S3C24XX_SZ_USBDEV SZ_1M
|
||||
|
||||
/* Watchdog */
|
||||
#define S3C2410_PA_WATCHDOG (0x53000000)
|
||||
#define S3C24XX_SZ_WATCHDOG SZ_1M
|
||||
|
||||
/* Standard size definitions for peripheral blocks. */
|
||||
|
||||
#define S3C24XX_SZ_UART SZ_1M
|
||||
#define S3C24XX_SZ_IIS SZ_1M
|
||||
#define S3C24XX_SZ_ADC SZ_1M
|
||||
#define S3C24XX_SZ_SPI SZ_1M
|
||||
#define S3C24XX_SZ_SDI SZ_1M
|
||||
#define S3C24XX_SZ_NAND SZ_1M
|
||||
#define S3C24XX_SZ_GPIO SZ_1M
|
||||
|
||||
/* USB host controller */
|
||||
#define S3C2410_PA_USBHOST (0x49000000)
|
||||
|
@ -75,10 +119,8 @@
|
|||
|
||||
/* S3C2412 memory and IO controls */
|
||||
#define S3C2412_PA_SSMC (0x4F000000)
|
||||
#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
|
||||
|
||||
#define S3C2412_PA_EBI (0x48800000)
|
||||
#define S3C2412_VA_EBI S3C_ADDR_CPU(0x00010000)
|
||||
|
||||
/* physical addresses of all the chip-select areas */
|
||||
|
||||
|
@ -100,12 +142,10 @@
|
|||
#define S3C24XX_PA_DMA S3C2410_PA_DMA
|
||||
#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
|
||||
#define S3C24XX_PA_LCD S3C2410_PA_LCD
|
||||
#define S3C24XX_PA_UART S3C2410_PA_UART
|
||||
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
|
||||
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
|
||||
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
|
||||
#define S3C24XX_PA_IIS S3C2410_PA_IIS
|
||||
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
|
||||
#define S3C24XX_PA_RTC S3C2410_PA_RTC
|
||||
#define S3C24XX_PA_ADC S3C2410_PA_ADC
|
||||
#define S3C24XX_PA_SPI S3C2410_PA_SPI
|
||||
|
|
|
@ -64,4 +64,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
|
|||
}
|
||||
|
||||
static inline void s3c_pm_restored_gpios(void) { }
|
||||
static inline void s3c_pm_saved_gpios(void) { }
|
||||
static inline void samsung_pm_saved_gpios(void) { }
|
||||
|
|
|
@ -102,6 +102,7 @@
|
|||
#define S3C2443_PCLKCON_UART3 (1<<3)
|
||||
#define S3C2443_PCLKCON_IIC (1<<4)
|
||||
#define S3C2443_PCLKCON_SDI (1<<5)
|
||||
#define S3C2443_PCLKCON_HSSPI (1<<6)
|
||||
#define S3C2443_PCLKCON_ADC (1<<7)
|
||||
#define S3C2443_PCLKCON_AC97 (1<<8)
|
||||
#define S3C2443_PCLKCON_IIS (1<<9)
|
||||
|
|
|
@ -696,9 +696,9 @@ static void __init h1940_init(void)
|
|||
S3C2410_MISCCR_USBSUSPND0 |
|
||||
S3C2410_MISCCR_USBSUSPND1, 0x0);
|
||||
|
||||
tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
|
||||
| (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
|
||||
| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
|
||||
tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT)
|
||||
| (0x02 << S3C24XX_PLL_PDIV_SHIFT)
|
||||
| (0x03 << S3C24XX_PLL_SDIV_SHIFT);
|
||||
writel(tmp, S3C2410_UPLLCON);
|
||||
|
||||
gpio_request(S3C2410_GPC(0), "LCD power");
|
||||
|
|
|
@ -72,8 +72,8 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
|||
|
||||
void __init s3c2410_map_io(void)
|
||||
{
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
|
||||
|
||||
iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc));
|
||||
}
|
||||
|
|
|
@ -9,7 +9,6 @@ config CPU_S3C2412
|
|||
select CPU_LLSERIAL_S3C2440
|
||||
select S3C2412_PM if PM
|
||||
select S3C2412_DMA if S3C2410_DMA
|
||||
select S3C2410_GPIO
|
||||
help
|
||||
Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
|
||||
|
||||
|
|
|
@ -12,7 +12,6 @@ obj- :=
|
|||
obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
|
||||
obj-$(CONFIG_CPU_S3C2412) += irq.o
|
||||
obj-$(CONFIG_CPU_S3C2412) += clock.o
|
||||
obj-$(CONFIG_CPU_S3C2412) += gpio.o
|
||||
obj-$(CONFIG_S3C2412_DMA) += dma.o
|
||||
obj-$(CONFIG_S3C2412_PM) += pm.o
|
||||
obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o
|
||||
|
|
|
@ -50,64 +50,46 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
|
|||
.name = "sdi",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SDI),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_SDI),
|
||||
.hw_addr.to = S3C2410_PA_SDI + S3C2410_SDIDATA,
|
||||
.hw_addr.from = S3C2410_PA_SDI + S3C2410_SDIDATA,
|
||||
},
|
||||
[DMACH_SPI0] = {
|
||||
.name = "spi0",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_SPI0RX),
|
||||
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_SPI1] = {
|
||||
.name = "spi1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_SPI1RX),
|
||||
.hw_addr.to = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + S3C2412_SPI1 + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART0_0),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_UART0_0),
|
||||
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART1_0),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_UART1_0),
|
||||
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART2_0),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_UART2_0),
|
||||
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART0_SRC2] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART0_1),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_UART0_1),
|
||||
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART1_SRC2] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART1_1),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_UART1_1),
|
||||
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART2_SRC2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2412_DMAREQSEL_UART2_1),
|
||||
.channels_rx = MAP(S3C2412_DMAREQSEL_UART2_1),
|
||||
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
|
@ -148,11 +130,11 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
|
|||
|
||||
static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
|
||||
struct s3c24xx_dma_map *map,
|
||||
enum s3c2410_dmasrc dir)
|
||||
enum dma_data_direction dir)
|
||||
{
|
||||
unsigned long chsel;
|
||||
|
||||
if (dir == S3C2410_DMASRC_HW)
|
||||
if (dir == DMA_FROM_DEVICE)
|
||||
chsel = map->channels_rx[0];
|
||||
else
|
||||
chsel = map->channels[0];
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
|
||||
{
|
||||
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
|
||||
struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
|
||||
unsigned long offs = pin - chip->chip.base;
|
||||
unsigned long flags;
|
||||
unsigned long slpcon;
|
||||
|
|
|
@ -13,7 +13,6 @@ config CPU_S3C2416
|
|||
select CPU_ARM926T
|
||||
select S3C2416_DMA if S3C2410_DMA
|
||||
select CPU_LLSERIAL_S3C2440
|
||||
select S3C_GPIO_PULL_UPDOWN
|
||||
select SAMSUNG_CLKSRC
|
||||
select S3C2443_CLOCK
|
||||
help
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <plat/cpu.h>
|
||||
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/pll6553x.h>
|
||||
#include <plat/pll.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -38,6 +37,32 @@ static unsigned int armdiv[8] = {
|
|||
[7] = 8,
|
||||
};
|
||||
|
||||
static struct clksrc_clk hsspi_eplldiv = {
|
||||
.clk = {
|
||||
.name = "hsspi-eplldiv",
|
||||
.parent = &clk_esysclk.clk,
|
||||
.ctrlbit = (1 << 14),
|
||||
.enable = s3c2443_clkcon_enable_s,
|
||||
},
|
||||
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
|
||||
};
|
||||
|
||||
static struct clk *hsspi_sources[] = {
|
||||
[0] = &hsspi_eplldiv.clk,
|
||||
[1] = NULL, /* to fix */
|
||||
};
|
||||
|
||||
static struct clksrc_clk hsspi_mux = {
|
||||
.clk = {
|
||||
.name = "hsspi-if",
|
||||
},
|
||||
.sources = &(struct clksrc_sources) {
|
||||
.sources = hsspi_sources,
|
||||
.nr_sources = ARRAY_SIZE(hsspi_sources),
|
||||
},
|
||||
.reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
|
||||
};
|
||||
|
||||
static struct clksrc_clk hsmmc_div[] = {
|
||||
[0] = {
|
||||
.clk = {
|
||||
|
@ -114,6 +139,8 @@ void __init_or_cpufreq s3c2416_setup_clocks(void)
|
|||
|
||||
|
||||
static struct clksrc_clk *clksrcs[] __initdata = {
|
||||
&hsspi_eplldiv,
|
||||
&hsspi_mux,
|
||||
&hsmmc_div[0],
|
||||
&hsmmc_div[1],
|
||||
&hsmmc_mux[0],
|
||||
|
|
|
@ -118,8 +118,8 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
|||
|
||||
void __init s3c2416_map_io(void)
|
||||
{
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
|
||||
s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown;
|
||||
s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown;
|
||||
|
||||
/* initialize device information early */
|
||||
s3c2416_default_sdhci0();
|
||||
|
|
|
@ -12,17 +12,7 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include <plat/regs-sdhci.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
|
||||
|
||||
|
@ -32,30 +22,3 @@ char *s3c2416_hsmmc_clksrcs[4] = {
|
|||
[2] = "hsmmc-if",
|
||||
/* [3] = "48m", - note not successfully used yet */
|
||||
};
|
||||
|
||||
void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
|
||||
void __iomem *r,
|
||||
struct mmc_ios *ios,
|
||||
struct mmc_card *card)
|
||||
{
|
||||
u32 ctrl2, ctrl3;
|
||||
|
||||
ctrl2 = __raw_readl(r + S3C_SDHCI_CONTROL2);
|
||||
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
|
||||
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
|
||||
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
|
||||
S3C_SDHCI_CTRL2_ENFBCLKRX |
|
||||
S3C_SDHCI_CTRL2_DFCNT_NONE |
|
||||
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
|
||||
|
||||
if (ios->clock < 25 * 1000000)
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
|
||||
S3C_SDHCI_CTRL3_FCSEL2 |
|
||||
S3C_SDHCI_CTRL3_FCSEL1 |
|
||||
S3C_SDHCI_CTRL3_FCSEL0);
|
||||
else
|
||||
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
|
||||
|
||||
__raw_writel(ctrl2, r + S3C_SDHCI_CONTROL2);
|
||||
__raw_writel(ctrl3, r + S3C_SDHCI_CONTROL3);
|
||||
}
|
||||
|
|
|
@ -5,10 +5,8 @@
|
|||
config CPU_S3C2440
|
||||
bool
|
||||
select CPU_ARM920T
|
||||
select S3C_GPIO_PULL_UP
|
||||
select S3C2410_CLOCK
|
||||
select S3C2410_PM if PM
|
||||
select S3C2410_GPIO
|
||||
select S3C2440_DMA if S3C2410_DMA
|
||||
select CPU_S3C244X
|
||||
select CPU_LLSERIAL_S3C2440
|
||||
|
@ -18,9 +16,7 @@ config CPU_S3C2440
|
|||
config CPU_S3C2442
|
||||
bool
|
||||
select CPU_ARM920T
|
||||
select S3C_GPIO_PULL_DOWN
|
||||
select S3C2410_CLOCK
|
||||
select S3C2410_GPIO
|
||||
select S3C2410_PM if PM
|
||||
select CPU_S3C244X
|
||||
select CPU_LLSERIAL_S3C2440
|
||||
|
|
|
@ -48,38 +48,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
|
|||
.channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
|
||||
.channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_SPI0] = {
|
||||
.name = "spi0",
|
||||
.channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_SPI1] = {
|
||||
.name = "spi1",
|
||||
.channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
|
@ -91,31 +79,26 @@ static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
|
|||
.name = "i2s-sdi",
|
||||
.channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
|
||||
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
|
||||
.channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_PCM_IN] = {
|
||||
.name = "pcm-in",
|
||||
.channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
|
||||
.channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
|
||||
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
|
||||
},
|
||||
[DMACH_PCM_OUT] = {
|
||||
.name = "pcm-out",
|
||||
.channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
|
||||
.channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
|
||||
.hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
|
||||
},
|
||||
[DMACH_MIC_IN] = {
|
||||
.name = "mic-in",
|
||||
.channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
|
||||
.channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
|
||||
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
|
||||
},
|
||||
[DMACH_USB_EP1] = {
|
||||
.name = "usb-ep1",
|
||||
|
|
|
@ -68,6 +68,6 @@ void __init s3c2440_map_io(void)
|
|||
{
|
||||
s3c244x_map_io();
|
||||
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
|
||||
}
|
||||
|
|
|
@ -180,6 +180,6 @@ void __init s3c2442_map_io(void)
|
|||
{
|
||||
s3c244x_map_io();
|
||||
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down;
|
||||
}
|
||||
|
|
|
@ -10,7 +10,6 @@ config CPU_S3C2443
|
|||
select CPU_LLSERIAL_S3C2440
|
||||
select SAMSUNG_CLKSRC
|
||||
select S3C2443_CLOCK
|
||||
select S3C_GPIO_PULL_S3C2443
|
||||
help
|
||||
Support for the S3C2443 SoC from the S3C24XX line
|
||||
|
||||
|
|
|
@ -57,10 +57,6 @@
|
|||
|
||||
/* clock selections */
|
||||
|
||||
static struct clk clk_i2s_ext = {
|
||||
.name = "i2s-ext",
|
||||
};
|
||||
|
||||
/* armdiv
|
||||
*
|
||||
* this clock is sourced from msysclk and can have a number of
|
||||
|
@ -128,7 +124,7 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
|
|||
unsigned long clkcon0;
|
||||
|
||||
clkcon0 = __raw_readl(S3C2443_CLKDIV0);
|
||||
clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 &= ~S3C2443_CLKDIV0_ARMDIV_MASK;
|
||||
clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
|
||||
__raw_writel(clkcon0, S3C2443_CLKDIV0);
|
||||
}
|
||||
|
@ -173,7 +169,7 @@ static struct clksrc_clk clk_arm = {
|
|||
|
||||
static struct clksrc_clk clk_hsspi = {
|
||||
.clk = {
|
||||
.name = "hsspi",
|
||||
.name = "hsspi-if",
|
||||
.parent = &clk_esysclk.clk,
|
||||
.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
|
||||
.enable = s3c2443_clkcon_enable_s,
|
||||
|
@ -235,48 +231,6 @@ static struct clk clk_hsmmc = {
|
|||
},
|
||||
};
|
||||
|
||||
/* i2s_eplldiv
|
||||
*
|
||||
* This clock is the output from the I2S divisor of ESYSCLK, and is separate
|
||||
* from the mux that comes after it (cannot merge into one single clock)
|
||||
*/
|
||||
|
||||
static struct clksrc_clk clk_i2s_eplldiv = {
|
||||
.clk = {
|
||||
.name = "i2s-eplldiv",
|
||||
.parent = &clk_esysclk.clk,
|
||||
},
|
||||
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
|
||||
};
|
||||
|
||||
/* i2s-ref
|
||||
*
|
||||
* i2s bus reference clock, selectable from external, esysclk or epllref
|
||||
*
|
||||
* Note, this used to be two clocks, but was compressed into one.
|
||||
*/
|
||||
|
||||
struct clk *clk_i2s_srclist[] = {
|
||||
[0] = &clk_i2s_eplldiv.clk,
|
||||
[1] = &clk_i2s_ext,
|
||||
[2] = &clk_epllref.clk,
|
||||
[3] = &clk_epllref.clk,
|
||||
};
|
||||
|
||||
static struct clksrc_clk clk_i2s = {
|
||||
.clk = {
|
||||
.name = "i2s-if",
|
||||
.ctrlbit = S3C2443_SCLKCON_I2SCLK,
|
||||
.enable = s3c2443_clkcon_enable_s,
|
||||
|
||||
},
|
||||
.sources = &(struct clksrc_sources) {
|
||||
.sources = clk_i2s_srclist,
|
||||
.nr_sources = ARRAY_SIZE(clk_i2s_srclist),
|
||||
},
|
||||
.reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
|
||||
};
|
||||
|
||||
/* standard clock definitions */
|
||||
|
||||
static struct clk init_clocks_off[] = {
|
||||
|
@ -285,11 +239,6 @@ static struct clk init_clocks_off[] = {
|
|||
.parent = &clk_p,
|
||||
.enable = s3c2443_clkcon_enable_p,
|
||||
.ctrlbit = S3C2443_PCLKCON_SDI,
|
||||
}, {
|
||||
.name = "iis",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2443_clkcon_enable_p,
|
||||
.ctrlbit = S3C2443_PCLKCON_IIS,
|
||||
}, {
|
||||
.name = "spi",
|
||||
.devname = "s3c2410-spi.0",
|
||||
|
@ -312,8 +261,6 @@ static struct clk init_clocks[] = {
|
|||
|
||||
static struct clksrc_clk *clksrcs[] __initdata = {
|
||||
&clk_arm,
|
||||
&clk_i2s_eplldiv,
|
||||
&clk_i2s,
|
||||
&clk_hsspi,
|
||||
&clk_hsmmc_div,
|
||||
};
|
||||
|
|
|
@ -54,68 +54,46 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
|
|||
[DMACH_SDI] = {
|
||||
.name = "sdi",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SDI),
|
||||
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_SPI0] = {
|
||||
.name = "spi0",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
|
||||
.hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_SPI1] = {
|
||||
.name = "spi1",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
|
||||
.hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
|
||||
.hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
|
||||
},
|
||||
[DMACH_UART0] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART0_0),
|
||||
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART1] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART1_0),
|
||||
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART2_0),
|
||||
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART3] = {
|
||||
.name = "uart3",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART3_0),
|
||||
.hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART0_SRC2] = {
|
||||
.name = "uart0",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART0_1),
|
||||
.hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART1_SRC2] = {
|
||||
.name = "uart1",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART1_1),
|
||||
.hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART2_SRC2] = {
|
||||
.name = "uart2",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART2_1),
|
||||
.hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_UART3_SRC2] = {
|
||||
.name = "uart3",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_UART3_1),
|
||||
.hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
|
||||
.hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
|
||||
},
|
||||
[DMACH_TIMER] = {
|
||||
.name = "timer",
|
||||
|
@ -124,27 +102,22 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
|
|||
[DMACH_I2S_IN] = {
|
||||
.name = "i2s-sdi",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_I2SRX),
|
||||
.hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_I2S_OUT] = {
|
||||
.name = "i2s-sdo",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_I2STX),
|
||||
.hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
|
||||
},
|
||||
[DMACH_PCM_IN] = {
|
||||
.name = "pcm-in",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_PCMIN),
|
||||
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
|
||||
},
|
||||
[DMACH_PCM_OUT] = {
|
||||
.name = "pcm-out",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
|
||||
.hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
|
||||
},
|
||||
[DMACH_MIC_IN] = {
|
||||
.name = "mic-in",
|
||||
.channels = MAP(S3C2443_DMAREQSEL_MICIN),
|
||||
.hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
@ -90,8 +90,8 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
|||
|
||||
void __init s3c2443_map_io(void)
|
||||
{
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443;
|
||||
s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull;
|
||||
s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull;
|
||||
|
||||
iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
|
||||
}
|
||||
|
|
|
@ -288,5 +288,6 @@ config MACH_WLF_CRAGG_6410
|
|||
select S3C_DEV_RTC
|
||||
select S3C64XX_DEV_SPI
|
||||
select S3C24XX_GPIO_EXTRA128
|
||||
select I2C
|
||||
help
|
||||
Machine support for the Wolfson Cragganmore S3C6410 variant.
|
||||
|
|
|
@ -13,7 +13,6 @@ obj- :=
|
|||
# Core files
|
||||
obj-y += cpu.o
|
||||
obj-y += clock.o
|
||||
obj-y += gpiolib.o
|
||||
|
||||
# Core support for S3C6400 system
|
||||
|
||||
|
@ -55,7 +54,7 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
|
|||
obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
|
||||
obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
|
||||
obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
|
||||
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
|
||||
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
|
||||
|
||||
# device support
|
||||
|
||||
|
|
|
@ -25,13 +25,13 @@
|
|||
|
||||
#include <mach/regs-sys.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/pll.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu-freq.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/clock-clksrc.h>
|
||||
#include <plat/pll.h>
|
||||
|
||||
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
|
||||
* ext_xtal_mux for want of an actual name from the manual.
|
||||
|
@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
|
|||
/* For now assume the mux always selects the crystal */
|
||||
clk_ext_xtal_mux.parent = xtal_clk;
|
||||
|
||||
epll = s3c6400_get_epll(xtal);
|
||||
epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
|
||||
__raw_readl(S3C_EPLL_CON1));
|
||||
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
|
||||
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
|
||||
|
||||
|
@ -744,7 +745,13 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
|
|||
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
|
||||
apll, mpll, epll);
|
||||
|
||||
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
|
||||
if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
|
||||
/* Synchronous mode */
|
||||
hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
|
||||
else
|
||||
/* Asynchronous mode */
|
||||
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
|
||||
|
||||
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
|
||||
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
|
||||
|
||||
|
|
|
@ -33,8 +33,8 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/clock.h>
|
||||
|
||||
#include <mach/s3c6400.h>
|
||||
#include <mach/s3c6410.h>
|
||||
#include <plat/s3c6400.h>
|
||||
#include <plat/s3c6410.h>
|
||||
|
||||
/* table of supported CPUs */
|
||||
|
||||
|
@ -43,16 +43,16 @@ static const char name_s3c6410[] = "S3C6410";
|
|||
|
||||
static struct cpu_table cpu_ids[] __initdata = {
|
||||
{
|
||||
.idcode = 0x36400000,
|
||||
.idmask = 0xfffff000,
|
||||
.idcode = S3C6400_CPU_ID,
|
||||
.idmask = S3C64XX_CPU_MASK,
|
||||
.map_io = s3c6400_map_io,
|
||||
.init_clocks = s3c6400_init_clocks,
|
||||
.init_uarts = s3c6400_init_uarts,
|
||||
.init = s3c6400_init,
|
||||
.name = name_s3c6400,
|
||||
}, {
|
||||
.idcode = 0x36410100,
|
||||
.idmask = 0xffffff00,
|
||||
.idcode = S3C6410_CPU_ID,
|
||||
.idmask = S3C64XX_CPU_MASK,
|
||||
.map_io = s3c6410_map_io,
|
||||
.init_clocks = s3c6410_init_clocks,
|
||||
.init_uarts = s3c6410_init_uarts,
|
||||
|
@ -140,22 +140,14 @@ void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
|||
|
||||
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
|
||||
{
|
||||
unsigned long idcode;
|
||||
|
||||
/* initialise the io descriptors we need for initialisation */
|
||||
iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
|
||||
iotable_init(mach_desc, size);
|
||||
|
||||
idcode = __raw_readl(S3C_VA_SYS + 0x118);
|
||||
if (!idcode) {
|
||||
/* S3C6400 has the ID register in a different place,
|
||||
* and needs a write before it can be read. */
|
||||
/* detect cpu id */
|
||||
s3c64xx_init_cpu();
|
||||
|
||||
__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
|
||||
idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
|
||||
}
|
||||
|
||||
s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
|
||||
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
|
||||
}
|
||||
|
||||
static __init int s3c64xx_sysdev_init(void)
|
||||
|
|
|
@ -147,14 +147,14 @@ static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan,
|
|||
u32 control0, control1;
|
||||
|
||||
switch (chan->source) {
|
||||
case S3C2410_DMASRC_HW:
|
||||
case DMA_FROM_DEVICE:
|
||||
src = chan->dev_addr;
|
||||
dst = data;
|
||||
control0 = PL080_CONTROL_SRC_AHB2;
|
||||
control0 |= PL080_CONTROL_DST_INCR;
|
||||
break;
|
||||
|
||||
case S3C2410_DMASRC_MEM:
|
||||
case DMA_TO_DEVICE:
|
||||
src = data;
|
||||
dst = chan->dev_addr;
|
||||
control0 = PL080_CONTROL_DST_AHB2;
|
||||
|
@ -416,7 +416,7 @@ EXPORT_SYMBOL(s3c2410_dma_enqueue);
|
|||
|
||||
|
||||
int s3c2410_dma_devconfig(enum dma_ch channel,
|
||||
enum s3c2410_dmasrc source,
|
||||
enum dma_data_direction source,
|
||||
unsigned long devaddr)
|
||||
{
|
||||
struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
|
||||
|
@ -437,11 +437,11 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
|
|||
pr_debug("%s: peripheral %d\n", __func__, peripheral);
|
||||
|
||||
switch (source) {
|
||||
case S3C2410_DMASRC_HW:
|
||||
case DMA_FROM_DEVICE:
|
||||
config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
|
||||
config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT;
|
||||
break;
|
||||
case S3C2410_DMASRC_MEM:
|
||||
case DMA_TO_DEVICE:
|
||||
config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT;
|
||||
config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT;
|
||||
break;
|
||||
|
@ -740,7 +740,7 @@ static int __init s3c64xx_dma_init(void)
|
|||
}
|
||||
|
||||
/* Set all DMA configuration to be DMA, not SDMA */
|
||||
writel(0xffffff, S3C_SYSREG(0x110));
|
||||
writel(0xffffff, S3C64XX_SDMA_SEL);
|
||||
|
||||
/* Register standard DMA controllers */
|
||||
s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
|
||||
|
|
|
@ -1,290 +0,0 @@
|
|||
/* arch/arm/plat-s3c64xx/gpiolib.c
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX - GPIOlib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/gpio-cfg-helpers.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
/* GPIO bank summary:
|
||||
*
|
||||
* Bank GPIOs Style SlpCon ExtInt Group
|
||||
* A 8 4Bit Yes 1
|
||||
* B 7 4Bit Yes 1
|
||||
* C 8 4Bit Yes 2
|
||||
* D 5 4Bit Yes 3
|
||||
* E 5 4Bit Yes None
|
||||
* F 16 2Bit Yes 4 [1]
|
||||
* G 7 4Bit Yes 5
|
||||
* H 10 4Bit[2] Yes 6
|
||||
* I 16 2Bit Yes None
|
||||
* J 12 2Bit Yes None
|
||||
* K 16 4Bit[2] No None
|
||||
* L 15 4Bit[2] No None
|
||||
* M 6 4Bit No IRQ_EINT
|
||||
* N 16 2Bit No IRQ_EINT
|
||||
* O 16 2Bit Yes 7
|
||||
* P 15 2Bit Yes 8
|
||||
* Q 9 2Bit Yes 9
|
||||
*
|
||||
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
|
||||
* [2] BANK has two control registers, GPxCON0 and GPxCON1
|
||||
*/
|
||||
|
||||
static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
|
||||
.cfg_eint = 7,
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
|
||||
.cfg_eint = 3,
|
||||
.get_config = s3c_gpio_getcfg_s3c64xx_4bit,
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
|
||||
}
|
||||
|
||||
static struct s3c_gpio_chip gpio_4bit[] = {
|
||||
{
|
||||
.base = S3C64XX_GPA_BASE,
|
||||
.config = &gpio_4bit_cfg_eint0111,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPA(0),
|
||||
.ngpio = S3C64XX_GPIO_A_NR,
|
||||
.label = "GPA",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPB_BASE,
|
||||
.config = &gpio_4bit_cfg_eint0111,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPB(0),
|
||||
.ngpio = S3C64XX_GPIO_B_NR,
|
||||
.label = "GPB",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPC_BASE,
|
||||
.config = &gpio_4bit_cfg_eint0111,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPC(0),
|
||||
.ngpio = S3C64XX_GPIO_C_NR,
|
||||
.label = "GPC",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPD_BASE,
|
||||
.config = &gpio_4bit_cfg_eint0111,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPD(0),
|
||||
.ngpio = S3C64XX_GPIO_D_NR,
|
||||
.label = "GPD",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPE_BASE,
|
||||
.config = &gpio_4bit_cfg_noint,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPE(0),
|
||||
.ngpio = S3C64XX_GPIO_E_NR,
|
||||
.label = "GPE",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPG_BASE,
|
||||
.config = &gpio_4bit_cfg_eint0111,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPG(0),
|
||||
.ngpio = S3C64XX_GPIO_G_NR,
|
||||
.label = "GPG",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPM_BASE,
|
||||
.config = &gpio_4bit_cfg_eint0011,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPM(0),
|
||||
.ngpio = S3C64XX_GPIO_M_NR,
|
||||
.label = "GPM",
|
||||
.to_irq = s3c64xx_gpio2int_gpm,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
|
||||
{
|
||||
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
|
||||
}
|
||||
|
||||
static struct s3c_gpio_chip gpio_4bit2[] = {
|
||||
{
|
||||
.base = S3C64XX_GPH_BASE + 0x4,
|
||||
.config = &gpio_4bit_cfg_eint0111,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPH(0),
|
||||
.ngpio = S3C64XX_GPIO_H_NR,
|
||||
.label = "GPH",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPK_BASE + 0x4,
|
||||
.config = &gpio_4bit_cfg_noint,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPK(0),
|
||||
.ngpio = S3C64XX_GPIO_K_NR,
|
||||
.label = "GPK",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPL_BASE + 0x4,
|
||||
.config = &gpio_4bit_cfg_eint0011,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPL(0),
|
||||
.ngpio = S3C64XX_GPIO_L_NR,
|
||||
.label = "GPL",
|
||||
.to_irq = s3c64xx_gpio2int_gpl,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
|
||||
.set_config = s3c_gpio_setcfg_s3c24xx,
|
||||
.get_config = s3c_gpio_getcfg_s3c24xx,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
|
||||
.cfg_eint = 2,
|
||||
.set_config = s3c_gpio_setcfg_s3c24xx,
|
||||
.get_config = s3c_gpio_getcfg_s3c24xx,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
|
||||
.cfg_eint = 3,
|
||||
.set_config = s3c_gpio_setcfg_s3c24xx,
|
||||
.get_config = s3c_gpio_getcfg_s3c24xx,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_chip gpio_2bit[] = {
|
||||
{
|
||||
.base = S3C64XX_GPF_BASE,
|
||||
.config = &gpio_2bit_cfg_eint11,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPF(0),
|
||||
.ngpio = S3C64XX_GPIO_F_NR,
|
||||
.label = "GPF",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPI_BASE,
|
||||
.config = &gpio_2bit_cfg_noint,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPI(0),
|
||||
.ngpio = S3C64XX_GPIO_I_NR,
|
||||
.label = "GPI",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPJ_BASE,
|
||||
.config = &gpio_2bit_cfg_noint,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPJ(0),
|
||||
.ngpio = S3C64XX_GPIO_J_NR,
|
||||
.label = "GPJ",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPN_BASE,
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.config = &gpio_2bit_cfg_eint10,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPN(0),
|
||||
.ngpio = S3C64XX_GPIO_N_NR,
|
||||
.label = "GPN",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPO_BASE,
|
||||
.config = &gpio_2bit_cfg_eint11,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPO(0),
|
||||
.ngpio = S3C64XX_GPIO_O_NR,
|
||||
.label = "GPO",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPP_BASE,
|
||||
.config = &gpio_2bit_cfg_eint11,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPP(0),
|
||||
.ngpio = S3C64XX_GPIO_P_NR,
|
||||
.label = "GPP",
|
||||
},
|
||||
}, {
|
||||
.base = S3C64XX_GPQ_BASE,
|
||||
.config = &gpio_2bit_cfg_eint11,
|
||||
.chip = {
|
||||
.base = S3C64XX_GPQ(0),
|
||||
.ngpio = S3C64XX_GPIO_Q_NR,
|
||||
.label = "GPQ",
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
|
||||
{
|
||||
chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
|
||||
}
|
||||
|
||||
static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
|
||||
int nr_chips,
|
||||
void (*fn)(struct s3c_gpio_chip *))
|
||||
{
|
||||
for (; nr_chips > 0; nr_chips--, chips++) {
|
||||
if (fn)
|
||||
(fn)(chips);
|
||||
s3c_gpiolib_add(chips);
|
||||
}
|
||||
}
|
||||
|
||||
static __init int s3c64xx_gpiolib_init(void)
|
||||
{
|
||||
s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
|
||||
samsung_gpiolib_add_4bit);
|
||||
|
||||
s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
|
||||
samsung_gpiolib_add_4bit2);
|
||||
|
||||
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
|
||||
s3c64xx_gpiolib_add_2bit);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
core_initcall(s3c64xx_gpiolib_init);
|
|
@ -1,7 +0,0 @@
|
|||
#ifndef __MACH_CLKDEV_H__
|
||||
#define __MACH_CLKDEV_H__
|
||||
|
||||
#define __clk_get(clk) ({ 1; })
|
||||
#define __clk_put(clk) do {} while (0)
|
||||
|
||||
#endif
|
23
arch/arm/mach-s3c64xx/include/mach/crag6410.h
Normal file
23
arch/arm/mach-s3c64xx/include/mach/crag6410.h
Normal file
|
@ -0,0 +1,23 @@
|
|||
/* Cragganmore 6410 shared definitions
|
||||
*
|
||||
* Copyright 2011 Wolfson Microelectronics plc
|
||||
* Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef MACH_CRAG6410_H
|
||||
#define MACH_CRAG6410_H
|
||||
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
|
||||
#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
|
||||
|
||||
#define PCA935X_GPIO_BASE GPIO_BOARD_START
|
||||
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
|
||||
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
|
||||
|
||||
#endif
|
|
@ -58,11 +58,15 @@ enum dma_ch {
|
|||
DMACH_MAX /* the end */
|
||||
};
|
||||
|
||||
static __inline__ bool s3c_dma_has_circular(void)
|
||||
static inline bool samsung_dma_has_circular(void)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline bool samsung_dma_is_dmadev(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#define S3C2410_DMAF_CIRCULAR (1 << 0)
|
||||
|
||||
#include <plat/dma.h>
|
||||
|
@ -95,7 +99,7 @@ struct s3c2410_dma_chan {
|
|||
unsigned char peripheral;
|
||||
|
||||
unsigned int flags;
|
||||
enum s3c2410_dmasrc source;
|
||||
enum dma_data_direction source;
|
||||
|
||||
|
||||
dma_addr_t dev_addr;
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#define __ASM_ARCH_MAP_H __FILE__
|
||||
|
||||
#include <plat/map-base.h>
|
||||
#include <plat/map-s3c.h>
|
||||
|
||||
/*
|
||||
* Post-mux Chip Select Regions Xm0CSn_
|
||||
|
@ -83,7 +84,6 @@
|
|||
#define S3C64XX_PA_IIC1 (0x7F00F000)
|
||||
|
||||
#define S3C64XX_PA_GPIO (0x7F008000)
|
||||
#define S3C64XX_VA_GPIO S3C_ADDR_CPU(0x00000000)
|
||||
#define S3C64XX_SZ_GPIO SZ_4K
|
||||
|
||||
#define S3C64XX_PA_SDRAM (0x50000000)
|
||||
|
@ -94,16 +94,10 @@
|
|||
#define S3C64XX_PA_VIC1 (0x71300000)
|
||||
|
||||
#define S3C64XX_PA_MODEM (0x74108000)
|
||||
#define S3C64XX_VA_MODEM S3C_ADDR_CPU(0x00100000)
|
||||
|
||||
#define S3C64XX_PA_USBHOST (0x74300000)
|
||||
|
||||
#define S3C64XX_PA_USB_HSPHY (0x7C100000)
|
||||
#define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000)
|
||||
|
||||
/* place VICs close together */
|
||||
#define VA_VIC0 (S3C_VA_IRQ + 0x00)
|
||||
#define VA_VIC1 (S3C_VA_IRQ + 0x10000)
|
||||
|
||||
/* compatibiltiy defines. */
|
||||
#define S3C_PA_TIMER S3C64XX_PA_TIMER
|
||||
|
@ -119,7 +113,6 @@
|
|||
#define S3C_PA_FB S3C64XX_PA_FB
|
||||
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST
|
||||
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
|
||||
#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
|
||||
#define S3C_PA_RTC S3C64XX_PA_RTC
|
||||
#define S3C_PA_WDT S3C64XX_PA_WATCHDOG
|
||||
|
||||
|
|
|
@ -1,45 +0,0 @@
|
|||
/* arch/arm/plat-s3c64xx/include/plat/pll.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64XX PLL code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
|
||||
#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
|
||||
#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
|
||||
#define S3C6400_PLL_MDIV_SHIFT (16)
|
||||
#define S3C6400_PLL_PDIV_SHIFT (8)
|
||||
#define S3C6400_PLL_SDIV_SHIFT (0)
|
||||
|
||||
#include <asm/div64.h>
|
||||
#include <plat/pll6553x.h>
|
||||
|
||||
static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
|
||||
u32 pllcon)
|
||||
{
|
||||
u32 mdiv, pdiv, sdiv;
|
||||
u64 fvco = baseclk;
|
||||
|
||||
mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
|
||||
pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
|
||||
sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
|
||||
|
||||
fvco *= mdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
|
||||
{
|
||||
return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
|
||||
__raw_readl(S3C_EPLL_CON1));
|
||||
}
|
|
@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void)
|
|||
__raw_writel(0, S3C64XX_SLPEN);
|
||||
}
|
||||
|
||||
static inline void s3c_pm_saved_gpios(void)
|
||||
static inline void samsung_pm_saved_gpios(void)
|
||||
{
|
||||
/* turn on the sleep mode and keep it there, as it seems that during
|
||||
* suspend the xCON registers get re-set and thus you can end up with
|
||||
|
|
|
@ -1,56 +0,0 @@
|
|||
/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* S3C64xx - pwm clock and timer support
|
||||
*/
|
||||
|
||||
/**
|
||||
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
|
||||
* @tcfg: The timer TCFG1 register bits shifted down to 0.
|
||||
*
|
||||
* Return true if the given configuration from TCFG1 is a TCLK instead
|
||||
* any of the TDIV clocks.
|
||||
*/
|
||||
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
|
||||
{
|
||||
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
|
||||
}
|
||||
|
||||
/**
|
||||
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
|
||||
* @tcfg1: The tcfg1 setting, shifted down.
|
||||
*
|
||||
* Get the divisor value for the given tcfg1 setting. We assume the
|
||||
* caller has already checked to see if this is not a TCLK source.
|
||||
*/
|
||||
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
|
||||
{
|
||||
return 1 << tcfg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
|
||||
*
|
||||
* Return true if we have a /1 in the tdiv setting.
|
||||
*/
|
||||
static inline unsigned int pwm_tdiv_has_div1(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
|
||||
* @div: The divisor to calculate the bit information for.
|
||||
*
|
||||
* Turn a divisor into the necessary bit field for TCFG1.
|
||||
*/
|
||||
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
|
||||
{
|
||||
return ilog2(div);
|
||||
}
|
||||
|
||||
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
|
|
@ -21,8 +21,11 @@
|
|||
#define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
|
||||
#define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
|
||||
|
||||
#define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
|
||||
|
||||
#define S3C64XX_OTHERS S3C_SYSREG(0x900)
|
||||
|
||||
#define S3C64XX_OTHERS_USBMASK (1 << 16)
|
||||
#define S3C64XX_OTHERS_SYNCMUXSEL (1 << 6)
|
||||
|
||||
#endif /* _PLAT_REGS_SYS_H */
|
||||
|
|
|
@ -45,7 +45,7 @@
|
|||
#include <plat/fb.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
|
||||
#include <mach/s3c6410.h>
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
|
182
arch/arm/mach-s3c64xx/mach-crag6410-module.c
Normal file
182
arch/arm/mach-s3c64xx/mach-crag6410-module.c
Normal file
|
@ -0,0 +1,182 @@
|
|||
/* Speyside modules for Cragganmore - board data probing
|
||||
*
|
||||
* Copyright 2011 Wolfson Microelectronics plc
|
||||
* Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/i2c.h>
|
||||
|
||||
#include <linux/mfd/wm831x/irq.h>
|
||||
#include <linux/mfd/wm831x/gpio.h>
|
||||
|
||||
#include <sound/wm8996.h>
|
||||
#include <sound/wm8962.h>
|
||||
#include <sound/wm9081.h>
|
||||
|
||||
#include <mach/crag6410.h>
|
||||
|
||||
static struct wm8996_retune_mobile_config wm8996_retune[] = {
|
||||
{
|
||||
.name = "Sub LPF",
|
||||
.rate = 48000,
|
||||
.regs = {
|
||||
0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
|
||||
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
|
||||
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "Sub HPF",
|
||||
.rate = 48000,
|
||||
.regs = {
|
||||
0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
|
||||
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
|
||||
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct wm8996_pdata wm8996_pdata __initdata = {
|
||||
.ldo_ena = S3C64XX_GPN(7),
|
||||
.gpio_base = CODEC_GPIO_BASE,
|
||||
.micdet_def = 1,
|
||||
.inl_mode = WM8996_DIFFERRENTIAL_1,
|
||||
.inr_mode = WM8996_DIFFERRENTIAL_1,
|
||||
|
||||
.irq_flags = IRQF_TRIGGER_RISING,
|
||||
|
||||
.gpio_default = {
|
||||
0x8001, /* GPIO1 == ADCLRCLK1 */
|
||||
0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
|
||||
0x0141, /* GPIO3 == HP_SEL */
|
||||
0x0002, /* GPIO4 == IRQ */
|
||||
0x020e, /* GPIO5 == CLKOUT */
|
||||
},
|
||||
|
||||
.retune_mobile_cfgs = wm8996_retune,
|
||||
.num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
|
||||
};
|
||||
|
||||
static struct wm8962_pdata wm8962_pdata __initdata = {
|
||||
.gpio_init = {
|
||||
0,
|
||||
WM8962_GPIO_FN_OPCLK,
|
||||
WM8962_GPIO_FN_DMICCLK,
|
||||
0,
|
||||
0x8000 | WM8962_GPIO_FN_DMICDAT,
|
||||
WM8962_GPIO_FN_IRQ, /* Open drain mode */
|
||||
},
|
||||
.irq_active_low = true,
|
||||
};
|
||||
|
||||
static struct wm9081_pdata wm9081_pdata __initdata = {
|
||||
.irq_high = false,
|
||||
.irq_cmos = false,
|
||||
};
|
||||
|
||||
static const struct i2c_board_info wm1254_devs[] = {
|
||||
{ I2C_BOARD_INFO("wm8996", 0x1a),
|
||||
.platform_data = &wm8996_pdata,
|
||||
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
|
||||
},
|
||||
{ I2C_BOARD_INFO("wm9081", 0x6c),
|
||||
.platform_data = &wm9081_pdata, },
|
||||
};
|
||||
|
||||
static const struct i2c_board_info wm1255_devs[] = {
|
||||
{ I2C_BOARD_INFO("wm5100", 0x1a),
|
||||
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
|
||||
},
|
||||
{ I2C_BOARD_INFO("wm9081", 0x6c),
|
||||
.platform_data = &wm9081_pdata, },
|
||||
};
|
||||
|
||||
static const struct i2c_board_info wm1259_devs[] = {
|
||||
{ I2C_BOARD_INFO("wm8962", 0x1a),
|
||||
.platform_data = &wm8962_pdata,
|
||||
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static __devinitdata const struct {
|
||||
u8 id;
|
||||
const char *name;
|
||||
const struct i2c_board_info *i2c_devs;
|
||||
int num_i2c_devs;
|
||||
} gf_mods[] = {
|
||||
{ .id = 0x01, .name = "1250-EV1 Springbank" },
|
||||
{ .id = 0x02, .name = "1251-EV1 Jura" },
|
||||
{ .id = 0x03, .name = "1252-EV1 Glenlivet" },
|
||||
{ .id = 0x11, .name = "6249-EV2 Glenfarclas", },
|
||||
{ .id = 0x21, .name = "1275-EV1 Mortlach" },
|
||||
{ .id = 0x25, .name = "1274-EV1 Glencadam" },
|
||||
{ .id = 0x31, .name = "1253-EV1 Tomatin", },
|
||||
{ .id = 0x39, .name = "1254-EV1 Dallas Dhu",
|
||||
.i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
|
||||
{ .id = 0x3a, .name = "1259-EV1 Tobermory",
|
||||
.i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
|
||||
{ .id = 0x3b, .name = "1255-EV1 Kilchoman",
|
||||
.i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
|
||||
{ .id = 0x3c, .name = "1273-EV1 Longmorn" },
|
||||
};
|
||||
|
||||
static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *i2c_id)
|
||||
{
|
||||
int ret, i, j, id, rev;
|
||||
|
||||
ret = i2c_smbus_read_byte_data(i2c, 0);
|
||||
if (ret < 0) {
|
||||
dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
id = (ret & 0xfe) >> 2;
|
||||
rev = ret & 0x3;
|
||||
for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
|
||||
if (id == gf_mods[i].id)
|
||||
break;
|
||||
|
||||
if (i < ARRAY_SIZE(gf_mods)) {
|
||||
dev_info(&i2c->dev, "%s revision %d\n",
|
||||
gf_mods[i].name, rev + 1);
|
||||
for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
|
||||
if (!i2c_new_device(i2c->adapter,
|
||||
&(gf_mods[i].i2c_devs[j])))
|
||||
dev_err(&i2c->dev,
|
||||
"Failed to register dev: %d\n", ret);
|
||||
}
|
||||
} else {
|
||||
dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
|
||||
id, rev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id wlf_gf_module_id[] = {
|
||||
{ "wlf-gf-module", 0 },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct i2c_driver wlf_gf_module_driver = {
|
||||
.driver = {
|
||||
.name = "wlf-gf-module",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = wlf_gf_module_probe,
|
||||
.id_table = wlf_gf_module_id,
|
||||
};
|
||||
|
||||
static int __init wlf_gf_module_register(void)
|
||||
{
|
||||
return i2c_add_driver(&wlf_gf_module_driver);
|
||||
}
|
||||
module_init(wlf_gf_module_register);
|
|
@ -43,13 +43,14 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <mach/s3c6410.h>
|
||||
#include <mach/regs-sys.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-modem.h>
|
||||
#include <mach/crag6410.h>
|
||||
|
||||
#include <mach/regs-gpio-memport.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-fb-v4.h>
|
||||
#include <plat/fb.h>
|
||||
|
@ -65,17 +66,6 @@
|
|||
#include <plat/iic.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <sound/wm8996.h>
|
||||
#include <sound/wm8962.h>
|
||||
#include <sound/wm9081.h>
|
||||
|
||||
#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
|
||||
#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
|
||||
|
||||
#define PCA935X_GPIO_BASE GPIO_BOARD_START
|
||||
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
|
||||
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
|
||||
|
||||
/* serial port setup */
|
||||
|
||||
#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
|
||||
|
@ -287,6 +277,11 @@ static struct platform_device speyside_device = {
|
|||
.id = -1,
|
||||
};
|
||||
|
||||
static struct platform_device lowland_device = {
|
||||
.name = "lowland",
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
static struct platform_device speyside_wm8962_device = {
|
||||
.name = "speyside-wm8962",
|
||||
.id = -1,
|
||||
|
@ -295,6 +290,8 @@ static struct platform_device speyside_wm8962_device = {
|
|||
static struct regulator_consumer_supply wallvdd_consumers[] = {
|
||||
REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
|
||||
REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
|
||||
REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
|
||||
REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data wallvdd_data = {
|
||||
|
@ -329,9 +326,6 @@ static struct platform_device *crag6410_devices[] __initdata = {
|
|||
&s3c_device_fb,
|
||||
&s3c_device_ohci,
|
||||
&s3c_device_usb_hsotg,
|
||||
&s3c_device_adc,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_ts,
|
||||
&s3c_device_timer[0],
|
||||
&s3c64xx_device_iis0,
|
||||
&s3c64xx_device_iis1,
|
||||
|
@ -345,6 +339,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
|
|||
&crag6410_backlight_device,
|
||||
&speyside_device,
|
||||
&speyside_wm8962_device,
|
||||
&lowland_device,
|
||||
&wallvdd_device,
|
||||
};
|
||||
|
||||
|
@ -353,6 +348,12 @@ static struct pca953x_platform_data crag6410_pca_data = {
|
|||
.irq_base = 0,
|
||||
};
|
||||
|
||||
/* VDDARM is controlled by DVS1 connected to GPK(0) */
|
||||
static struct wm831x_buckv_pdata vddarm_pdata = {
|
||||
.dvs_control_src = 1,
|
||||
.dvs_gpio = S3C64XX_GPK(0),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
|
||||
REGULATOR_SUPPLY("vddarm", NULL),
|
||||
};
|
||||
|
@ -368,6 +369,7 @@ static struct regulator_init_data vddarm __initdata = {
|
|||
.num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
|
||||
.consumer_supplies = vddarm_consumers,
|
||||
.supply_regulator = "WALLVDD",
|
||||
.driver_data = &vddarm_pdata,
|
||||
};
|
||||
|
||||
static struct regulator_init_data vddint __initdata = {
|
||||
|
@ -503,6 +505,8 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = {
|
|||
.backup = &banff_backup_pdata,
|
||||
|
||||
.gpio_defaults = {
|
||||
/* GPIO5: DVS1_REQ - CMOS, DBVDD, active high */
|
||||
[4] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA | 0x8,
|
||||
/* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
|
||||
[10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
|
||||
/* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
|
||||
|
@ -560,8 +564,12 @@ static struct regulator_init_data pvdd_1v2 __initdata = {
|
|||
};
|
||||
|
||||
static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
|
||||
REGULATOR_SUPPLY("LDOVDD", "1-001a"),
|
||||
REGULATOR_SUPPLY("PLLVDD", "1-001a"),
|
||||
REGULATOR_SUPPLY("DBVDD", "1-001a"),
|
||||
REGULATOR_SUPPLY("DBVDD1", "1-001a"),
|
||||
REGULATOR_SUPPLY("DBVDD2", "1-001a"),
|
||||
REGULATOR_SUPPLY("DBVDD3", "1-001a"),
|
||||
REGULATOR_SUPPLY("CPVDD", "1-001a"),
|
||||
REGULATOR_SUPPLY("AVDD2", "1-001a"),
|
||||
REGULATOR_SUPPLY("DCVDD", "1-001a"),
|
||||
|
@ -614,81 +622,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
|
|||
.disable_touch = true,
|
||||
};
|
||||
|
||||
static struct wm8996_retune_mobile_config wm8996_retune[] = {
|
||||
{
|
||||
.name = "Sub LPF",
|
||||
.rate = 48000,
|
||||
.regs = {
|
||||
0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
|
||||
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
|
||||
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "Sub HPF",
|
||||
.rate = 48000,
|
||||
.regs = {
|
||||
0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
|
||||
0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
|
||||
0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct wm8996_pdata wm8996_pdata __initdata = {
|
||||
.ldo_ena = S3C64XX_GPN(7),
|
||||
.gpio_base = CODEC_GPIO_BASE,
|
||||
.micdet_def = 1,
|
||||
.inl_mode = WM8996_DIFFERRENTIAL_1,
|
||||
.inr_mode = WM8996_DIFFERRENTIAL_1,
|
||||
|
||||
.irq_flags = IRQF_TRIGGER_RISING,
|
||||
|
||||
.gpio_default = {
|
||||
0x8001, /* GPIO1 == ADCLRCLK1 */
|
||||
0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
|
||||
0x0141, /* GPIO3 == HP_SEL */
|
||||
0x0002, /* GPIO4 == IRQ */
|
||||
0x020e, /* GPIO5 == CLKOUT */
|
||||
},
|
||||
|
||||
.retune_mobile_cfgs = wm8996_retune,
|
||||
.num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
|
||||
};
|
||||
|
||||
static struct wm8962_pdata wm8962_pdata __initdata = {
|
||||
.gpio_init = {
|
||||
0,
|
||||
WM8962_GPIO_FN_OPCLK,
|
||||
WM8962_GPIO_FN_DMICCLK,
|
||||
0,
|
||||
0x8000 | WM8962_GPIO_FN_DMICDAT,
|
||||
WM8962_GPIO_FN_IRQ, /* Open drain mode */
|
||||
},
|
||||
.irq_active_low = true,
|
||||
};
|
||||
|
||||
static struct wm9081_pdata wm9081_pdata __initdata = {
|
||||
.irq_high = false,
|
||||
.irq_cmos = false,
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_devs1[] __initdata = {
|
||||
{ I2C_BOARD_INFO("wm8311", 0x34),
|
||||
.irq = S3C_EINT(0),
|
||||
.platform_data = &glenfarclas_pmic_pdata },
|
||||
|
||||
{ I2C_BOARD_INFO("wlf-gf-module", 0x24) },
|
||||
{ I2C_BOARD_INFO("wlf-gf-module", 0x25) },
|
||||
{ I2C_BOARD_INFO("wlf-gf-module", 0x26) },
|
||||
|
||||
{ I2C_BOARD_INFO("wm1250-ev1", 0x27) },
|
||||
{ I2C_BOARD_INFO("wm8996", 0x1a),
|
||||
.platform_data = &wm8996_pdata,
|
||||
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
|
||||
},
|
||||
{ I2C_BOARD_INFO("wm9081", 0x6c),
|
||||
.platform_data = &wm9081_pdata, },
|
||||
{ I2C_BOARD_INFO("wm8962", 0x1a),
|
||||
.platform_data = &wm8962_pdata,
|
||||
.irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init crag6410_map_io(void)
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
#include <plat/fb.h>
|
||||
#include <plat/nand.h>
|
||||
|
||||
#include <mach/s3c6410.h>
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
|
|
@ -32,8 +32,8 @@
|
|||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-modem.h>
|
||||
#include <mach/regs-srom.h>
|
||||
#include <mach/s3c6410.h>
|
||||
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/adc.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
|
@ -205,12 +205,6 @@ static struct platform_device mini6410_lcd_powerdev = {
|
|||
.dev.platform_data = &mini6410_lcd_power_data,
|
||||
};
|
||||
|
||||
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
|
||||
.delay = 10000,
|
||||
.presc = 49,
|
||||
.oversampling_shift = 2,
|
||||
};
|
||||
|
||||
static struct platform_device *mini6410_devices[] __initdata = {
|
||||
&mini6410_device_eth,
|
||||
&s3c_device_hsmmc0,
|
||||
|
@ -319,7 +313,7 @@ static void __init mini6410_machine_init(void)
|
|||
|
||||
s3c_nand_set_platdata(&mini6410_nand_info);
|
||||
s3c_fb_set_platdata(&mini6410_lcd_pdata);
|
||||
s3c24xx_ts_set_platdata(&s3c_ts_platform);
|
||||
s3c24xx_ts_set_platdata(NULL);
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
|
||||
|
|
|
@ -39,7 +39,7 @@
|
|||
#include <plat/iic.h>
|
||||
#include <plat/fb.h>
|
||||
|
||||
#include <mach/s3c6410.h>
|
||||
#include <plat/s3c6410.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
|
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