arm64/sve: Low-level SVE architectural state manipulation functions
Manipulating the SVE architectural state, including the vector and predicate registers, first-fault register and the vector length, requires the use of dedicated instructions added by SVE. This patch adds suitable assembly functions for saving and restoring the SVE registers and querying the vector length. Setting of the vector length is done as part of register restore. Since people building kernels may not all get an SVE-enabled toolchain for a while, this patch uses macros that generate explicit opcodes in place of assembler mnemonics. Signed-off-by: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Dave Martin
Will Deacon
parent
672365649c
commit
1fc5dce78a
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@ -67,6 +67,11 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state);
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extern void fpsimd_flush_task_state(struct task_struct *target);
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extern void sve_save_state(void *state, u32 *pfpsr);
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extern void sve_load_state(void const *state, u32 const *pfpsr,
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unsigned long vq_minus_1);
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extern unsigned int sve_get_vl(void);
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/* For use by EFI runtime services calls only */
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extern void __efi_fpsimd_begin(void);
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extern void __efi_fpsimd_end(void);
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@ -75,3 +75,151 @@
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ldr w\tmpnr, [\state, #16 * 2 + 4]
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fpsimd_restore_fpcr x\tmpnr, \state
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.endm
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/* Sanity-check macros to help avoid encoding garbage instructions */
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.macro _check_general_reg nr
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.if (\nr) < 0 || (\nr) > 30
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.error "Bad register number \nr."
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.endif
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.endm
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.macro _sve_check_zreg znr
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.if (\znr) < 0 || (\znr) > 31
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.error "Bad Scalable Vector Extension vector register number \znr."
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.endif
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.endm
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.macro _sve_check_preg pnr
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.if (\pnr) < 0 || (\pnr) > 15
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.error "Bad Scalable Vector Extension predicate register number \pnr."
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.endif
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.endm
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.macro _check_num n, min, max
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.if (\n) < (\min) || (\n) > (\max)
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.error "Number \n out of range [\min,\max]"
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.endif
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.endm
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/* SVE instruction encodings for non-SVE-capable assemblers */
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/* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_str_v nz, nxbase, offset=0
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_sve_check_zreg \nz
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0xe5804000 \
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| (\nz) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_ldr_v nz, nxbase, offset=0
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_sve_check_zreg \nz
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0x85804000 \
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| (\nz) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_str_p np, nxbase, offset=0
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_sve_check_preg \np
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0xe5800000 \
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| (\np) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */
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.macro _sve_ldr_p np, nxbase, offset=0
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_sve_check_preg \np
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_check_general_reg \nxbase
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_check_num (\offset), -0x100, 0xff
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.inst 0x85800000 \
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| (\np) \
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| ((\nxbase) << 5) \
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| (((\offset) & 7) << 10) \
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| (((\offset) & 0x1f8) << 13)
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.endm
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/* RDVL X\nx, #\imm */
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.macro _sve_rdvl nx, imm
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_check_general_reg \nx
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_check_num (\imm), -0x20, 0x1f
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.inst 0x04bf5000 \
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| (\nx) \
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| (((\imm) & 0x3f) << 5)
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.endm
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/* RDFFR (unpredicated): RDFFR P\np.B */
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.macro _sve_rdffr np
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_sve_check_preg \np
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.inst 0x2519f000 \
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| (\np)
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.endm
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/* WRFFR P\np.B */
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.macro _sve_wrffr np
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_sve_check_preg \np
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.inst 0x25289000 \
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| ((\np) << 5)
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.endm
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.macro __for from:req, to:req
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.if (\from) == (\to)
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_for__body \from
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.else
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__for \from, (\from) + ((\to) - (\from)) / 2
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__for (\from) + ((\to) - (\from)) / 2 + 1, \to
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.endif
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.endm
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.macro _for var:req, from:req, to:req, insn:vararg
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.macro _for__body \var:req
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\insn
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.endm
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__for \from, \to
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.purgem _for__body
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.endm
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.macro sve_save nxbase, xpfpsr, nxtmp
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_for n, 0, 31, _sve_str_v \n, \nxbase, \n - 34
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_for n, 0, 15, _sve_str_p \n, \nxbase, \n - 16
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_sve_rdffr 0
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_sve_str_p 0, \nxbase
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_sve_ldr_p 0, \nxbase, -16
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mrs x\nxtmp, fpsr
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str w\nxtmp, [\xpfpsr]
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mrs x\nxtmp, fpcr
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str w\nxtmp, [\xpfpsr, #4]
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.endm
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.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp
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mrs_s x\nxtmp, SYS_ZCR_EL1
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bic x\nxtmp, x\nxtmp, ZCR_ELx_LEN_MASK
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orr x\nxtmp, x\nxtmp, \xvqminus1
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msr_s SYS_ZCR_EL1, x\nxtmp // self-synchronising
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_for n, 0, 31, _sve_ldr_v \n, \nxbase, \n - 34
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_sve_ldr_p 0, \nxbase
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_sve_wrffr 0
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_for n, 0, 15, _sve_ldr_p \n, \nxbase, \n - 16
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ldr w\nxtmp, [\xpfpsr]
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msr fpsr, x\nxtmp
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ldr w\nxtmp, [\xpfpsr, #4]
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msr fpcr, x\nxtmp
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.endm
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@ -41,3 +41,20 @@ ENTRY(fpsimd_load_state)
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fpsimd_restore x0, 8
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ret
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ENDPROC(fpsimd_load_state)
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#ifdef CONFIG_ARM64_SVE
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ENTRY(sve_save_state)
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sve_save 0, x1, 2
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ret
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ENDPROC(sve_save_state)
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ENTRY(sve_load_state)
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sve_load 0, x1, x2, 3
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ret
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ENDPROC(sve_load_state)
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ENTRY(sve_get_vl)
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_sve_rdvl 0, 1
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ret
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ENDPROC(sve_get_vl)
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#endif /* CONFIG_ARM64_SVE */
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