drm: dp helper: extract drm_dp_channel_eq_ok
radeon and intel use the exact same definition. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -205,3 +205,53 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
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return error;
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}
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EXPORT_SYMBOL(i2c_dp_aux_add_bus);
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/* Helpers for DP link training */
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static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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{
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_dp_channel_eq_ok);
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
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@ -37,7 +37,6 @@
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#include "i915_drv.h"
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define DP_LINK_STATUS_SIZE 6
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#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
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/**
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@ -1436,13 +1435,6 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_
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DP_LINK_STATUS_SIZE);
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}
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static uint8_t
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intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
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int r)
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{
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static uint8_t
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intel_get_adjust_request_voltage(uint8_t adjust_request[2],
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int lane)
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@ -1728,29 +1720,6 @@ intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count
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return true;
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}
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/* Check to see if channel eq is done on all channels */
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#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
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DP_LANE_CHANNEL_EQ_DONE|\
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DP_LANE_SYMBOL_LOCKED)
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static bool
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intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
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{
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uint8_t lane_align;
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uint8_t lane_status;
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int lane;
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lane_align = intel_dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < intel_dp->lane_count; lane++) {
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lane_status = intel_get_lane_status(link_status, lane);
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if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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static bool
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intel_dp_set_link_train(struct intel_dp *intel_dp,
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uint32_t dp_reg_value,
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@ -2004,7 +1973,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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continue;
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}
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if (intel_channel_eq_ok(intel_dp, link_status)) {
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if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
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channel_eq = true;
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break;
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}
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@ -2223,7 +2192,7 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
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DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
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}
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if (!intel_channel_eq_ok(intel_dp, link_status)) {
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if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
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DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
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drm_get_encoder_name(&intel_dp->base.base));
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intel_dp_start_link_train(intel_dp);
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@ -34,7 +34,6 @@
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/* move these to drm_dp_helper.c/h */
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#define DP_LINK_CONFIGURATION_SIZE 9
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#define DP_LINK_STATUS_SIZE 6
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#define DP_DPCD_SIZE 8
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static char *voltage_names[] = {
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@ -318,25 +317,6 @@ static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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return true;
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}
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static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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u8 lane_align;
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u8 lane_status;
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int lane;
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lane_align = dp_link_status(link_status,
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DP_LANE_ALIGN_STATUS_UPDATED);
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if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
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return false;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
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return false;
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}
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return true;
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}
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static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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@ -664,7 +644,7 @@ bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
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if (!radeon_dp_get_link_status(radeon_connector, link_status))
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return false;
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if (dp_channel_eq_ok(link_status, dig->dp_lane_count))
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if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
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return false;
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return true;
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}
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@ -896,7 +876,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
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break;
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}
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if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
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if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
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channel_eq = true;
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break;
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}
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@ -322,4 +322,9 @@ struct i2c_algo_dp_aux_data {
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int
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i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
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#define DP_LINK_STATUS_SIZE 6
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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#endif /* _DRM_DP_HELPER_H_ */
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