[PATCH] S2io: Code cleanup
Hi, We are submitting a series of 13 patches to support our Xframe I and Xframe II line of products. The patches can be categorized as follows: Patches 1-8 : Changes applicable to both Xframe I and II Patches 9-11: Xframe II specific features Patch 12: Addresses issues found during testing cycle. Patch 13: Incorpoates mostly the review comments from community and some last moment bug fixes. Please review the patches and let us know your comments. Starting with patch 1 below. This patch involves cosmetic changes(tabs and indentation, regrouping of transmit and receive data structures, typecasting, code cleanup). Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com> Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
raghavendra.koushik@neterion.com
Jeff Garzik
parent
cd04b947bc
commit
20346722ec
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@ -77,19 +77,18 @@ typedef struct _XENA_dev_config {
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#define ADAPTER_ECC_EN BIT(55)
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u64 serr_source;
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#define SERR_SOURCE_PIC BIT(0)
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#define SERR_SOURCE_TXDMA BIT(1)
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#define SERR_SOURCE_RXDMA BIT(2)
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#define SERR_SOURCE_PIC BIT(0)
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#define SERR_SOURCE_TXDMA BIT(1)
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#define SERR_SOURCE_RXDMA BIT(2)
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#define SERR_SOURCE_MAC BIT(3)
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#define SERR_SOURCE_MC BIT(4)
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#define SERR_SOURCE_XGXS BIT(5)
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#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
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SERR_SOURCE_TXDMA | \
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SERR_SOURCE_RXDMA | \
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SERR_SOURCE_MAC | \
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SERR_SOURCE_MC | \
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SERR_SOURCE_XGXS)
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#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
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SERR_SOURCE_TXDMA | \
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SERR_SOURCE_RXDMA | \
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SERR_SOURCE_MAC | \
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SERR_SOURCE_MC | \
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SERR_SOURCE_XGXS)
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u8 unused_0[0x800 - 0x120];
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1832
drivers/net/s2io.c
1832
drivers/net/s2io.c
File diff suppressed because it is too large
Load diff
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@ -31,6 +31,9 @@
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#define SUCCESS 0
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#define FAILURE -1
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/* Maximum time to flicker LED when asked to identify NIC using ethtool */
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#define MAX_FLICKER_TIME 60000 /* 60 Secs */
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/* Maximum outstanding splits to be configured into xena. */
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typedef enum xena_max_outstanding_splits {
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XENA_ONE_SPLIT_TRANSACTION = 0,
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@ -45,10 +48,10 @@ typedef enum xena_max_outstanding_splits {
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#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
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/* OS concerned variables and constants */
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#define WATCH_DOG_TIMEOUT 5*HZ
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#define EFILL 0x1234
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#define ALIGN_SIZE 127
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#define PCIX_COMMAND_REGISTER 0x62
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#define WATCH_DOG_TIMEOUT 15*HZ
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#define EFILL 0x1234
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#define ALIGN_SIZE 127
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#define PCIX_COMMAND_REGISTER 0x62
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/*
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* Debug related variables.
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@ -61,7 +64,7 @@ typedef enum xena_max_outstanding_splits {
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#define INTR_DBG 4
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/* Global variable that defines the present debug level of the driver. */
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static int debug_level = ERR_DBG; /* Default level. */
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int debug_level = ERR_DBG; /* Default level. */
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/* DEBUG message print. */
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#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
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@ -71,6 +74,12 @@ static int debug_level = ERR_DBG; /* Default level. */
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#define L4_CKSUM_OK 0xFFFF
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#define S2IO_JUMBO_SIZE 9600
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/* Driver statistics maintained by driver */
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typedef struct {
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unsigned long long single_ecc_errs;
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unsigned long long double_ecc_errs;
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} swStat_t;
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/* The statistics block of Xena */
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typedef struct stat_block {
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/* Tx MAC statistics counters. */
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@ -188,10 +197,26 @@ typedef struct stat_block {
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u32 txf_rd_cnt;
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} StatInfo_t;
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/* Structures representing different init time configuration
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/*
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* Structures representing different init time configuration
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* parameters of the NIC.
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*/
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#define MAX_TX_FIFOS 8
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#define MAX_RX_RINGS 8
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/* FIFO mappings for all possible number of fifos configured */
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int fifo_map[][MAX_TX_FIFOS] = {
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{0, 0, 0, 0, 0, 0, 0, 0},
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{0, 0, 0, 0, 1, 1, 1, 1},
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{0, 0, 0, 1, 1, 1, 2, 2},
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{0, 0, 1, 1, 2, 2, 3, 3},
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{0, 0, 1, 1, 2, 2, 3, 4},
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{0, 0, 1, 1, 2, 3, 4, 5},
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{0, 0, 1, 2, 3, 4, 5, 6},
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{0, 1, 2, 3, 4, 5, 6, 7},
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};
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/* Maintains Per FIFO related information. */
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typedef struct tx_fifo_config {
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#define MAX_AVAILABLE_TXDS 8192
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@ -237,14 +262,14 @@ typedef struct rx_ring_config {
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#define NO_SNOOP_RXD_BUFFER 0x02
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} rx_ring_config_t;
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/* This structure provides contains values of the tunable parameters
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* of the H/W
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/* This structure provides contains values of the tunable parameters
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* of the H/W
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*/
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struct config_param {
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/* Tx Side */
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u32 tx_fifo_num; /*Number of Tx FIFOs */
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#define MAX_TX_FIFOS 8
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u8 fifo_mapping[MAX_TX_FIFOS];
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tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
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u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
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u64 tx_intr_type;
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@ -252,7 +277,6 @@ struct config_param {
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/* Rx Side */
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u32 rx_ring_num; /*Number of receive rings */
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#define MAX_RX_RINGS 8
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#define MAX_RX_BLOCKS_PER_RING 150
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rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
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@ -269,6 +293,7 @@ struct config_param {
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#define MAX_PYLD_JUMBO 9600
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#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
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#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
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u16 bus_speed;
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};
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/* Structure representing MAC Addrs */
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@ -277,7 +302,7 @@ typedef struct mac_addr {
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} macaddr_t;
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/* Structure that represent every FIFO element in the BAR1
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* Address location.
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* Address location.
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*/
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typedef struct _TxFIFO_element {
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u64 TxDL_Pointer;
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@ -339,6 +364,7 @@ typedef struct _RxD_t {
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#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
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#define RXD_FRAME_PROTO_IPV4 BIT(27)
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#define RXD_FRAME_PROTO_IPV6 BIT(28)
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#define RXD_FRAME_IP_FRAG BIT(29)
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#define RXD_FRAME_PROTO_TCP BIT(30)
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#define RXD_FRAME_PROTO_UDP BIT(31)
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#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
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@ -347,10 +373,10 @@ typedef struct _RxD_t {
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u64 Control_2;
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#ifndef CONFIG_2BUFF_MODE
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#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
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#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
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#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
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#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
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#else
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#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16)
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#define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
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#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
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#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
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#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
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@ -363,7 +389,7 @@ typedef struct _RxD_t {
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#define SET_NUM_TAG(val) vBIT(val,16,32)
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#ifndef CONFIG_2BUFF_MODE
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#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
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#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
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#else
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#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
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>> 48)
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@ -382,7 +408,7 @@ typedef struct _RxD_t {
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#endif
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} RxD_t;
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/* Structure that represents the Rx descriptor block which contains
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/* Structure that represents the Rx descriptor block which contains
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* 128 Rx descriptors.
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*/
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#ifndef CONFIG_2BUFF_MODE
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@ -392,11 +418,11 @@ typedef struct _RxD_block {
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u64 reserved_0;
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#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
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u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
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u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
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* Rxd in this blk */
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u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
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u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
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* the upper 32 bits should
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* the upper 32 bits should
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* be 0 */
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} RxD_block_t;
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#else
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@ -405,13 +431,13 @@ typedef struct _RxD_block {
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RxD_t rxd[MAX_RXDS_PER_BLOCK];
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#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
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u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
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u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
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* in this blk */
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u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
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} RxD_block_t;
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#define SIZE_OF_BLOCK 4096
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/* Structure to hold virtual addresses of Buf0 and Buf1 in
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/* Structure to hold virtual addresses of Buf0 and Buf1 in
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* 2buf mode. */
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typedef struct bufAdd {
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void *ba_0_org;
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@ -423,8 +449,8 @@ typedef struct bufAdd {
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/* Structure which stores all the MAC control parameters */
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/* This structure stores the offset of the RxD in the ring
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* from which the Rx Interrupt processor can start picking
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/* This structure stores the offset of the RxD in the ring
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* from which the Rx Interrupt processor can start picking
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* up the RxDs for processing.
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*/
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typedef struct _rx_curr_get_info_t {
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@ -436,7 +462,7 @@ typedef struct _rx_curr_get_info_t {
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typedef rx_curr_get_info_t rx_curr_put_info_t;
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/* This structure stores the offset of the TxDl in the FIFO
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* from which the Tx Interrupt processor can start picking
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* from which the Tx Interrupt processor can start picking
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* up the TxDLs for send complete interrupt processing.
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*/
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typedef struct {
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@ -446,32 +472,96 @@ typedef struct {
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typedef tx_curr_get_info_t tx_curr_put_info_t;
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/* Structure that holds the Phy and virt addresses of the Blocks */
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typedef struct rx_block_info {
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RxD_t *block_virt_addr;
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dma_addr_t block_dma_addr;
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} rx_block_info_t;
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/* pre declaration of the nic structure */
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typedef struct s2io_nic nic_t;
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/* Ring specific structure */
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typedef struct ring_info {
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/* The ring number */
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int ring_no;
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/*
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* Place holders for the virtual and physical addresses of
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* all the Rx Blocks
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*/
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rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
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int block_count;
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int pkt_cnt;
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/*
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* Put pointer info which indictes which RxD has to be replenished
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* with a new buffer.
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*/
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rx_curr_put_info_t rx_curr_put_info;
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/*
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* Get pointer info which indictes which is the last RxD that was
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* processed by the driver.
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*/
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rx_curr_get_info_t rx_curr_get_info;
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#ifndef CONFIG_S2IO_NAPI
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/* Index to the absolute position of the put pointer of Rx ring */
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int put_pos;
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#endif
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#ifdef CONFIG_2BUFF_MODE
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/* Buffer Address store. */
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buffAdd_t **ba;
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#endif
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nic_t *nic;
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} ring_info_t;
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/* Fifo specific structure */
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typedef struct fifo_info {
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/* FIFO number */
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int fifo_no;
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/* Maximum TxDs per TxDL */
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int max_txds;
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/* Place holder of all the TX List's Phy and Virt addresses. */
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list_info_hold_t *list_info;
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/*
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* Current offset within the tx FIFO where driver would write
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* new Tx frame
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*/
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tx_curr_put_info_t tx_curr_put_info;
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/*
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* Current offset within tx FIFO from where the driver would start freeing
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* the buffers
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*/
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tx_curr_get_info_t tx_curr_get_info;
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nic_t *nic;
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}fifo_info_t;
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/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
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* is maintained in this structure.
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*/
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typedef struct mac_info {
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/* rx side stuff */
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/* Put pointer info which indictes which RxD has to be replenished
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* with a new buffer.
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*/
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rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
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/* Get pointer info which indictes which is the last RxD that was
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* processed by the driver.
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*/
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rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
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u16 rmac_pause_time;
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u16 mc_pause_threshold_q0q3;
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u16 mc_pause_threshold_q4q7;
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/* tx side stuff */
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/* logical pointer of start of each Tx FIFO */
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TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
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/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
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tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
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tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
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/* Fifo specific structure */
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fifo_info_t fifos[MAX_TX_FIFOS];
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/* rx side stuff */
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/* Ring specific structure */
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ring_info_t rings[MAX_RX_RINGS];
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u16 rmac_pause_time;
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u16 mc_pause_threshold_q0q3;
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u16 mc_pause_threshold_q4q7;
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void *stats_mem; /* orignal pointer to allocated mem */
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dma_addr_t stats_mem_phy; /* Physical address of the stat block */
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@ -485,12 +575,6 @@ typedef struct {
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int usage_cnt;
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} usr_addr_t;
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/* Structure that holds the Phy and virt addresses of the Blocks */
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typedef struct rx_block_info {
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RxD_t *block_virt_addr;
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dma_addr_t block_dma_addr;
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} rx_block_info_t;
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/* Default Tunable parameters of the NIC. */
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#define DEFAULT_FIFO_LEN 4096
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#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
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@ -499,7 +583,20 @@ typedef struct rx_block_info {
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#define LARGE_BLK_CNT 100
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/* Structure representing one instance of the NIC */
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typedef struct s2io_nic {
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struct s2io_nic {
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#ifdef CONFIG_S2IO_NAPI
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/*
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* Count of packets to be processed in a given iteration, it will be indicated
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* by the quota field of the device structure when NAPI is enabled.
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*/
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int pkts_to_process;
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#endif
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struct net_device *dev;
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mac_info_t mac_control;
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struct config_param config;
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struct pci_dev *pdev;
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void __iomem *bar0;
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void __iomem *bar1;
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#define MAX_MAC_SUPPORTED 16
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#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
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@ -507,33 +604,17 @@ typedef struct s2io_nic {
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macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
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struct net_device_stats stats;
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void __iomem *bar0;
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void __iomem *bar1;
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struct config_param config;
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mac_info_t mac_control;
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int high_dma_flag;
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int device_close_flag;
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int device_enabled_once;
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char name[32];
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char name[50];
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struct tasklet_struct task;
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volatile unsigned long tasklet_status;
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struct timer_list timer;
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struct net_device *dev;
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struct pci_dev *pdev;
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u16 vendor_id;
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u16 device_id;
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u16 ccmd;
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u32 cbar0_1;
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u32 cbar0_2;
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u32 cbar1_1;
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u32 cbar1_2;
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u32 cirq;
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u8 cache_line;
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u32 rom_expansion;
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u16 pcix_cmd;
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u32 irq;
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/* Space to back up the PCI config space */
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u32 config_space[256 / sizeof(u32)];
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atomic_t rx_bufs_left[MAX_RX_RINGS];
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spinlock_t tx_lock;
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@ -558,27 +639,11 @@ typedef struct s2io_nic {
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u16 tx_err_count;
|
||||
u16 rx_err_count;
|
||||
|
||||
#ifndef CONFIG_S2IO_NAPI
|
||||
/* Index to the absolute position of the put pointer of Rx ring. */
|
||||
int put_pos[MAX_RX_RINGS];
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Place holders for the virtual and physical addresses of
|
||||
* all the Rx Blocks
|
||||
*/
|
||||
rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
|
||||
int block_count[MAX_RX_RINGS];
|
||||
int pkt_cnt[MAX_RX_RINGS];
|
||||
|
||||
/* Place holder of all the TX List's Phy and Virt addresses. */
|
||||
list_info_hold_t *list_info[MAX_TX_FIFOS];
|
||||
|
||||
/* Id timer, used to blink NIC to physically identify NIC. */
|
||||
struct timer_list id_timer;
|
||||
|
||||
/* Restart timer, used to restart NIC if the device is stuck and
|
||||
* a schedule task that will set the correct Link state once the
|
||||
* a schedule task that will set the correct Link state once the
|
||||
* NIC's PHY has stabilized after a state change.
|
||||
*/
|
||||
#ifdef INIT_TQUEUE
|
||||
|
|
@ -589,12 +654,12 @@ typedef struct s2io_nic {
|
|||
struct work_struct set_link_task;
|
||||
#endif
|
||||
|
||||
/* Flag that can be used to turn on or turn off the Rx checksum
|
||||
/* Flag that can be used to turn on or turn off the Rx checksum
|
||||
* offload feature.
|
||||
*/
|
||||
int rx_csum;
|
||||
|
||||
/* after blink, the adapter must be restored with original
|
||||
/* after blink, the adapter must be restored with original
|
||||
* values.
|
||||
*/
|
||||
u64 adapt_ctrl_org;
|
||||
|
|
@ -604,16 +669,12 @@ typedef struct s2io_nic {
|
|||
#define LINK_DOWN 1
|
||||
#define LINK_UP 2
|
||||
|
||||
#ifdef CONFIG_2BUFF_MODE
|
||||
/* Buffer Address store. */
|
||||
buffAdd_t **ba[MAX_RX_RINGS];
|
||||
#endif
|
||||
int task_flag;
|
||||
#define CARD_DOWN 1
|
||||
#define CARD_UP 2
|
||||
atomic_t card_state;
|
||||
volatile unsigned long link_state;
|
||||
} nic_t;
|
||||
};
|
||||
|
||||
#define RESET_ERROR 1;
|
||||
#define CMD_ERROR 2;
|
||||
|
|
@ -622,9 +683,10 @@ typedef struct s2io_nic {
|
|||
#ifndef readq
|
||||
static inline u64 readq(void __iomem *addr)
|
||||
{
|
||||
u64 ret = readl(addr + 4);
|
||||
ret <<= 32;
|
||||
ret |= readl(addr);
|
||||
u64 ret = 0;
|
||||
ret = readl(addr + 4);
|
||||
(u64) ret <<= 32;
|
||||
(u64) ret |= readl(addr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -637,10 +699,10 @@ static inline void writeq(u64 val, void __iomem *addr)
|
|||
writel((u32) (val >> 32), (addr + 4));
|
||||
}
|
||||
|
||||
/* In 32 bit modes, some registers have to be written in a
|
||||
/* In 32 bit modes, some registers have to be written in a
|
||||
* particular order to expect correct hardware operation. The
|
||||
* macro SPECIAL_REG_WRITE is used to perform such ordered
|
||||
* writes. Defines UF (Upper First) and LF (Lower First) will
|
||||
* macro SPECIAL_REG_WRITE is used to perform such ordered
|
||||
* writes. Defines UF (Upper First) and LF (Lower First) will
|
||||
* be used to specify the required write order.
|
||||
*/
|
||||
#define UF 1
|
||||
|
|
@ -716,6 +778,7 @@ static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
|
|||
#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
|
||||
PCC_FB_ECC Error. */
|
||||
|
||||
#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
|
||||
/*
|
||||
* Prototype declaration.
|
||||
*/
|
||||
|
|
@ -725,36 +788,29 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev);
|
|||
static int init_shared_mem(struct s2io_nic *sp);
|
||||
static void free_shared_mem(struct s2io_nic *sp);
|
||||
static int init_nic(struct s2io_nic *nic);
|
||||
#ifndef CONFIG_S2IO_NAPI
|
||||
static void rx_intr_handler(struct s2io_nic *sp);
|
||||
#endif
|
||||
static void tx_intr_handler(struct s2io_nic *sp);
|
||||
static void rx_intr_handler(ring_info_t *ring_data);
|
||||
static void tx_intr_handler(fifo_info_t *fifo_data);
|
||||
static void alarm_intr_handler(struct s2io_nic *sp);
|
||||
|
||||
static int s2io_starter(void);
|
||||
static void s2io_closer(void);
|
||||
void s2io_closer(void);
|
||||
static void s2io_tx_watchdog(struct net_device *dev);
|
||||
static void s2io_tasklet(unsigned long dev_addr);
|
||||
static void s2io_set_multicast(struct net_device *dev);
|
||||
#ifndef CONFIG_2BUFF_MODE
|
||||
static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
|
||||
#else
|
||||
static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
|
||||
buffAdd_t * ba);
|
||||
#endif
|
||||
static void s2io_link(nic_t * sp, int link);
|
||||
static void s2io_reset(nic_t * sp);
|
||||
#ifdef CONFIG_S2IO_NAPI
|
||||
static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
|
||||
void s2io_link(nic_t * sp, int link);
|
||||
void s2io_reset(nic_t * sp);
|
||||
#if defined(CONFIG_S2IO_NAPI)
|
||||
static int s2io_poll(struct net_device *dev, int *budget);
|
||||
#endif
|
||||
static void s2io_init_pci(nic_t * sp);
|
||||
static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
|
||||
int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
|
||||
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
|
||||
static int verify_xena_quiescence(u64 val64, int flag);
|
||||
static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
|
||||
static struct ethtool_ops netdev_ethtool_ops;
|
||||
static void s2io_set_link(unsigned long data);
|
||||
static int s2io_set_swapper(nic_t * sp);
|
||||
static void s2io_card_down(nic_t * nic);
|
||||
static int s2io_card_up(nic_t * nic);
|
||||
|
||||
int s2io_set_swapper(nic_t * sp);
|
||||
static void s2io_card_down(nic_t *nic);
|
||||
static int s2io_card_up(nic_t *nic);
|
||||
int get_xena_rev_id(struct pci_dev *pdev);
|
||||
#endif /* _S2IO_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue