pinctrl: sh-pfc: r8a7795: Add SDHI support
Add SDHI[0-3] pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>steinar/wifi_calib_4_9_kernel
Takeshi Kihara
Geert Uytterhoeven
parent
ed66700c03
commit
20cacae155
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@ -2674,6 +2674,212 @@ static const unsigned int scif5_clk_pins[] = {
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static const unsigned int scif5_clk_mux[] = {
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SCK5_MARK,
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};
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/* - SDHI0 ------------------------------------------------------------------ */
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static const unsigned int sdhi0_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(3, 2),
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};
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static const unsigned int sdhi0_data1_mux[] = {
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SD0_DAT0_MARK,
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};
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static const unsigned int sdhi0_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
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RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
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};
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static const unsigned int sdhi0_data4_mux[] = {
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SD0_DAT0_MARK, SD0_DAT1_MARK,
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SD0_DAT2_MARK, SD0_DAT3_MARK,
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};
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static const unsigned int sdhi0_ctrl_pins[] = {
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/* CLK, CMD */
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RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
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};
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static const unsigned int sdhi0_ctrl_mux[] = {
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SD0_CLK_MARK, SD0_CMD_MARK,
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};
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static const unsigned int sdhi0_cd_pins[] = {
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/* CD */
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RCAR_GP_PIN(3, 12),
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};
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static const unsigned int sdhi0_cd_mux[] = {
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SD0_CD_MARK,
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};
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static const unsigned int sdhi0_wp_pins[] = {
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/* WP */
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RCAR_GP_PIN(3, 13),
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};
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static const unsigned int sdhi0_wp_mux[] = {
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SD0_WP_MARK,
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};
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/* - SDHI1 ------------------------------------------------------------------ */
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static const unsigned int sdhi1_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(3, 8),
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};
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static const unsigned int sdhi1_data1_mux[] = {
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SD1_DAT0_MARK,
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};
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static const unsigned int sdhi1_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
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RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
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};
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static const unsigned int sdhi1_data4_mux[] = {
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SD1_DAT0_MARK, SD1_DAT1_MARK,
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SD1_DAT2_MARK, SD1_DAT3_MARK,
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};
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static const unsigned int sdhi1_ctrl_pins[] = {
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/* CLK, CMD */
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RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
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};
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static const unsigned int sdhi1_ctrl_mux[] = {
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SD1_CLK_MARK, SD1_CMD_MARK,
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};
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static const unsigned int sdhi1_cd_pins[] = {
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/* CD */
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RCAR_GP_PIN(3, 14),
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};
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static const unsigned int sdhi1_cd_mux[] = {
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SD1_CD_MARK,
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};
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static const unsigned int sdhi1_wp_pins[] = {
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/* WP */
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RCAR_GP_PIN(3, 15),
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};
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static const unsigned int sdhi1_wp_mux[] = {
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SD1_WP_MARK,
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};
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/* - SDHI2 ------------------------------------------------------------------ */
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static const unsigned int sdhi2_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(4, 2),
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};
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static const unsigned int sdhi2_data1_mux[] = {
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SD2_DAT0_MARK,
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};
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static const unsigned int sdhi2_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
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RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
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};
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static const unsigned int sdhi2_data4_mux[] = {
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SD2_DAT0_MARK, SD2_DAT1_MARK,
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SD2_DAT2_MARK, SD2_DAT3_MARK,
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};
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static const unsigned int sdhi2_data8_pins[] = {
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/* D[0:7] */
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RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
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RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
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RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
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RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
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};
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static const unsigned int sdhi2_data8_mux[] = {
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SD2_DAT0_MARK, SD2_DAT1_MARK,
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SD2_DAT2_MARK, SD2_DAT3_MARK,
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SD2_DAT4_MARK, SD2_DAT5_MARK,
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SD2_DAT6_MARK, SD2_DAT7_MARK,
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};
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static const unsigned int sdhi2_ctrl_pins[] = {
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/* CLK, CMD */
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RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
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};
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static const unsigned int sdhi2_ctrl_mux[] = {
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SD2_CLK_MARK, SD2_CMD_MARK,
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};
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static const unsigned int sdhi2_cd_a_pins[] = {
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/* CD */
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RCAR_GP_PIN(4, 13),
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};
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static const unsigned int sdhi2_cd_a_mux[] = {
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SD2_CD_A_MARK,
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};
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static const unsigned int sdhi2_cd_b_pins[] = {
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/* CD */
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RCAR_GP_PIN(5, 10),
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};
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static const unsigned int sdhi2_cd_b_mux[] = {
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SD2_CD_B_MARK,
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};
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static const unsigned int sdhi2_wp_a_pins[] = {
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/* WP */
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RCAR_GP_PIN(4, 14),
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};
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static const unsigned int sdhi2_wp_a_mux[] = {
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SD2_WP_A_MARK,
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};
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static const unsigned int sdhi2_wp_b_pins[] = {
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/* WP */
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RCAR_GP_PIN(5, 11),
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};
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static const unsigned int sdhi2_wp_b_mux[] = {
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SD2_WP_B_MARK,
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};
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static const unsigned int sdhi2_ds_pins[] = {
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/* DS */
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RCAR_GP_PIN(4, 6),
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};
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static const unsigned int sdhi2_ds_mux[] = {
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SD2_DS_MARK,
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};
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/* - SDHI3 ------------------------------------------------------------------ */
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static const unsigned int sdhi3_data1_pins[] = {
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/* D0 */
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RCAR_GP_PIN(4, 9),
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};
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static const unsigned int sdhi3_data1_mux[] = {
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SD3_DAT0_MARK,
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};
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static const unsigned int sdhi3_data4_pins[] = {
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/* D[0:3] */
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RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
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RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
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};
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static const unsigned int sdhi3_data4_mux[] = {
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SD3_DAT0_MARK, SD3_DAT1_MARK,
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SD3_DAT2_MARK, SD3_DAT3_MARK,
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};
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static const unsigned int sdhi3_data8_pins[] = {
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/* D[0:7] */
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RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
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RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
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RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
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RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
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};
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static const unsigned int sdhi3_data8_mux[] = {
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SD3_DAT0_MARK, SD3_DAT1_MARK,
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SD3_DAT2_MARK, SD3_DAT3_MARK,
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SD3_DAT4_MARK, SD3_DAT5_MARK,
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SD3_DAT6_MARK, SD3_DAT7_MARK,
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};
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static const unsigned int sdhi3_ctrl_pins[] = {
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/* CLK, CMD */
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RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
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};
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static const unsigned int sdhi3_ctrl_mux[] = {
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SD3_CLK_MARK, SD3_CMD_MARK,
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};
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static const unsigned int sdhi3_cd_pins[] = {
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/* CD */
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RCAR_GP_PIN(4, 15),
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};
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static const unsigned int sdhi3_cd_mux[] = {
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SD3_CD_MARK,
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};
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static const unsigned int sdhi3_wp_pins[] = {
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/* WP */
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RCAR_GP_PIN(4, 16),
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};
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static const unsigned int sdhi3_wp_mux[] = {
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SD3_WP_MARK,
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};
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static const unsigned int sdhi3_ds_pins[] = {
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/* DS */
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RCAR_GP_PIN(4, 17),
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};
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static const unsigned int sdhi3_ds_mux[] = {
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SD3_DS_MARK,
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};
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/* - SCIF Clock ------------------------------------------------------------- */
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static const unsigned int scif_clk_a_pins[] = {
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@ -3047,6 +3253,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(scif5_clk),
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SH_PFC_PIN_GROUP(scif_clk_a),
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SH_PFC_PIN_GROUP(scif_clk_b),
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SH_PFC_PIN_GROUP(sdhi0_data1),
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SH_PFC_PIN_GROUP(sdhi0_data4),
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SH_PFC_PIN_GROUP(sdhi0_ctrl),
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SH_PFC_PIN_GROUP(sdhi0_cd),
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SH_PFC_PIN_GROUP(sdhi0_wp),
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SH_PFC_PIN_GROUP(sdhi1_data1),
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SH_PFC_PIN_GROUP(sdhi1_data4),
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SH_PFC_PIN_GROUP(sdhi1_ctrl),
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SH_PFC_PIN_GROUP(sdhi1_cd),
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SH_PFC_PIN_GROUP(sdhi1_wp),
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SH_PFC_PIN_GROUP(sdhi2_data1),
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SH_PFC_PIN_GROUP(sdhi2_data4),
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SH_PFC_PIN_GROUP(sdhi2_data8),
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SH_PFC_PIN_GROUP(sdhi2_ctrl),
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SH_PFC_PIN_GROUP(sdhi2_cd_a),
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SH_PFC_PIN_GROUP(sdhi2_wp_a),
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SH_PFC_PIN_GROUP(sdhi2_cd_b),
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SH_PFC_PIN_GROUP(sdhi2_wp_b),
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SH_PFC_PIN_GROUP(sdhi2_ds),
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SH_PFC_PIN_GROUP(sdhi3_data1),
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SH_PFC_PIN_GROUP(sdhi3_data4),
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SH_PFC_PIN_GROUP(sdhi3_data8),
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SH_PFC_PIN_GROUP(sdhi3_ctrl),
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SH_PFC_PIN_GROUP(sdhi3_cd),
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SH_PFC_PIN_GROUP(sdhi3_wp),
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SH_PFC_PIN_GROUP(sdhi3_ds),
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SH_PFC_PIN_GROUP(ssi0_data),
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SH_PFC_PIN_GROUP(ssi01239_ctrl),
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SH_PFC_PIN_GROUP(ssi1_data_a),
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@ -3315,6 +3547,44 @@ static const char * const scif_clk_groups[] = {
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"scif_clk_b",
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};
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static const char * const sdhi0_groups[] = {
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"sdhi0_data1",
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"sdhi0_data4",
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"sdhi0_ctrl",
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"sdhi0_cd",
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"sdhi0_wp",
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};
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static const char * const sdhi1_groups[] = {
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"sdhi1_data1",
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"sdhi1_data4",
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"sdhi1_ctrl",
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"sdhi1_cd",
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"sdhi1_wp",
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};
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static const char * const sdhi2_groups[] = {
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"sdhi2_data1",
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"sdhi2_data4",
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"sdhi2_data8",
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"sdhi2_ctrl",
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"sdhi2_cd_a",
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"sdhi2_wp_a",
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"sdhi2_cd_b",
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"sdhi2_wp_b",
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"sdhi2_ds",
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};
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static const char * const sdhi3_groups[] = {
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"sdhi3_data1",
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"sdhi3_data4",
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"sdhi3_data8",
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"sdhi3_ctrl",
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"sdhi3_cd",
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"sdhi3_wp",
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"sdhi3_ds",
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};
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static const char * const ssi_groups[] = {
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"ssi0_data",
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"ssi01239_ctrl",
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@ -3365,6 +3635,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(scif4),
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SH_PFC_FUNCTION(scif5),
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SH_PFC_FUNCTION(scif_clk),
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SH_PFC_FUNCTION(sdhi0),
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SH_PFC_FUNCTION(sdhi1),
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SH_PFC_FUNCTION(sdhi2),
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SH_PFC_FUNCTION(sdhi3),
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SH_PFC_FUNCTION(ssi),
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};
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