intel_mid_dma: change the slave interface
In 2.6.36 kernel, dma slave control command was introduced, this patch changes the intel-mid-dma driver to this new kernel slave interface Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Koul, Vinod
Dan Williams
parent
8b6492231d
commit
20dd63900d
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@ -92,13 +92,13 @@ static int get_block_ts(int len, int tx_width, int block_size)
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int byte_width = 0, block_ts = 0;
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switch (tx_width) {
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case LNW_DMA_WIDTH_8BIT:
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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byte_width = 1;
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break;
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case LNW_DMA_WIDTH_16BIT:
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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byte_width = 2;
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break;
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case LNW_DMA_WIDTH_32BIT:
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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default:
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byte_width = 4;
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break;
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@ -367,7 +367,7 @@ static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
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int i;
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pr_debug("MDMA: Entered midc_lli_fill_sg\n");
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mids = midc->chan.private;
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mids = midc->mid_slave;
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lli_bloc_desc = desc->lli;
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lli_next = desc->lli_phys;
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@ -398,9 +398,9 @@ static int midc_lli_fill_sg(struct intel_mid_dma_chan *midc,
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sg_phy_addr = sg_phys(sg);
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if (desc->dirn == DMA_TO_DEVICE) {
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lli_bloc_desc->sar = sg_phy_addr;
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lli_bloc_desc->dar = mids->per_addr;
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lli_bloc_desc->dar = mids->dma_slave.dst_addr;
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} else if (desc->dirn == DMA_FROM_DEVICE) {
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lli_bloc_desc->sar = mids->per_addr;
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lli_bloc_desc->sar = mids->dma_slave.src_addr;
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lli_bloc_desc->dar = sg_phy_addr;
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}
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/*Copy values into block descriptor in system memroy*/
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@ -507,6 +507,23 @@ static enum dma_status intel_mid_dma_tx_status(struct dma_chan *chan,
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return ret;
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}
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static int dma_slave_control(struct dma_chan *chan, unsigned long arg)
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{
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struct intel_mid_dma_chan *midc = to_intel_mid_dma_chan(chan);
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struct dma_slave_config *slave = (struct dma_slave_config *)arg;
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struct intel_mid_dma_slave *mid_slave;
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BUG_ON(!midc);
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BUG_ON(!slave);
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pr_debug("MDMA: slave control called\n");
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mid_slave = to_intel_mid_dma_slave(slave);
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BUG_ON(!mid_slave);
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midc->mid_slave = mid_slave;
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return 0;
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}
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/**
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* intel_mid_dma_device_control - DMA device control
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* @chan: chan for DMA control
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@ -523,6 +540,9 @@ static int intel_mid_dma_device_control(struct dma_chan *chan,
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struct intel_mid_dma_desc *desc, *_desc;
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union intel_mid_dma_cfg_lo cfg_lo;
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if (cmd == DMA_SLAVE_CONFIG)
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return dma_slave_control(chan, arg);
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if (cmd != DMA_TERMINATE_ALL)
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return -ENXIO;
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@ -540,7 +560,6 @@ static int intel_mid_dma_device_control(struct dma_chan *chan,
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/* Disable interrupts */
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disable_dma_interrupt(midc);
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midc->descs_allocated = 0;
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midc->slave = NULL;
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spin_unlock_bh(&midc->lock);
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list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) {
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@ -578,23 +597,24 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
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union intel_mid_dma_ctl_hi ctl_hi;
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union intel_mid_dma_cfg_lo cfg_lo;
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union intel_mid_dma_cfg_hi cfg_hi;
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enum intel_mid_dma_width width = 0;
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enum dma_slave_buswidth width;
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pr_debug("MDMA: Prep for memcpy\n");
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BUG_ON(!chan);
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if (!len)
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return NULL;
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mids = chan->private;
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BUG_ON(!mids);
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midc = to_intel_mid_dma_chan(chan);
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BUG_ON(!midc);
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mids = midc->mid_slave;
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BUG_ON(!mids);
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pr_debug("MDMA:called for DMA %x CH %d Length %zu\n",
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midc->dma->pci_id, midc->ch_id, len);
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pr_debug("MDMA:Cfg passed Mode %x, Dirn %x, HS %x, Width %x\n",
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mids->cfg_mode, mids->dirn, mids->hs_mode, mids->src_width);
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mids->cfg_mode, mids->dma_slave.direction,
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mids->hs_mode, mids->dma_slave.src_addr_width);
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/*calculate CFG_LO*/
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if (mids->hs_mode == LNW_DMA_SW_HS) {
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@ -613,13 +633,13 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
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if (midc->dma->pimr_mask) {
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cfg_hi.cfgx.protctl = 0x0; /*default value*/
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cfg_hi.cfgx.fifo_mode = 1;
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if (mids->dirn == DMA_TO_DEVICE) {
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if (mids->dma_slave.direction == DMA_TO_DEVICE) {
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cfg_hi.cfgx.src_per = 0;
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if (mids->device_instance == 0)
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cfg_hi.cfgx.dst_per = 3;
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if (mids->device_instance == 1)
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cfg_hi.cfgx.dst_per = 1;
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} else if (mids->dirn == DMA_FROM_DEVICE) {
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} else if (mids->dma_slave.direction == DMA_FROM_DEVICE) {
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if (mids->device_instance == 0)
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cfg_hi.cfgx.src_per = 2;
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if (mids->device_instance == 1)
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@ -636,7 +656,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
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/*calculate CTL_HI*/
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ctl_hi.ctlx.reser = 0;
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ctl_hi.ctlx.done = 0;
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width = mids->src_width;
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width = mids->dma_slave.src_addr_width;
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ctl_hi.ctlx.block_ts = get_block_ts(len, width, midc->dma->block_size);
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pr_debug("MDMA:calc len %d for block size %d\n",
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@ -644,21 +664,21 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
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/*calculate CTL_LO*/
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ctl_lo.ctl_lo = 0;
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ctl_lo.ctlx.int_en = 1;
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ctl_lo.ctlx.dst_tr_width = mids->dst_width;
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ctl_lo.ctlx.src_tr_width = mids->src_width;
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ctl_lo.ctlx.dst_msize = mids->src_msize;
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ctl_lo.ctlx.src_msize = mids->dst_msize;
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ctl_lo.ctlx.dst_tr_width = mids->dma_slave.dst_addr_width;
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ctl_lo.ctlx.src_tr_width = mids->dma_slave.src_addr_width;
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ctl_lo.ctlx.dst_msize = mids->dma_slave.src_maxburst;
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ctl_lo.ctlx.src_msize = mids->dma_slave.dst_maxburst;
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if (mids->cfg_mode == LNW_DMA_MEM_TO_MEM) {
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ctl_lo.ctlx.tt_fc = 0;
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ctl_lo.ctlx.sinc = 0;
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ctl_lo.ctlx.dinc = 0;
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} else {
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if (mids->dirn == DMA_TO_DEVICE) {
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if (mids->dma_slave.direction == DMA_TO_DEVICE) {
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ctl_lo.ctlx.sinc = 0;
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ctl_lo.ctlx.dinc = 2;
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ctl_lo.ctlx.tt_fc = 1;
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} else if (mids->dirn == DMA_FROM_DEVICE) {
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} else if (mids->dma_slave.direction == DMA_FROM_DEVICE) {
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ctl_lo.ctlx.sinc = 2;
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ctl_lo.ctlx.dinc = 0;
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ctl_lo.ctlx.tt_fc = 2;
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@ -681,7 +701,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_memcpy(
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desc->ctl_lo = ctl_lo.ctl_lo;
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desc->ctl_hi = ctl_hi.ctl_hi;
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desc->width = width;
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desc->dirn = mids->dirn;
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desc->dirn = mids->dma_slave.direction;
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desc->lli_phys = 0;
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desc->lli = NULL;
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desc->lli_pool = NULL;
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@ -722,7 +742,7 @@ static struct dma_async_tx_descriptor *intel_mid_dma_prep_slave_sg(
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midc = to_intel_mid_dma_chan(chan);
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BUG_ON(!midc);
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mids = chan->private;
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mids = midc->mid_slave;
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BUG_ON(!mids);
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if (!midc->dma->pimr_mask) {
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@ -187,13 +187,13 @@ struct intel_mid_dma_chan {
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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struct intel_mid_dma_slave *slave;
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unsigned int descs_allocated;
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struct middma_device *dma;
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bool busy;
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bool in_use;
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u32 raw_tfr;
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u32 raw_block;
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struct intel_mid_dma_slave *mid_slave;
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};
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static inline struct intel_mid_dma_chan *to_intel_mid_dma_chan(
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@ -264,7 +264,7 @@ struct intel_mid_dma_desc {
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dma_addr_t next;
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enum dma_data_direction dirn;
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enum dma_status status;
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enum intel_mid_dma_width width; /*width of DMA txn*/
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enum dma_slave_buswidth width; /*width of DMA txn*/
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enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
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};
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@ -289,6 +289,13 @@ static inline struct intel_mid_dma_desc *to_intel_mid_dma_desc
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return container_of(txd, struct intel_mid_dma_desc, txd);
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}
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static inline struct intel_mid_dma_slave *to_intel_mid_dma_slave
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(struct dma_slave_config *slave)
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{
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return container_of(slave, struct intel_mid_dma_slave, dma_slave);
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}
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int dma_resume(struct pci_dev *pci);
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#endif /*__INTEL_MID_DMAC_REGS_H__*/
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@ -28,14 +28,6 @@
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#include <linux/dmaengine.h>
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#define DMA_PREP_CIRCULAR_LIST (1 << 10)
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/*DMA transaction width, src and dstn width would be same
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The DMA length must be width aligned,
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for 32 bit width the length must be 32 bit (4bytes) aligned only*/
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enum intel_mid_dma_width {
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LNW_DMA_WIDTH_8BIT = 0x0,
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LNW_DMA_WIDTH_16BIT = 0x1,
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LNW_DMA_WIDTH_32BIT = 0x2,
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};
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/*DMA mode configurations*/
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enum intel_mid_dma_mode {
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@ -75,15 +67,10 @@ enum intel_mid_dma_msize {
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* peripheral device connected to single DMAC
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*/
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struct intel_mid_dma_slave {
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enum dma_data_direction dirn;
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enum intel_mid_dma_width src_width; /*width of DMA src txn*/
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enum intel_mid_dma_width dst_width; /*width of DMA dst txn*/
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enum intel_mid_dma_hs_mode hs_mode; /*handshaking*/
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enum intel_mid_dma_mode cfg_mode; /*mode configuration*/
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enum intel_mid_dma_msize src_msize; /*size if src burst*/
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enum intel_mid_dma_msize dst_msize; /*size of dst burst*/
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dma_addr_t per_addr; /*Peripheral address*/
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unsigned int device_instance; /*0, 1 for periphral instance*/
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struct dma_slave_config dma_slave;
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};
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#endif /*__INTEL_MID_DMA_H__*/
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