MIPS: memset.S: Reinstate delay slot indentation
Assembly language within the MIPS kernel conventionally indents
instructions which are in a branch delay slot to make them easier to
see. Commit 8483b14aaa
("MIPS: lib: memset: Whitespace fixes") rather
inexplicably removed all of these indentations from memset.S. Reinstate
the convention for all instructions in a branch delay slot. This
effectively reverts the above commit, plus other locations introduced
with MIPSR6 support.
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/19111/
Signed-off-by: James Hogan <jhogan@kernel.org>
This commit is contained in:
parent
84002c8859
commit
21325631f3
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@ -95,7 +95,7 @@
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sltiu t0, a2, STORSIZE /* very small region? */
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bnez t0, .Lsmall_memset\@
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andi t0, a0, STORMASK /* aligned? */
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andi t0, a0, STORMASK /* aligned? */
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#ifdef CONFIG_CPU_MICROMIPS
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move t8, a1 /* used by 'swp' instruction */
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@ -103,12 +103,12 @@
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#endif
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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beqz t0, 1f
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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PTR_SUBU t0, STORSIZE /* alignment in bytes */
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#else
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.set noat
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li AT, STORSIZE
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beqz t0, 1f
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PTR_SUBU t0, AT /* alignment in bytes */
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PTR_SUBU t0, AT /* alignment in bytes */
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.set at
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#endif
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@ -149,7 +149,7 @@
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1: ori t1, a2, 0x3f /* # of full blocks */
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xori t1, 0x3f
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beqz t1, .Lmemset_partial\@ /* no block to fill */
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andi t0, a2, 0x40-STORSIZE
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andi t0, a2, 0x40-STORSIZE
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PTR_ADDU t1, a0 /* end address */
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.set reorder
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@ -174,7 +174,7 @@
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.set at
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#endif
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jr t1
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PTR_ADDU a0, t0 /* dest ptr */
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PTR_ADDU a0, t0 /* dest ptr */
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.set push
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.set noreorder
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@ -186,7 +186,7 @@
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beqz a2, 1f
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#ifndef CONFIG_CPU_MIPSR6
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PTR_ADDU a0, a2 /* What's left */
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PTR_ADDU a0, a2 /* What's left */
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R10KCBARRIER(0(ra))
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#ifdef __MIPSEB__
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EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
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@ -194,7 +194,7 @@
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EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
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#endif
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#else
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PTR_SUBU t0, $0, a2
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PTR_SUBU t0, $0, a2
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PTR_ADDIU t0, 1
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STORE_BYTE(0)
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STORE_BYTE(1)
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@ -210,11 +210,11 @@
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0:
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#endif
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1: jr ra
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move a2, zero
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move a2, zero
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.Lsmall_memset\@:
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beqz a2, 2f
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PTR_ADDU t1, a0, a2
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PTR_ADDU t1, a0, a2
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1: PTR_ADDIU a0, 1 /* fill bytewise */
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R10KCBARRIER(0(ra))
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@ -222,7 +222,7 @@
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EX(sb, a1, -1(a0), .Lsmall_fixup\@)
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2: jr ra /* done */
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move a2, zero
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move a2, zero
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.if __memset == 1
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END(memset)
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.set __memset, 0
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@ -238,7 +238,7 @@
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.Lfirst_fixup\@:
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jr ra
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nop
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nop
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.Lfwd_fixup\@:
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PTR_L t0, TI_TASK($28)
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@ -246,7 +246,7 @@
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, t1
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jr ra
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LONG_SUBU a2, t0
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LONG_SUBU a2, t0
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.Lpartial_fixup\@:
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PTR_L t0, TI_TASK($28)
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@ -254,7 +254,7 @@
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LONG_L t0, THREAD_BUADDR(t0)
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LONG_ADDU a2, a0
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jr ra
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LONG_SUBU a2, t0
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LONG_SUBU a2, t0
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.Llast_fixup\@:
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jr ra
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@ -278,7 +278,7 @@
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LEAF(memset)
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EXPORT_SYMBOL(memset)
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beqz a1, 1f
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move v0, a0 /* result */
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move v0, a0 /* result */
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andi a1, 0xff /* spread fillword */
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LONG_SLL t1, a1, 8
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