[SCSI] a3000: Reindentation
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: James Bottomley <James.Bottomley@suse.de>wifi-calibration
Geert Uytterhoeven
James Bottomley
parent
be4540db06
commit
2135101340
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@ -19,26 +19,26 @@
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#include "wd33c93.h"
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#include "a3000.h"
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#include<linux/stat.h>
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#include <linux/stat.h>
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#define DMA(ptr) ((a3000_scsiregs *)((ptr)->base))
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#define HDATA(ptr) ((struct WD33C93_hostdata *)((ptr)->hostdata))
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#define DMA(ptr) ((a3000_scsiregs *)((ptr)->base))
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#define HDATA(ptr) ((struct WD33C93_hostdata *)((ptr)->hostdata))
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static struct Scsi_Host *a3000_host = NULL;
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static int a3000_release(struct Scsi_Host *instance);
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static irqreturn_t a3000_intr (int irq, void *dummy)
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static irqreturn_t a3000_intr(int irq, void *dummy)
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{
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unsigned long flags;
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unsigned int status = DMA(a3000_host)->ISTR;
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if (!(status & ISTR_INT_P))
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return IRQ_NONE;
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if (status & ISTR_INTS)
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{
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if (status & ISTR_INTS) {
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spin_lock_irqsave(a3000_host->host_lock, flags);
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wd33c93_intr (a3000_host);
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wd33c93_intr(a3000_host);
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spin_unlock_irqrestore(a3000_host->host_lock, flags);
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return IRQ_HANDLED;
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}
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@ -48,161 +48,161 @@ static irqreturn_t a3000_intr (int irq, void *dummy)
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static int dma_setup(struct scsi_cmnd *cmd, int dir_in)
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{
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unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
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unsigned long addr = virt_to_bus(cmd->SCp.ptr);
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unsigned short cntr = CNTR_PDMD | CNTR_INTEN;
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unsigned long addr = virt_to_bus(cmd->SCp.ptr);
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/*
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* if the physical address has the wrong alignment, or if
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* physical address is bad, or if it is a write and at the
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* end of a physical memory chunk, then allocate a bounce
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* buffer
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*/
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if (addr & A3000_XFER_MASK)
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{
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HDATA(a3000_host)->dma_bounce_len = (cmd->SCp.this_residual + 511)
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& ~0x1ff;
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HDATA(a3000_host)->dma_bounce_buffer =
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kmalloc (HDATA(a3000_host)->dma_bounce_len, GFP_KERNEL);
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/* can't allocate memory; use PIO */
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if (!HDATA(a3000_host)->dma_bounce_buffer) {
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HDATA(a3000_host)->dma_bounce_len = 0;
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return 1;
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/*
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* if the physical address has the wrong alignment, or if
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* physical address is bad, or if it is a write and at the
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* end of a physical memory chunk, then allocate a bounce
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* buffer
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*/
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if (addr & A3000_XFER_MASK) {
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HDATA(a3000_host)->dma_bounce_len =
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(cmd->SCp.this_residual + 511) & ~0x1ff;
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HDATA(a3000_host)->dma_bounce_buffer =
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kmalloc(HDATA(a3000_host)->dma_bounce_len, GFP_KERNEL);
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/* can't allocate memory; use PIO */
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if (!HDATA(a3000_host)->dma_bounce_buffer) {
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HDATA(a3000_host)->dma_bounce_len = 0;
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return 1;
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}
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if (!dir_in) {
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/* copy to bounce buffer for a write */
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memcpy(HDATA(a3000_host)->dma_bounce_buffer,
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cmd->SCp.ptr, cmd->SCp.this_residual);
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}
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addr = virt_to_bus(HDATA(a3000_host)->dma_bounce_buffer);
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}
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if (!dir_in) {
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/* copy to bounce buffer for a write */
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memcpy (HDATA(a3000_host)->dma_bounce_buffer,
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cmd->SCp.ptr, cmd->SCp.this_residual);
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/* setup dma direction */
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if (!dir_in)
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cntr |= CNTR_DDIR;
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/* remember direction */
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HDATA(a3000_host)->dma_dir = dir_in;
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DMA(a3000_host)->CNTR = cntr;
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/* setup DMA *physical* address */
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DMA(a3000_host)->ACR = addr;
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if (dir_in) {
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/* invalidate any cache */
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cache_clear(addr, cmd->SCp.this_residual);
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} else {
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/* push any dirty cache */
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cache_push(addr, cmd->SCp.this_residual);
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}
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addr = virt_to_bus(HDATA(a3000_host)->dma_bounce_buffer);
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}
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/* start DMA */
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mb(); /* make sure setup is completed */
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DMA(a3000_host)->ST_DMA = 1;
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mb(); /* make sure DMA has started before next IO */
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/* setup dma direction */
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if (!dir_in)
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cntr |= CNTR_DDIR;
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/* remember direction */
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HDATA(a3000_host)->dma_dir = dir_in;
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DMA(a3000_host)->CNTR = cntr;
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/* setup DMA *physical* address */
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DMA(a3000_host)->ACR = addr;
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if (dir_in)
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/* invalidate any cache */
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cache_clear (addr, cmd->SCp.this_residual);
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else
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/* push any dirty cache */
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cache_push (addr, cmd->SCp.this_residual);
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/* start DMA */
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mb(); /* make sure setup is completed */
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DMA(a3000_host)->ST_DMA = 1;
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mb(); /* make sure DMA has started before next IO */
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/* return success */
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return 0;
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/* return success */
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return 0;
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}
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static void dma_stop(struct Scsi_Host *instance, struct scsi_cmnd *SCpnt,
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int status)
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{
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/* disable SCSI interrupts */
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unsigned short cntr = CNTR_PDMD;
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/* disable SCSI interrupts */
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unsigned short cntr = CNTR_PDMD;
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if (!HDATA(instance)->dma_dir)
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cntr |= CNTR_DDIR;
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if (!HDATA(instance)->dma_dir)
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cntr |= CNTR_DDIR;
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DMA(instance)->CNTR = cntr;
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mb(); /* make sure CNTR is updated before next IO */
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DMA(instance)->CNTR = cntr;
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mb(); /* make sure CNTR is updated before next IO */
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/* flush if we were reading */
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if (HDATA(instance)->dma_dir) {
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DMA(instance)->FLUSH = 1;
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mb(); /* don't allow prefetch */
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while (!(DMA(instance)->ISTR & ISTR_FE_FLG))
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barrier();
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mb(); /* no IO until FLUSH is done */
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}
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/* clear a possible interrupt */
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/* I think that this CINT is only necessary if you are
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* using the terminal count features. HM 7 Mar 1994
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*/
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DMA(instance)->CINT = 1;
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/* stop DMA */
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DMA(instance)->SP_DMA = 1;
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mb(); /* make sure DMA is stopped before next IO */
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/* restore the CONTROL bits (minus the direction flag) */
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DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN;
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mb(); /* make sure CNTR is updated before next IO */
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/* copy from a bounce buffer, if necessary */
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if (status && HDATA(instance)->dma_bounce_buffer) {
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if (SCpnt) {
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if (HDATA(instance)->dma_dir && SCpnt)
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memcpy (SCpnt->SCp.ptr,
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HDATA(instance)->dma_bounce_buffer,
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SCpnt->SCp.this_residual);
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kfree (HDATA(instance)->dma_bounce_buffer);
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HDATA(instance)->dma_bounce_buffer = NULL;
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HDATA(instance)->dma_bounce_len = 0;
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} else {
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kfree (HDATA(instance)->dma_bounce_buffer);
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HDATA(instance)->dma_bounce_buffer = NULL;
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HDATA(instance)->dma_bounce_len = 0;
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/* flush if we were reading */
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if (HDATA(instance)->dma_dir) {
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DMA(instance)->FLUSH = 1;
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mb(); /* don't allow prefetch */
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while (!(DMA(instance)->ISTR & ISTR_FE_FLG))
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barrier();
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mb(); /* no IO until FLUSH is done */
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}
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/* clear a possible interrupt */
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/* I think that this CINT is only necessary if you are
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* using the terminal count features. HM 7 Mar 1994
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*/
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DMA(instance)->CINT = 1;
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/* stop DMA */
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DMA(instance)->SP_DMA = 1;
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mb(); /* make sure DMA is stopped before next IO */
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/* restore the CONTROL bits (minus the direction flag) */
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DMA(instance)->CNTR = CNTR_PDMD | CNTR_INTEN;
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mb(); /* make sure CNTR is updated before next IO */
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/* copy from a bounce buffer, if necessary */
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if (status && HDATA(instance)->dma_bounce_buffer) {
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if (SCpnt) {
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if (HDATA(instance)->dma_dir && SCpnt)
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memcpy(SCpnt->SCp.ptr,
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HDATA(instance)->dma_bounce_buffer,
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SCpnt->SCp.this_residual);
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kfree(HDATA(instance)->dma_bounce_buffer);
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HDATA(instance)->dma_bounce_buffer = NULL;
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HDATA(instance)->dma_bounce_len = 0;
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} else {
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kfree(HDATA(instance)->dma_bounce_buffer);
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HDATA(instance)->dma_bounce_buffer = NULL;
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HDATA(instance)->dma_bounce_len = 0;
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}
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}
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}
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}
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static int __init a3000_detect(struct scsi_host_template *tpnt)
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{
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wd33c93_regs regs;
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wd33c93_regs regs;
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if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI))
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return 0;
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if (!request_mem_region(0xDD0000, 256, "wd33c93"))
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return 0;
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if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(A3000_SCSI))
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return 0;
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if (!request_mem_region(0xDD0000, 256, "wd33c93"))
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return 0;
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tpnt->proc_name = "A3000";
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tpnt->proc_info = &wd33c93_proc_info;
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tpnt->proc_name = "A3000";
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tpnt->proc_info = &wd33c93_proc_info;
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a3000_host = scsi_register (tpnt, sizeof(struct WD33C93_hostdata));
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if (a3000_host == NULL)
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goto fail_register;
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a3000_host = scsi_register(tpnt, sizeof(struct WD33C93_hostdata));
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if (a3000_host == NULL)
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goto fail_register;
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a3000_host->base = ZTWO_VADDR(0xDD0000);
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a3000_host->irq = IRQ_AMIGA_PORTS;
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DMA(a3000_host)->DAWR = DAWR_A3000;
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regs.SASR = &(DMA(a3000_host)->SASR);
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regs.SCMD = &(DMA(a3000_host)->SCMD);
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HDATA(a3000_host)->no_sync = 0xff;
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HDATA(a3000_host)->fast = 0;
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HDATA(a3000_host)->dma_mode = CTRL_DMA;
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wd33c93_init(a3000_host, regs, dma_setup, dma_stop, WD33C93_FS_12_15);
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if (request_irq(IRQ_AMIGA_PORTS, a3000_intr, IRQF_SHARED, "A3000 SCSI",
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a3000_intr))
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goto fail_irq;
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DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN;
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a3000_host->base = ZTWO_VADDR(0xDD0000);
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a3000_host->irq = IRQ_AMIGA_PORTS;
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DMA(a3000_host)->DAWR = DAWR_A3000;
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regs.SASR = &(DMA(a3000_host)->SASR);
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regs.SCMD = &(DMA(a3000_host)->SCMD);
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HDATA(a3000_host)->no_sync = 0xff;
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HDATA(a3000_host)->fast = 0;
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HDATA(a3000_host)->dma_mode = CTRL_DMA;
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wd33c93_init(a3000_host, regs, dma_setup, dma_stop, WD33C93_FS_12_15);
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if (request_irq(IRQ_AMIGA_PORTS, a3000_intr, IRQF_SHARED, "A3000 SCSI",
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a3000_intr))
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goto fail_irq;
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DMA(a3000_host)->CNTR = CNTR_PDMD | CNTR_INTEN;
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return 1;
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return 1;
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fail_irq:
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scsi_unregister(a3000_host);
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scsi_unregister(a3000_host);
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fail_register:
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release_mem_region(0xDD0000, 256);
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return 0;
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release_mem_region(0xDD0000, 256);
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return 0;
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}
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static int a3000_bus_reset(struct scsi_cmnd *cmd)
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{
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/* FIXME perform bus-specific reset */
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/* FIXME 2: kill this entire function, which should
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cause mid-layer to call wd33c93_host_reset anyway? */
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@ -236,10 +236,10 @@ static struct scsi_host_template driver_template = {
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static int a3000_release(struct Scsi_Host *instance)
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{
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DMA(instance)->CNTR = 0;
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release_mem_region(0xDD0000, 256);
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free_irq(IRQ_AMIGA_PORTS, a3000_intr);
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return 1;
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DMA(instance)->CNTR = 0;
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release_mem_region(0xDD0000, 256);
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free_irq(IRQ_AMIGA_PORTS, a3000_intr);
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return 1;
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}
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MODULE_LICENSE("GPL");
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@ -12,40 +12,40 @@
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#include <linux/types.h>
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#ifndef CMD_PER_LUN
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#define CMD_PER_LUN 2
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#define CMD_PER_LUN 2
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#endif
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#ifndef CAN_QUEUE
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#define CAN_QUEUE 16
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#define CAN_QUEUE 16
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#endif
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/*
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* if the transfer address ANDed with this results in a non-zero
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* result, then we can't use DMA.
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*/
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#define A3000_XFER_MASK (0x00000003)
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#define A3000_XFER_MASK (0x00000003)
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typedef struct {
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unsigned char pad1[2];
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volatile unsigned short DAWR;
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volatile unsigned int WTC;
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unsigned char pad2[2];
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volatile unsigned short CNTR;
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volatile unsigned long ACR;
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unsigned char pad3[2];
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volatile unsigned short ST_DMA;
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unsigned char pad4[2];
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volatile unsigned short FLUSH;
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unsigned char pad5[2];
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volatile unsigned short CINT;
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unsigned char pad6[2];
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volatile unsigned short ISTR;
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unsigned char pad7[30];
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volatile unsigned short SP_DMA;
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unsigned char pad8;
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volatile unsigned char SASR;
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unsigned char pad9;
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volatile unsigned char SCMD;
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unsigned char pad1[2];
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volatile unsigned short DAWR;
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volatile unsigned int WTC;
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unsigned char pad2[2];
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volatile unsigned short CNTR;
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volatile unsigned long ACR;
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unsigned char pad3[2];
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volatile unsigned short ST_DMA;
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unsigned char pad4[2];
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volatile unsigned short FLUSH;
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unsigned char pad5[2];
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volatile unsigned short CINT;
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unsigned char pad6[2];
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volatile unsigned short ISTR;
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unsigned char pad7[30];
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volatile unsigned short SP_DMA;
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unsigned char pad8;
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volatile unsigned char SASR;
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unsigned char pad9;
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volatile unsigned char SCMD;
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} a3000_scsiregs;
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#define DAWR_A3000 (3)
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