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clk: samsung: exynos4: fixup reg access on be

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Use the byte-order aware big endian accessors, allowing for kernels
running under big-endian.

Signed-off-by: Matthew Leach <matthew@mattleach.net>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Matthew Leach 2016-06-08 19:30:58 +01:00 committed by Sylwester Nawrocki
parent 4de103397b
commit 21a5560b5d
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/samsung/clk-exynos4.c
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@ -1375,12 +1375,12 @@ static void __init exynos4x12_core_down_clock(void)
if (num_possible_cpus() == 4)
tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
__raw_writel(tmp, reg_base + PWR_CTRL1);
writel_relaxed(tmp, reg_base + PWR_CTRL1);
/*
* Disable the clock up feature in case it was enabled by bootloader.
*/
__raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
}
#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \