tools/power turbostat: simplify Bzy_MHz calculation
Bzy_MHz = TSC_delta*tsc_tweak/APERF_delta/MPERF_delta/measurement_interval becomes Bzy_MHz = base_mhz/APERF_delta/MPERF_delta on systems which support MSR_NHM_PLATFORM_INFO. base_mhz is calculated directly from the base_ratio reported in MSR_NHM_PLATFORM_INFO * bclk, and bclk is discovered via MSR or cpuid. This reduces the dependency of Bzy_MHz calculation on the TSC. Previously, there were 4 TSC readings required in each caculation, the raw TSC delta combined with the measurement_interval. This also removes the "tsc_tweak" correction factor used when TSC runs on a different base clock from the CPU's bclk. After this change, tsc_tweak is used only for %Busy. The end-result should be a Bzy_MHz result slightly less prone to jitter. Signed-off-by: Len Brown <len.brown@intel.com>
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@ -75,6 +75,7 @@ unsigned int aperf_mperf_multiplier = 1;
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int do_smi;
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double bclk;
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double base_hz;
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unsigned int has_base_hz;
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double tsc_tweak = 1.0;
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unsigned int show_pkg;
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unsigned int show_core;
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@ -96,6 +97,7 @@ unsigned int do_ring_perf_limit_reasons;
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unsigned int crystal_hz;
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unsigned long long tsc_hz;
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int base_cpu;
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double discover_bclk(unsigned int family, unsigned int model);
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#define RAPL_PKG (1 << 0)
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/* 0x610 MSR_PKG_POWER_LIMIT */
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@ -511,9 +513,13 @@ int format_counters(struct thread_data *t, struct core_data *c,
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}
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/* Bzy_MHz */
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if (has_aperf)
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outp += sprintf(outp, "%8.0f",
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1.0 * t->tsc * tsc_tweak / units * t->aperf / t->mperf / interval_float);
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if (has_aperf) {
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if (has_base_hz)
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outp += sprintf(outp, "%8.0f", base_hz / units * t->aperf / t->mperf);
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else
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outp += sprintf(outp, "%8.0f",
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1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
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}
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/* TSC_MHz */
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outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float);
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@ -1158,12 +1164,6 @@ int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV,
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static void
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calculate_tsc_tweak()
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{
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unsigned long long msr;
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unsigned int base_ratio;
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get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
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base_ratio = (msr >> 8) & 0xFF;
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base_hz = base_ratio * bclk * 1000000;
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tsc_tweak = base_hz / tsc_hz;
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}
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@ -1821,6 +1821,7 @@ void check_permissions()
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int probe_nhm_msrs(unsigned int family, unsigned int model)
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{
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unsigned long long msr;
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unsigned int base_ratio;
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int *pkg_cstate_limits;
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if (!genuine_intel)
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@ -1829,6 +1830,8 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
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if (family != 6)
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return 0;
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bclk = discover_bclk(family, model);
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switch (model) {
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case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
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case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
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@ -1871,9 +1874,13 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
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return 0;
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}
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get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
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pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
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get_msr(base_cpu, MSR_NHM_PLATFORM_INFO, &msr);
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base_ratio = (msr >> 8) & 0xFF;
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base_hz = base_ratio * bclk * 1000000;
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has_base_hz = 1;
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return 1;
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}
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int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
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@ -2780,7 +2787,6 @@ void process_cpuid()
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do_skl_residency = has_skl_msrs(family, model);
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do_slm_cstates = is_slm(family, model);
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do_knl_cstates = is_knl(family, model);
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bclk = discover_bclk(family, model);
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rapl_probe(family, model);
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perf_limit_reasons_probe(family, model);
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