Freescale arm64 device tree updates for 4.10:
- Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJYKrk2AAoJEFBXWFqHsHzOQlwH+wQXK2WABTOjRVchLOzup/cD UtB7mbmXJrBSePa3OTvF8xMk4VFfjm9oljmLnUEnzWEfjsS2aURT2GJBWv/ddhqw Mg/fYcZ1LgzJq8VOnenLpF1L2jc/I2hivCkBNmmkMK0HQvURKEAsdqNDc7Zg0meY 64qokll9Uz4DM2yeHkrUs9Q13UPs9/88ikYbE+CVDFaI0TCJjZUTImmjYkt8pJyk poDtW6yE8ibMNk2DK4e4tthPRcYnhkFOtSJF6Qy6jouV/J9+aaKG5+rj4MBeF8Aj T2+RFSQ4s2BuI5cH3qQq8Fv7lvF0Ay4wNWZl420R7shjbPWQNdIcbAbKL+51De0= =jiir -----END PGP SIGNATURE----- Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Freescale arm64 device tree updates for 4.10: - Enable Thermal Monitoring Unit (TMU) for thermal management on LS1043A and LS2080A. - Add support for LS1046A SoC, which has similar peripherals as LS1043A but integrates 4 A72 cores. - Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB. * tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add TMU device tree support for LS2080A arm64: dts: ls1043a: Add TMU device tree support for LS1043A arm64: dts: add LS1046A-QDS board support Documentation: DT: Add entry for QorIQ LS1046A-QDS board arm64: dts: add LS1046A-RDB board support Documentation: DT: Add entry for QorIQ LS1046A-RDB board arm64: dts: add QorIQ LS1046A SoC support dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen dt-bindings: i2c: adds two more nxp devices dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
22381d08c7
|
@ -97,7 +97,7 @@ Freescale LS1021A Platform Device Tree Bindings
|
|||
Required root node compatible properties:
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||||
- compatible = "fsl,ls1021a";
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Freescale LS1021A SoC-specific Device Tree Bindings
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Freescale SoC-specific Device Tree Bindings
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-------------------------------------------
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Freescale SCFG
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|
@ -105,7 +105,11 @@ Freescale SCFG
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configuration and status registers for the chip. Such as getting PEX port
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status.
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Required properties:
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- compatible: should be "fsl,ls1021a-scfg"
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- compatible: Should contain a chip-specific compatible string,
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Chip-specific strings are of the form "fsl,<chip>-scfg",
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The following <chip>s are known to be supported:
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ls1021a, ls1043a, ls1046a, ls2080a.
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- reg: should contain base address and length of SCFG memory-mapped registers
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Example:
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@ -119,7 +123,11 @@ Freescale DCFG
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configuration and status for the device. Such as setting the secondary
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core start address and release the secondary core from holdoff and startup.
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Required properties:
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- compatible: should be "fsl,ls1021a-dcfg"
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- compatible: Should contain a chip-specific compatible string,
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Chip-specific strings are of the form "fsl,<chip>-dcfg",
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The following <chip>s are known to be supported:
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ls1021a, ls1043a, ls1046a, ls2080a.
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- reg : should contain base address and length of DCFG memory-mapped registers
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Example:
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@ -131,6 +139,10 @@ Example:
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Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
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----------------------------------------------------------------
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LS1043A SoC
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Required root node properties:
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- compatible = "fsl,ls1043a";
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LS1043A ARMv8 based RDB Board
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Required root node properties:
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- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
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@ -139,6 +151,22 @@ LS1043A ARMv8 based QDS Board
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Required root node properties:
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- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
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LS1046A SoC
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Required root node properties:
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- compatible = "fsl,ls1046a";
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LS1046A ARMv8 based QDS Board
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Required root node properties:
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- compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
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LS1046A ARMv8 based RDB Board
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Required root node properties:
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- compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
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LS2080A SoC
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Required root node properties:
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- compatible = "fsl,ls2080a";
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LS2080A ARMv8 based Simulator model
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Required root node properties:
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- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
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|
|
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@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
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Required properties:
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- reg: Physical base address and size of the controller's register area.
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- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
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chip could be ls1021a, ls2080a, ls1043a etc.
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chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
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- clocks: Input clock specifier. Refer to common clock bindings.
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- interrupts: Interrupt specifier. Refer to interrupt binding.
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@ -32,6 +32,9 @@ Required properties:
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* "fsl,b4420-clockgen"
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* "fsl,b4860-clockgen"
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* "fsl,ls1021a-clockgen"
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* "fsl,ls1043a-clockgen"
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* "fsl,ls1046a-clockgen"
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* "fsl,ls2080a-clockgen"
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Chassis-version clock strings include:
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* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
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* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
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|
|
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@ -130,6 +130,8 @@ nuvoton,npct501 i2c trusted platform module (TPM)
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nuvoton,npct601 i2c trusted platform module (TPM2)
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nxp,pca9556 Octal SMBus and I2C registered interface
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nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
|
||||
nxp,pcf2127 Real-time clock
|
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nxp,pcf2129 Real-time clock
|
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nxp,pcf8563 Real-time clock/calendar
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nxp,pcf85063 Tiny Real-Time Clock
|
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oki,ml86v7667 OKI ML86V7667 video decoder
|
||||
|
|
|
@ -1,5 +1,7 @@
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|||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
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||||
|
|
|
@ -45,7 +45,7 @@
|
|||
*/
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||||
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||||
/dts-v1/;
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||||
/include/ "fsl-ls1043a.dtsi"
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#include "fsl-ls1043a.dtsi"
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|
||||
/ {
|
||||
model = "LS1043A QDS Board";
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|
|
|
@ -45,7 +45,7 @@
|
|||
*/
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||||
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||||
/dts-v1/;
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/include/ "fsl-ls1043a.dtsi"
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||||
#include "fsl-ls1043a.dtsi"
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||||
|
||||
/ {
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||||
model = "LS1043A RDB Board";
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||||
|
|
|
@ -44,6 +44,8 @@
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|||
* OTHER DEALINGS IN THE SOFTWARE.
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||||
*/
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||||
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#include <dt-bindings/thermal/thermal.h>
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||||
/ {
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||||
compatible = "fsl,ls1043a";
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interrupt-parent = <&gic>;
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|
@ -66,6 +68,7 @@
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|||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
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||||
next-level-cache = <&l2>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
|
@ -255,6 +258,81 @@
|
|||
big-endian;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
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compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
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interrupts = <0 33 0x4>;
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
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||||
0x00000002 0x00000032
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||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
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||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
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||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
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||||
0x00020005 0x00000061
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||||
0x00020006 0x0000006d
|
||||
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
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||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
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polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
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||||
|
||||
thermal-sensors = <&tmu 3>;
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|
||||
trips {
|
||||
cpu_alert: cpu-alert {
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||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
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cpu_crit: cpu-crit {
|
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temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT
|
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THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dspi0: dspi@2100000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
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#address-cells = <1>;
|
||||
|
|
212
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
Normal file
212
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
Normal file
|
@ -0,0 +1,212 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Shaohui Xie <Shaohui.Xie@nxp.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A QDS Board";
|
||||
compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
gpio3 = &gpio3;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&dspi {
|
||||
bus-num = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a11", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
||||
flash@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst25wf040b", "jedec,spi-nor";
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
reg = <1>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
|
||||
flash@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "en25s64", "jedec,spi-nor";
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
reg = <2>;
|
||||
spi-max-frequency = <10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
pca9547@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x2>;
|
||||
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
ina220@41 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x41>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
/* IRQ10_B */
|
||||
interrupts = <0 150 0x4>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x56>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x57>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461a";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NOR, NAND Flashes and FPGA on board */
|
||||
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
|
||||
0x1 0x0 0x0 0x7e800000 0x00010000
|
||||
0x2 0x0 0x0 0x7fb00000 0x00000100>;
|
||||
status = "okay";
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
};
|
||||
|
||||
fpga: board-control@2,0 {
|
||||
compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis";
|
||||
reg = <0x2 0x0 0x0000100>;
|
||||
};
|
||||
};
|
||||
|
||||
&lpuart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
num-cs = <2>;
|
||||
bus-num = <0>;
|
||||
status = "okay";
|
||||
|
||||
qflash0: s25fl128s@0 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
150
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
Normal file
150
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
Normal file
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A RDB Board";
|
||||
compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
|
||||
|
||||
aliases {
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NAND Flashe and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
|
||||
0x2 0x0 0x0 0x7fb00000 0x00000100>;
|
||||
status = "okay";
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "fsl,ifc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x10000>;
|
||||
};
|
||||
|
||||
cpld: board-control@2,0 {
|
||||
compatible = "fsl,ls1046ardb-cpld";
|
||||
reg = <0x2 0x0 0x0000100>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
num-cs = <2>;
|
||||
bus-num = <0>;
|
||||
status = "okay";
|
||||
|
||||
qflash0: s25fs512s@0 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
qflash1: s25fs512s@1 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
515
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
Normal file
515
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
Normal file
|
@ -0,0 +1,515 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1046a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x00010000>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1410000 0 0x10000>, /* GICD */
|
||||
<0x0 0x1420000 0 0x20000>, /* GICC */
|
||||
<0x0 0x1440000 0 0x20000>, /* GICH */
|
||||
<0x0 0x1460000 0 0x20000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
||||
big-endian;
|
||||
fsl,qspi-has-second-chip;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <0>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1046a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1046a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1046a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
dspi: dspi@2100000 {
|
||||
compatible = "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2330000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog0: watchdog@2ad0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 1>,
|
||||
<&clockgen 4 1>;
|
||||
};
|
||||
|
||||
usb0: usb@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
usb1: usb@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
usb2: usb@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1046a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl-ls2080a.dtsi"
|
||||
#include "fsl-ls2080a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale Layerscape 2080a QDS Board";
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl-ls2080a.dtsi"
|
||||
#include "fsl-ls2080a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale Layerscape 2080a RDB Board";
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "fsl-ls2080a.dtsi"
|
||||
#include "fsl-ls2080a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale Layerscape 2080a software Simulator model";
|
||||
|
|
|
@ -44,6 +44,8 @@
|
|||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls2080a";
|
||||
interrupt-parent = <&gic>;
|
||||
|
@ -62,15 +64,16 @@
|
|||
*/
|
||||
|
||||
/* We have 4 clusters having 2 Cortex-A57 cores each */
|
||||
cpu@0 {
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&cluster0_l2>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1>;
|
||||
|
@ -78,15 +81,16 @@
|
|||
next-level-cache = <&cluster0_l2>;
|
||||
};
|
||||
|
||||
cpu@100 {
|
||||
cpu2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x100>;
|
||||
clocks = <&clockgen 1 1>;
|
||||
next-level-cache = <&cluster1_l2>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu@101 {
|
||||
cpu3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x101>;
|
||||
|
@ -94,15 +98,16 @@
|
|||
next-level-cache = <&cluster1_l2>;
|
||||
};
|
||||
|
||||
cpu@200 {
|
||||
cpu4: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x200>;
|
||||
clocks = <&clockgen 1 2>;
|
||||
next-level-cache = <&cluster2_l2>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu@201 {
|
||||
cpu5: cpu@201 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x201>;
|
||||
|
@ -110,15 +115,16 @@
|
|||
next-level-cache = <&cluster2_l2>;
|
||||
};
|
||||
|
||||
cpu@300 {
|
||||
cpu6: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x300>;
|
||||
clocks = <&clockgen 1 3>;
|
||||
next-level-cache = <&cluster3_l2>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu@301 {
|
||||
cpu7: cpu@301 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x301>;
|
||||
|
@ -216,6 +222,100 @@
|
|||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
tmu: tmu@1f80000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f80000 0x0 0x10000>;
|
||||
interrupts = <0 23 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
little-endian;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
|
||||
thermal-sensors = <&tmu 4>;
|
||||
|
||||
trips {
|
||||
cpu_alert: cpu-alert {
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
cpu_crit: cpu-crit {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map1 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map2 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu4 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
map3 {
|
||||
trip = <&cpu_alert>;
|
||||
cooling-device =
|
||||
<&cpu6 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21c0500 0x0 0x100>;
|
||||
|
|
Loading…
Reference in a new issue