Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: fsldma: Fix compile warnings fsldma: fix memory leak on error path in fsl_dma_prep_memcpy() fsldma: snooping is not enabled for last entry in descriptor chain fsldma: fix infinite loop on multi-descriptor DMA chain completion fsldma: fix "DMA halt timeout!" errors fsldma: fix check on potential fdev->chan[] overflow fsldma: update mailling list address in MAINTAINERS
This commit is contained in:
commit
228b60acaa
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@ -2251,7 +2251,7 @@ P: Li Yang
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M: leoli@freescale.com
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P: Zhang Wei
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M: zw@zh-kernel.org
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L: linuxppc-embedded@ozlabs.org
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L: linuxppc-dev@ozlabs.org
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L: linux-kernel@vger.kernel.org
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S: Maintained
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F: drivers/dma/fsldma.*
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@ -179,9 +179,14 @@ static void dma_halt(struct fsl_dma_chan *fsl_chan)
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static void set_ld_eol(struct fsl_dma_chan *fsl_chan,
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struct fsl_desc_sw *desc)
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{
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u64 snoop_bits;
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snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
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? FSL_DMA_SNEN : 0;
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desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan,
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DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL,
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64);
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DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
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| snoop_bits, 64);
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}
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static void append_ld_queue(struct fsl_dma_chan *fsl_chan,
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@ -313,8 +318,8 @@ static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable)
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static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
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struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan);
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struct fsl_desc_sw *desc;
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unsigned long flags;
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dma_cookie_t cookie;
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@ -322,14 +327,17 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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spin_lock_irqsave(&fsl_chan->desc_lock, flags);
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cookie = fsl_chan->common.cookie;
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cookie++;
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if (cookie < 0)
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cookie = 1;
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desc->async_tx.cookie = cookie;
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fsl_chan->common.cookie = desc->async_tx.cookie;
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list_for_each_entry(desc, &tx->tx_list, node) {
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cookie++;
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if (cookie < 0)
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cookie = 1;
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append_ld_queue(fsl_chan, desc);
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list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev);
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desc->async_tx.cookie = cookie;
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}
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fsl_chan->common.cookie = cookie;
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append_ld_queue(fsl_chan, tx_to_fsl_desc(tx));
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list_splice_init(&tx->tx_list, fsl_chan->ld_queue.prev);
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spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
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@ -454,8 +462,8 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
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{
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struct fsl_dma_chan *fsl_chan;
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struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
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struct list_head *list;
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size_t copy;
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LIST_HEAD(link_chain);
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if (!chan)
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return NULL;
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@ -472,7 +480,7 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
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if (!new) {
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dev_err(fsl_chan->dev,
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"No free memory for link descriptor\n");
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return NULL;
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goto fail;
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}
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#ifdef FSL_DMA_LD_DEBUG
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dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new);
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@ -507,7 +515,19 @@ static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
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/* Set End-of-link to the last link descriptor of new list*/
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set_ld_eol(fsl_chan, new);
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return first ? &first->async_tx : NULL;
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return &first->async_tx;
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fail:
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if (!first)
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return NULL;
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list = &first->async_tx.tx_list;
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list_for_each_entry_safe_reverse(new, prev, list, node) {
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list_del(&new->node);
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dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys);
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}
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return NULL;
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}
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/**
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@ -598,15 +618,16 @@ static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
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dma_addr_t next_dest_addr;
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unsigned long flags;
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spin_lock_irqsave(&fsl_chan->desc_lock, flags);
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if (!dma_is_idle(fsl_chan))
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return;
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goto out_unlock;
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dma_halt(fsl_chan);
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/* If there are some link descriptors
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* not transfered in queue. We need to start it.
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*/
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spin_lock_irqsave(&fsl_chan->desc_lock, flags);
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/* Find the first un-transfer desciptor */
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for (ld_node = fsl_chan->ld_queue.next;
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@ -617,19 +638,20 @@ static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
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fsl_chan->common.cookie) == DMA_SUCCESS);
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ld_node = ld_node->next);
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spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
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if (ld_node != &fsl_chan->ld_queue) {
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/* Get the ld start address from ld_queue */
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next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys;
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dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n",
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(void *)next_dest_addr);
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dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n",
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(unsigned long long)next_dest_addr);
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set_cdar(fsl_chan, next_dest_addr);
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dma_start(fsl_chan);
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} else {
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set_cdar(fsl_chan, 0);
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set_ndar(fsl_chan, 0);
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}
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out_unlock:
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spin_unlock_irqrestore(&fsl_chan->desc_lock, flags);
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}
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/**
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@ -734,8 +756,9 @@ static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data)
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*/
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if (stat & FSL_DMA_SR_EOSI) {
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dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n");
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dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n",
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(void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan));
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dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n",
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(unsigned long long)get_cdar(fsl_chan),
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(unsigned long long)get_ndar(fsl_chan));
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stat &= ~FSL_DMA_SR_EOSI;
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update_cookie = 1;
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}
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@ -830,7 +853,7 @@ static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev,
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new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1);
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new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7;
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if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) {
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if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
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dev_err(fdev->dev, "There is no %d channel!\n",
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new_fsl_chan->id);
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err = -EINVAL;
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@ -925,8 +948,8 @@ static int __devinit of_fsl_dma_probe(struct of_device *dev,
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}
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dev_info(&dev->dev, "Probe the Freescale DMA driver for %s "
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"controller at %p...\n",
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match->compatible, (void *)fdev->reg.start);
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"controller at 0x%llx...\n",
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match->compatible, (unsigned long long)fdev->reg.start);
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fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end
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- fdev->reg.start + 1);
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