iommu/vt-d: Use per-cpu IOVA caching
Commit 9257b4a2
('iommu/iova: introduce per-cpu caching to iova allocation')
introduced per-CPU IOVA caches to massively improve scalability. Use them.
Signed-off-by: Omer Peleg <omer@cs.technion.ac.il>
[mad@cs.technion.ac.il: rebased, cleaned up and reworded the commit message]
Signed-off-by: Adam Morrison <mad@cs.technion.ac.il>
Reviewed-by: Shaohua Li <shli@fb.com>
Reviewed-by: Ben Serebrin <serebrin@google.com>
[dwmw2: split out VT-d part into a separate patch]
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
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9257b4a206
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@ -3357,7 +3357,7 @@ static unsigned long intel_alloc_iova(struct device *dev,
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struct dmar_domain *domain,
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unsigned long nrpages, uint64_t dma_mask)
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{
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struct iova *iova = NULL;
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unsigned long iova_pfn = 0;
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/* Restrict dma_mask to the width that the iommu can handle */
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dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
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@ -3370,19 +3370,19 @@ static unsigned long intel_alloc_iova(struct device *dev,
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* DMA_BIT_MASK(32) and if that fails then try allocating
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* from higher range
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*/
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iova = alloc_iova(&domain->iovad, nrpages,
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IOVA_PFN(DMA_BIT_MASK(32)), 1);
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if (iova)
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return iova->pfn_lo;
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iova_pfn = alloc_iova_fast(&domain->iovad, nrpages,
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IOVA_PFN(DMA_BIT_MASK(32)));
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if (iova_pfn)
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return iova_pfn;
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}
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iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
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if (unlikely(!iova)) {
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iova_pfn = alloc_iova_fast(&domain->iovad, nrpages, IOVA_PFN(dma_mask));
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if (unlikely(!iova_pfn)) {
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pr_err("Allocating %ld-page iova for %s failed",
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nrpages, dev_name(dev));
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return 0;
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}
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return iova->pfn_lo;
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return iova_pfn;
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}
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static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
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@ -3536,7 +3536,7 @@ static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
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error:
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if (iova_pfn)
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free_iova(&domain->iovad, iova_pfn);
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free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size));
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pr_err("Device %s request: %zx@%llx dir %d --- failed\n",
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dev_name(dev), size, (unsigned long long)paddr, dir);
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return 0;
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@ -3591,7 +3591,7 @@ static void flush_unmaps(struct deferred_flush_data *flush_data)
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iommu_flush_dev_iotlb(domain,
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(uint64_t)iova_pfn << PAGE_SHIFT, mask);
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}
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free_iova(&domain->iovad, iova_pfn);
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free_iova_fast(&domain->iovad, iova_pfn, nrpages);
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if (freelist)
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dma_free_pagelist(freelist);
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}
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@ -3691,7 +3691,7 @@ static void intel_unmap(struct device *dev, dma_addr_t dev_addr, size_t size)
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iommu_flush_iotlb_psi(iommu, domain, start_pfn,
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nrpages, !freelist, 0);
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/* free iova */
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free_iova(&domain->iovad, iova_pfn);
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free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(nrpages));
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dma_free_pagelist(freelist);
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} else {
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add_unmap(domain, iova_pfn, nrpages, freelist);
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@ -3849,7 +3849,7 @@ static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nele
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if (unlikely(ret)) {
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dma_pte_free_pagetable(domain, start_vpfn,
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start_vpfn + size - 1);
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free_iova(&domain->iovad, iova_pfn);
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free_iova_fast(&domain->iovad, iova_pfn, dma_to_mm_pfn(size));
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return 0;
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}
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@ -4588,6 +4588,28 @@ static struct notifier_block intel_iommu_memory_nb = {
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.priority = 0
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};
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static void free_all_cpu_cached_iovas(unsigned int cpu)
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{
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int i;
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for (i = 0; i < g_num_of_iommus; i++) {
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struct intel_iommu *iommu = g_iommus[i];
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struct dmar_domain *domain;
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u16 did;
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if (!iommu)
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continue;
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for (did = 0; did < 0xffff; did++) {
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domain = get_iommu_domain(iommu, did);
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if (!domain)
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continue;
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free_cpu_cached_iovas(cpu, &domain->iovad);
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}
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}
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}
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static int intel_iommu_cpu_notifier(struct notifier_block *nfb,
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unsigned long action, void *v)
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{
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@ -4596,6 +4618,7 @@ static int intel_iommu_cpu_notifier(struct notifier_block *nfb,
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switch (action) {
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case CPU_DEAD:
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case CPU_DEAD_FROZEN:
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free_all_cpu_cached_iovas(cpu);
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flush_unmaps_timeout(cpu);
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break;
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}
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