ASoC: Updates for v3.9
A few updates, more than I'd like, fixing some relatively small issues but mostly driver specific ones. Nothing wildly exciting so if it doesn't make v3.9 it won't be the end of the world but it'd be nice. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRZuy1AAoJELSic+t+oim9OEEP/2gMv6Snvv64DE0QBpEiSuYw te8xwz87cQzQp5tqWqnmgtM6g5/zC2zLEybhgZM4PBr/ZFbK6v7Ezki19pE2KOzE FhgyeAnfmySkWBrMRHPy0uj5snh8oEdZov64JP2g4wSfoPaOTJKawAnXaJkqRxD9 uHu37jtEfmdKJITvlKxoFieb9Q5fQc7upzINw4aOW6pr4yAYEAVp+lcSNr3aENKz C8ZrI8bbCgbfYHbmCF8j321f/QcFw9cHO8L+auLUpFF4vjn4HEZ4ArG0DxLU2iws 0o2wj1Xn+nNSlF+fo7+VCtvPKEvBcxLfjoP1yc1RHmo2POzdysxte038thoFCJ3j pnIOoq8H6WZejGA6vSMc6nlWkEBjEtworOjaT8wHWSiEbcjCcbeRjzUEo+GU1pdr 8xyr3bpisabgfJ5VbpJeUTIKMsScwCUbKA6eY3IDAmaUobpvsDVaW/01SdttylKn 9urEUiWUGOZbW3T/MoeQGeWfyMbWjbr17HzPPn15nzuTFOk44ONP0oQXQe8TJuB+ rNmV/+b2q4cnpnECG/eMH5fo4TZEp/7INHTFQtMg45ot6/VNMz9JLRm3ikru1+yF kuooaRAqA5c5zeavRCQV7yZL9idLEHjtLy8fY55r1FE0fRQZ5PksTCZcNFlrOajj DTRWhgFa7b7/c2Jm5W0e =W1XN -----END PGP SIGNATURE----- Merge tag 'asoc-v3.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus ASoC: Updates for v3.9 A few updates, more than I'd like, fixing some relatively small issues but mostly driver specific ones. Nothing wildly exciting so if it doesn't make v3.9 it won't be the end of the world but it'd be nice.
This commit is contained in:
commit
232a73dda2
|
@ -15,6 +15,13 @@ amemthresh - INTEGER
|
|||
enabled and the variable is automatically set to 2, otherwise
|
||||
the strategy is disabled and the variable is set to 1.
|
||||
|
||||
backup_only - BOOLEAN
|
||||
0 - disabled (default)
|
||||
not 0 - enabled
|
||||
|
||||
If set, disable the director function while the server is
|
||||
in backup mode to avoid packet loops for DR/TUN methods.
|
||||
|
||||
conntrack - BOOLEAN
|
||||
0 - disabled (default)
|
||||
not 0 - enabled
|
||||
|
|
27
MAINTAINERS
27
MAINTAINERS
|
@ -3242,6 +3242,12 @@ F: Documentation/firmware_class/
|
|||
F: drivers/base/firmware*.c
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||||
F: include/linux/firmware.h
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||||
|
||||
FLASHSYSTEM DRIVER (IBM FlashSystem 70/80 PCI SSD Flash Card)
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M: Joshua Morris <josh.h.morris@us.ibm.com>
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M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
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S: Maintained
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F: drivers/block/rsxx/
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||||
FLOPPY DRIVER
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M: Jiri Kosina <jkosina@suse.cz>
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||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/floppy.git
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|
@ -5059,9 +5065,8 @@ S: Maintained
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|||
F: drivers/net/ethernet/marvell/sk*
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||||
|
||||
MARVELL LIBERTAS WIRELESS DRIVER
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||||
M: Dan Williams <dcbw@redhat.com>
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L: libertas-dev@lists.infradead.org
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S: Maintained
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S: Orphan
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F: drivers/net/wireless/libertas/
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MARVELL MV643XX ETHERNET DRIVER
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|
@ -5563,6 +5568,7 @@ F: include/uapi/linux/if_*
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F: include/uapi/linux/netdevice.h
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NETXEN (1/10) GbE SUPPORT
|
||||
M: Manish Chopra <manish.chopra@qlogic.com>
|
||||
M: Sony Chacko <sony.chacko@qlogic.com>
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M: Rajesh Borundia <rajesh.borundia@qlogic.com>
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||||
L: netdev@vger.kernel.org
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|
@ -5683,7 +5689,7 @@ S: Maintained
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F: arch/arm/*omap*/*clock*
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OMAP POWER MANAGEMENT SUPPORT
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M: Kevin Hilman <khilman@ti.com>
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M: Kevin Hilman <khilman@deeprootsystems.com>
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L: linux-omap@vger.kernel.org
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S: Maintained
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F: arch/arm/*omap*/*pm*
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|
@ -5777,7 +5783,7 @@ F: arch/arm/*omap*/usb*
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|||
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OMAP GPIO DRIVER
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M: Santosh Shilimkar <santosh.shilimkar@ti.com>
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M: Kevin Hilman <khilman@ti.com>
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M: Kevin Hilman <khilman@deeprootsystems.com>
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||||
L: linux-omap@vger.kernel.org
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S: Maintained
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||||
F: drivers/gpio/gpio-omap.c
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|
@ -6209,7 +6215,7 @@ F: include/linux/power_supply.h
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F: drivers/power/
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PNP SUPPORT
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M: Adam Belay <abelay@mit.edu>
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M: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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M: Bjorn Helgaas <bhelgaas@google.com>
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S: Maintained
|
||||
F: drivers/pnp/
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||||
|
@ -6551,12 +6557,6 @@ S: Maintained
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|||
F: Documentation/blockdev/ramdisk.txt
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F: drivers/block/brd.c
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||||
|
||||
RAMSAM DRIVER (IBM RamSan 70/80 PCI SSD Flash Card)
|
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M: Joshua Morris <josh.h.morris@us.ibm.com>
|
||||
M: Philip Kelleher <pjk1939@linux.vnet.ibm.com>
|
||||
S: Maintained
|
||||
F: drivers/block/rsxx/
|
||||
|
||||
RANDOM NUMBER DRIVER
|
||||
M: Theodore Ts'o" <tytso@mit.edu>
|
||||
S: Maintained
|
||||
|
@ -7173,7 +7173,7 @@ F: arch/arm/mach-s3c2410/bast-irq.c
|
|||
|
||||
TI DAVINCI MACHINE SUPPORT
|
||||
M: Sekhar Nori <nsekhar@ti.com>
|
||||
M: Kevin Hilman <khilman@ti.com>
|
||||
M: Kevin Hilman <khilman@deeprootsystems.com>
|
||||
L: davinci-linux-open-source@linux.davincidsp.com (moderated for non-subscribers)
|
||||
T: git git://gitorious.org/linux-davinci/linux-davinci.git
|
||||
Q: http://patchwork.kernel.org/project/linux-davinci/list/
|
||||
|
@ -7706,9 +7706,10 @@ F: include/linux/swiotlb.h
|
|||
|
||||
SYNOPSYS ARC ARCHITECTURE
|
||||
M: Vineet Gupta <vgupta@synopsys.com>
|
||||
L: linux-snps-arc@vger.kernel.org
|
||||
S: Supported
|
||||
F: arch/arc/
|
||||
F: Documentation/devicetree/bindings/arc/
|
||||
F: drivers/tty/serial/arc-uart.c
|
||||
|
||||
SYSV FILESYSTEM
|
||||
M: Christoph Hellwig <hch@infradead.org>
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 9
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Unicycling Gorilla
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -12,7 +12,7 @@ NM := $(NM) -B
|
|||
|
||||
LDFLAGS_vmlinux := -static -N #-relax
|
||||
CHECKFLAGS += -D__alpha__ -m64
|
||||
cflags-y := -pipe -mno-fp-regs -ffixed-8 -msmall-data
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||||
cflags-y := -pipe -mno-fp-regs -ffixed-8
|
||||
cflags-y += $(call cc-option, -fno-jump-tables)
|
||||
|
||||
cpuflags-$(CONFIG_ALPHA_EV4) := -mcpu=ev4
|
||||
|
|
|
@ -26,7 +26,7 @@
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|||
#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
|
||||
#define fd_cacheflush(addr,size) /* nothing */
|
||||
#define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt,\
|
||||
IRQF_DISABLED, "floppy", NULL)
|
||||
0, "floppy", NULL)
|
||||
#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL)
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
|
|
@ -117,13 +117,6 @@ handle_irq(int irq)
|
|||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* From here we must proceed with IPL_MAX. Note that we do not
|
||||
* explicitly enable interrupts afterwards - some MILO PALcode
|
||||
* (namely LX164 one) seems to have severe problems with RTI
|
||||
* at IPL 0.
|
||||
*/
|
||||
local_irq_disable();
|
||||
irq_enter();
|
||||
generic_handle_irq_desc(irq, desc);
|
||||
irq_exit();
|
||||
|
|
|
@ -45,6 +45,14 @@ do_entInt(unsigned long type, unsigned long vector,
|
|||
unsigned long la_ptr, struct pt_regs *regs)
|
||||
{
|
||||
struct pt_regs *old_regs;
|
||||
|
||||
/*
|
||||
* Disable interrupts during IRQ handling.
|
||||
* Note that there is no matching local_irq_enable() due to
|
||||
* severe problems with RTI at IPL0 and some MILO PALcode
|
||||
* (namely LX164).
|
||||
*/
|
||||
local_irq_disable();
|
||||
switch (type) {
|
||||
case 0:
|
||||
#ifdef CONFIG_SMP
|
||||
|
@ -62,7 +70,6 @@ do_entInt(unsigned long type, unsigned long vector,
|
|||
{
|
||||
long cpu;
|
||||
|
||||
local_irq_disable();
|
||||
smp_percpu_timer_interrupt(regs);
|
||||
cpu = smp_processor_id();
|
||||
if (cpu != boot_cpuid) {
|
||||
|
@ -222,7 +229,6 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr,
|
|||
|
||||
struct irqaction timer_irqaction = {
|
||||
.handler = timer_interrupt,
|
||||
.flags = IRQF_DISABLED,
|
||||
.name = "timer",
|
||||
};
|
||||
|
||||
|
|
|
@ -188,6 +188,10 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
|
|||
extern void free_reserved_mem(void *, void *);
|
||||
extern void pcibios_claim_one_bus(struct pci_bus *);
|
||||
|
||||
static struct resource irongate_io = {
|
||||
.name = "Irongate PCI IO",
|
||||
.flags = IORESOURCE_IO,
|
||||
};
|
||||
static struct resource irongate_mem = {
|
||||
.name = "Irongate PCI MEM",
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||||
.flags = IORESOURCE_MEM,
|
||||
|
@ -209,6 +213,7 @@ nautilus_init_pci(void)
|
|||
|
||||
irongate = pci_get_bus_and_slot(0, 0);
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||||
bus->self = irongate;
|
||||
bus->resource[0] = &irongate_io;
|
||||
bus->resource[1] = &irongate_mem;
|
||||
|
||||
pci_bus_size_bridges(bus);
|
||||
|
|
|
@ -280,15 +280,15 @@ titan_late_init(void)
|
|||
* all reported to the kernel as machine checks, so the handler
|
||||
* is a nop so it can be called to count the individual events.
|
||||
*/
|
||||
titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(63+16, titan_intr_nop, 0,
|
||||
"CChip Error", NULL);
|
||||
titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(62+16, titan_intr_nop, 0,
|
||||
"PChip 0 H_Error", NULL);
|
||||
titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(61+16, titan_intr_nop, 0,
|
||||
"PChip 1 H_Error", NULL);
|
||||
titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(60+16, titan_intr_nop, 0,
|
||||
"PChip 0 C_Error", NULL);
|
||||
titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(59+16, titan_intr_nop, 0,
|
||||
"PChip 1 C_Error", NULL);
|
||||
|
||||
/*
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||||
|
@ -348,9 +348,9 @@ privateer_init_pci(void)
|
|||
* Hook a couple of extra err interrupts that the
|
||||
* common titan code won't.
|
||||
*/
|
||||
titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(53+16, titan_intr_nop, 0,
|
||||
"NMI", NULL);
|
||||
titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED,
|
||||
titan_request_irq(50+16, titan_intr_nop, 0,
|
||||
"Temperature Warning", NULL);
|
||||
|
||||
/*
|
||||
|
|
|
@ -126,7 +126,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg,
|
|||
int i;
|
||||
|
||||
for_each_sg(sg, s, nents, i)
|
||||
sg->dma_address = dma_map_page(dev, sg_page(s), s->offset,
|
||||
s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
|
||||
s->length, dir);
|
||||
|
||||
return nents;
|
||||
|
|
|
@ -72,7 +72,4 @@ extern int elf_check_arch(const struct elf32_hdr *);
|
|||
*/
|
||||
#define ELF_PLATFORM (NULL)
|
||||
|
||||
#define SET_PERSONALITY(ex) \
|
||||
set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
|
||||
|
||||
#endif
|
||||
|
|
|
@ -415,7 +415,7 @@
|
|||
*-------------------------------------------------------------*/
|
||||
.macro SAVE_ALL_EXCEPTION marker
|
||||
|
||||
st \marker, [sp, 8]
|
||||
st \marker, [sp, 8] /* orig_r8 */
|
||||
st r0, [sp, 4] /* orig_r0, needed only for sys calls */
|
||||
|
||||
/* Restore r9 used to code the early prologue */
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
|
||||
#ifdef CONFIG_KGDB
|
||||
|
||||
#include <asm/user.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/* to ensure compatibility with Linux 2.6.35, we don't implement the get/set
|
||||
* register API yet */
|
||||
|
@ -53,9 +53,7 @@ enum arc700_linux_regnums {
|
|||
};
|
||||
|
||||
#else
|
||||
static inline void kgdb_trap(struct pt_regs *regs, int param)
|
||||
{
|
||||
}
|
||||
#define kgdb_trap(regs, param)
|
||||
#endif
|
||||
|
||||
#endif /* __ARC_KGDB_H__ */
|
||||
|
|
|
@ -123,7 +123,7 @@ static inline long regs_return_value(struct pt_regs *regs)
|
|||
#define orig_r8_IS_SCALL 0x0001
|
||||
#define orig_r8_IS_SCALL_RESTARTED 0x0002
|
||||
#define orig_r8_IS_BRKPT 0x0004
|
||||
#define orig_r8_IS_EXCPN 0x0004
|
||||
#define orig_r8_IS_EXCPN 0x0008
|
||||
#define orig_r8_IS_IRQ1 0x0010
|
||||
#define orig_r8_IS_IRQ2 0x0020
|
||||
|
||||
|
|
|
@ -16,8 +16,6 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
int sys_clone_wrapper(int, int, int, int, int);
|
||||
int sys_fork_wrapper(void);
|
||||
int sys_vfork_wrapper(void);
|
||||
int sys_cacheflush(uint32_t, uint32_t uint32_t);
|
||||
int sys_arc_settls(void *);
|
||||
int sys_arc_gettls(void);
|
||||
|
|
|
@ -28,14 +28,14 @@
|
|||
*/
|
||||
struct user_regs_struct {
|
||||
|
||||
struct scratch {
|
||||
struct {
|
||||
long pad;
|
||||
long bta, lp_start, lp_end, lp_count;
|
||||
long status32, ret, blink, fp, gp;
|
||||
long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
|
||||
long sp;
|
||||
} scratch;
|
||||
struct callee {
|
||||
struct {
|
||||
long pad;
|
||||
long r25, r24, r23, r22, r21, r20;
|
||||
long r19, r18, r17, r16, r15, r14, r13;
|
||||
|
|
|
@ -452,7 +452,7 @@ tracesys:
|
|||
; using ERET won't work since next-PC has already committed
|
||||
lr r12, [efa]
|
||||
GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
|
||||
st r12, [r11, THREAD_FAULT_ADDR]
|
||||
st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
|
||||
|
||||
; PRE Sys Call Ptrace hook
|
||||
mov r0, sp ; pt_regs needed
|
||||
|
@ -792,31 +792,6 @@ ARC_EXIT ret_from_fork
|
|||
|
||||
;################### Special Sys Call Wrappers ##########################
|
||||
|
||||
; TBD: call do_fork directly from here
|
||||
ARC_ENTRY sys_fork_wrapper
|
||||
SAVE_CALLEE_SAVED_USER
|
||||
bl @sys_fork
|
||||
DISCARD_CALLEE_SAVED_USER
|
||||
|
||||
GET_CURR_THR_INFO_FLAGS r10
|
||||
btst r10, TIF_SYSCALL_TRACE
|
||||
bnz tracesys_exit
|
||||
|
||||
b ret_from_system_call
|
||||
ARC_EXIT sys_fork_wrapper
|
||||
|
||||
ARC_ENTRY sys_vfork_wrapper
|
||||
SAVE_CALLEE_SAVED_USER
|
||||
bl @sys_vfork
|
||||
DISCARD_CALLEE_SAVED_USER
|
||||
|
||||
GET_CURR_THR_INFO_FLAGS r10
|
||||
btst r10, TIF_SYSCALL_TRACE
|
||||
bnz tracesys_exit
|
||||
|
||||
b ret_from_system_call
|
||||
ARC_EXIT sys_vfork_wrapper
|
||||
|
||||
ARC_ENTRY sys_clone_wrapper
|
||||
SAVE_CALLEE_SAVED_USER
|
||||
bl @sys_clone
|
||||
|
|
|
@ -9,6 +9,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/kgdb.h>
|
||||
#include <linux/sched.h>
|
||||
#include <asm/disasm.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
|
|
|
@ -232,10 +232,8 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
|
|||
|
||||
n += scnprintf(buf + n, len - n, "\n");
|
||||
|
||||
#ifdef _ASM_GENERIC_UNISTD_H
|
||||
n += scnprintf(buf + n, len - n,
|
||||
"OS ABI [v2]\t: asm-generic/{unistd,stat,fcntl}\n");
|
||||
#endif
|
||||
"OS ABI [v3]\t: no-legacy-syscalls\n");
|
||||
|
||||
return buf;
|
||||
}
|
||||
|
|
|
@ -6,8 +6,6 @@
|
|||
#include <asm/syscalls.h>
|
||||
|
||||
#define sys_clone sys_clone_wrapper
|
||||
#define sys_fork sys_fork_wrapper
|
||||
#define sys_vfork sys_vfork_wrapper
|
||||
|
||||
#undef __SYSCALL
|
||||
#define __SYSCALL(nr, call) [nr] = (call),
|
||||
|
|
|
@ -1183,9 +1183,9 @@ config ARM_NR_BANKS
|
|||
default 8
|
||||
|
||||
config IWMMXT
|
||||
bool "Enable iWMMXt support"
|
||||
bool "Enable iWMMXt support" if !CPU_PJ4
|
||||
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
|
||||
default y if PXA27x || PXA3xx || ARCH_MMP
|
||||
default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
|
||||
help
|
||||
Enable support for iWMMXt context switching at run time if
|
||||
running on a CPU that supports it.
|
||||
|
@ -1439,6 +1439,16 @@ config ARM_ERRATA_775420
|
|||
to deadlock. This workaround puts DSB before executing ISB if
|
||||
an abort may occur on cache maintenance.
|
||||
|
||||
config ARM_ERRATA_798181
|
||||
bool "ARM errata: TLBI/DSB failure on Cortex-A15"
|
||||
depends on CPU_V7 && SMP
|
||||
help
|
||||
On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
|
||||
adequately shooting down all use of the old entries. This
|
||||
option enables the Linux kernel workaround for this erratum
|
||||
which sends an IPI to the CPUs that are running the same ASID
|
||||
as the one being invalidated.
|
||||
|
||||
endmenu
|
||||
|
||||
source "arch/arm/common/Kconfig"
|
||||
|
|
|
@ -495,6 +495,7 @@ config DEBUG_IMX_UART_PORT
|
|||
DEBUG_IMX53_UART || \
|
||||
DEBUG_IMX6Q_UART
|
||||
default 1
|
||||
depends on ARCH_MXC
|
||||
help
|
||||
Choose UART port on which kernel low-level debug messages
|
||||
should be output.
|
||||
|
|
|
@ -54,7 +54,7 @@
|
|||
};
|
||||
|
||||
mvsdio@d00d4000 {
|
||||
pinctrl-0 = <&sdio_pins2>;
|
||||
pinctrl-0 = <&sdio_pins3>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
/*
|
||||
|
|
|
@ -59,6 +59,12 @@
|
|||
"mpp50", "mpp51", "mpp52";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sdio_pins3: sdio-pins3 {
|
||||
marvell,pins = "mpp48", "mpp49", "mpp50",
|
||||
"mpp51", "mpp52", "mpp53";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@d0018100 {
|
||||
|
|
|
@ -191,8 +191,8 @@
|
|||
|
||||
prcmu: prcmu@80157000 {
|
||||
compatible = "stericsson,db8500-prcmu";
|
||||
reg = <0x80157000 0x1000>;
|
||||
reg-names = "prcmu";
|
||||
reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
|
||||
reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
|
||||
interrupts = <0 47 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
@ -77,6 +77,7 @@
|
|||
};
|
||||
|
||||
nand@3000000 {
|
||||
chip-delay = <40>;
|
||||
status = "okay";
|
||||
|
||||
partition@0 {
|
||||
|
|
|
@ -13,6 +13,9 @@
|
|||
compatible = "marvell,orion5x";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
};
|
||||
intc: interrupt-controller {
|
||||
compatible = "marvell,orion-intc", "marvell,intc";
|
||||
interrupt-controller;
|
||||
|
@ -32,7 +35,9 @@
|
|||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
reg = <0x10100 0x40>;
|
||||
ngpio = <32>;
|
||||
ngpios = <32>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <6>, <7>, <8>, <9>;
|
||||
};
|
||||
|
||||
|
@ -91,7 +96,7 @@
|
|||
reg = <0x90000 0x10000>,
|
||||
<0xf2200000 0x800>;
|
||||
reg-names = "regs", "sram";
|
||||
interrupts = <22>;
|
||||
interrupts = <28>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -385,7 +385,7 @@
|
|||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra20-slink";
|
||||
reg = <0x7000d480 0x200>;
|
||||
reg = <0x7000d800 0x200>;
|
||||
interrupts = <0 83 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 17>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -372,7 +372,7 @@
|
|||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
|
||||
reg = <0x7000d480 0x200>;
|
||||
reg = <0x7000d800 0x200>;
|
||||
interrupts = <0 83 0x04>;
|
||||
nvidia,dma-request-selector = <&apbdma 17>;
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -24,7 +24,7 @@ extern struct arm_delay_ops {
|
|||
void (*delay)(unsigned long);
|
||||
void (*const_udelay)(unsigned long);
|
||||
void (*udelay)(unsigned long);
|
||||
bool const_clock;
|
||||
unsigned long ticks_per_jiffy;
|
||||
} arm_delay_ops;
|
||||
|
||||
#define __delay(n) arm_delay_ops.delay(n)
|
||||
|
|
|
@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page);
|
|||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Needed to be able to broadcast the TLB invalidation for kmap.
|
||||
*/
|
||||
#ifdef CONFIG_ARM_ERRATA_798181
|
||||
#undef ARCH_NEEDS_KMAP_HIGH_GET
|
||||
#endif
|
||||
|
||||
#ifdef ARCH_NEEDS_KMAP_HIGH_GET
|
||||
extern void *kmap_high_get(struct page *page);
|
||||
#else
|
||||
|
|
|
@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm);
|
|||
void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
|
||||
#define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; })
|
||||
|
||||
DECLARE_PER_CPU(atomic64_t, active_asids);
|
||||
|
||||
#else /* !CONFIG_CPU_HAS_ASID */
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
|
|
|
@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void)
|
|||
isb();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_798181
|
||||
static inline void dummy_flush_tlb_a15_erratum(void)
|
||||
{
|
||||
/*
|
||||
* Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0.
|
||||
*/
|
||||
asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0));
|
||||
dsb();
|
||||
}
|
||||
#else
|
||||
static inline void dummy_flush_tlb_a15_erratum(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* flush_pmd_entry
|
||||
*
|
||||
|
|
|
@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old)
|
|||
*/
|
||||
|
||||
.macro mcount_enter
|
||||
/*
|
||||
* This pad compensates for the push {lr} at the call site. Note that we are
|
||||
* unable to unwind through a function which does not otherwise save its lr.
|
||||
*/
|
||||
UNWIND(.pad #4)
|
||||
stmdb sp!, {r0-r3, lr}
|
||||
UNWIND(.save {r0-r3, lr})
|
||||
.endm
|
||||
|
||||
.macro mcount_get_lr reg
|
||||
|
@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old)
|
|||
.endm
|
||||
|
||||
ENTRY(__gnu_mcount_nc)
|
||||
UNWIND(.fnstart)
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
mov ip, lr
|
||||
ldmia sp!, {lr}
|
||||
|
@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc)
|
|||
#else
|
||||
__mcount
|
||||
#endif
|
||||
UNWIND(.fnend)
|
||||
ENDPROC(__gnu_mcount_nc)
|
||||
|
||||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
ENTRY(ftrace_caller)
|
||||
UNWIND(.fnstart)
|
||||
__ftrace_caller
|
||||
UNWIND(.fnend)
|
||||
ENDPROC(ftrace_caller)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FUNCTION_GRAPH_TRACER
|
||||
ENTRY(ftrace_graph_caller)
|
||||
UNWIND(.fnstart)
|
||||
__ftrace_graph_caller
|
||||
UNWIND(.fnend)
|
||||
ENDPROC(ftrace_graph_caller)
|
||||
#endif
|
||||
|
||||
|
|
|
@ -267,7 +267,7 @@ __create_page_tables:
|
|||
addne r6, r6, #1 << SECTION_SHIFT
|
||||
strne r6, [r3]
|
||||
|
||||
#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
|
||||
#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
|
||||
sub r4, r4, #4 @ Fixup page table pointer
|
||||
@ for 64-bit descriptors
|
||||
#endif
|
||||
|
|
|
@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused)
|
|||
}
|
||||
|
||||
if (err) {
|
||||
pr_warning("CPU %d debug is powered down!\n", cpu);
|
||||
pr_warn_once("CPU %d debug is powered down!\n", cpu);
|
||||
cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
|
||||
return;
|
||||
}
|
||||
|
@ -987,7 +987,7 @@ clear_vcr:
|
|||
isb();
|
||||
|
||||
if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
|
||||
pr_warning("CPU %d failed to disable vector catch\n", cpu);
|
||||
pr_warn_once("CPU %d failed to disable vector catch\n", cpu);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -1007,7 +1007,7 @@ clear_vcr:
|
|||
}
|
||||
|
||||
if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) {
|
||||
pr_warning("CPU %d failed to clear debug register pairs\n", cpu);
|
||||
pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -353,6 +353,23 @@ void __init early_print(const char *str, ...)
|
|||
printk("%s", buf);
|
||||
}
|
||||
|
||||
static void __init cpuid_init_hwcaps(void)
|
||||
{
|
||||
unsigned int divide_instrs;
|
||||
|
||||
if (cpu_architecture() < CPU_ARCH_ARMv7)
|
||||
return;
|
||||
|
||||
divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
|
||||
|
||||
switch (divide_instrs) {
|
||||
case 2:
|
||||
elf_hwcap |= HWCAP_IDIVA;
|
||||
case 1:
|
||||
elf_hwcap |= HWCAP_IDIVT;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init feat_v6_fixup(void)
|
||||
{
|
||||
int id = read_cpuid_id();
|
||||
|
@ -483,8 +500,11 @@ static void __init setup_processor(void)
|
|||
snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
|
||||
list->elf_name, ENDIANNESS);
|
||||
elf_hwcap = list->elf_hwcap;
|
||||
|
||||
cpuid_init_hwcaps();
|
||||
|
||||
#ifndef CONFIG_ARM_THUMB
|
||||
elf_hwcap &= ~HWCAP_THUMB;
|
||||
elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
|
||||
#endif
|
||||
|
||||
feat_v6_fixup();
|
||||
|
@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
|
|||
size -= start & ~PAGE_MASK;
|
||||
bank->start = PAGE_ALIGN(start);
|
||||
|
||||
#ifndef CONFIG_LPAE
|
||||
#ifndef CONFIG_ARM_LPAE
|
||||
if (bank->start + size < bank->start) {
|
||||
printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
|
||||
"32-bit physical address space\n", (long long)start);
|
||||
|
|
|
@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb,
|
|||
if (freq->flags & CPUFREQ_CONST_LOOPS)
|
||||
return NOTIFY_OK;
|
||||
|
||||
if (arm_delay_ops.const_clock)
|
||||
return NOTIFY_OK;
|
||||
|
||||
if (!per_cpu(l_p_j_ref, cpu)) {
|
||||
per_cpu(l_p_j_ref, cpu) =
|
||||
per_cpu(cpu_data, cpu).loops_per_jiffy;
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
||||
/**********************************************************************/
|
||||
|
||||
|
@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored)
|
|||
local_flush_bp_all();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM_ERRATA_798181
|
||||
static int erratum_a15_798181(void)
|
||||
{
|
||||
unsigned int midr = read_cpuid_id();
|
||||
|
||||
/* Cortex-A15 r0p0..r3p2 affected */
|
||||
if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
#else
|
||||
static int erratum_a15_798181(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ipi_flush_tlb_a15_erratum(void *arg)
|
||||
{
|
||||
dmb();
|
||||
}
|
||||
|
||||
static void broadcast_tlb_a15_erratum(void)
|
||||
{
|
||||
if (!erratum_a15_798181())
|
||||
return;
|
||||
|
||||
dummy_flush_tlb_a15_erratum();
|
||||
smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
|
||||
NULL, 1);
|
||||
}
|
||||
|
||||
static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
|
||||
{
|
||||
int cpu;
|
||||
cpumask_t mask = { CPU_BITS_NONE };
|
||||
|
||||
if (!erratum_a15_798181())
|
||||
return;
|
||||
|
||||
dummy_flush_tlb_a15_erratum();
|
||||
for_each_online_cpu(cpu) {
|
||||
if (cpu == smp_processor_id())
|
||||
continue;
|
||||
/*
|
||||
* We only need to send an IPI if the other CPUs are running
|
||||
* the same ASID as the one being invalidated. There is no
|
||||
* need for locking around the active_asids check since the
|
||||
* switch_mm() function has at least one dmb() (as required by
|
||||
* this workaround) in case a context switch happens on
|
||||
* another CPU after the condition below.
|
||||
*/
|
||||
if (atomic64_read(&mm->context.id) ==
|
||||
atomic64_read(&per_cpu(active_asids, cpu)))
|
||||
cpumask_set_cpu(cpu, &mask);
|
||||
}
|
||||
smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
|
||||
}
|
||||
|
||||
void flush_tlb_all(void)
|
||||
{
|
||||
if (tlb_ops_need_broadcast())
|
||||
on_each_cpu(ipi_flush_tlb_all, NULL, 1);
|
||||
else
|
||||
local_flush_tlb_all();
|
||||
broadcast_tlb_a15_erratum();
|
||||
}
|
||||
|
||||
void flush_tlb_mm(struct mm_struct *mm)
|
||||
|
@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm)
|
|||
on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1);
|
||||
else
|
||||
local_flush_tlb_mm(mm);
|
||||
broadcast_tlb_mm_a15_erratum(mm);
|
||||
}
|
||||
|
||||
void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
|
||||
|
@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
|
|||
&ta, 1);
|
||||
} else
|
||||
local_flush_tlb_page(vma, uaddr);
|
||||
broadcast_tlb_mm_a15_erratum(vma->vm_mm);
|
||||
}
|
||||
|
||||
void flush_tlb_kernel_page(unsigned long kaddr)
|
||||
|
@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr)
|
|||
on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
|
||||
} else
|
||||
local_flush_tlb_kernel_page(kaddr);
|
||||
broadcast_tlb_a15_erratum();
|
||||
}
|
||||
|
||||
void flush_tlb_range(struct vm_area_struct *vma,
|
||||
|
@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma,
|
|||
&ta, 1);
|
||||
} else
|
||||
local_flush_tlb_range(vma, start, end);
|
||||
broadcast_tlb_mm_a15_erratum(vma->vm_mm);
|
||||
}
|
||||
|
||||
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
||||
|
@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
|||
on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
|
||||
} else
|
||||
local_flush_tlb_kernel_range(start, end);
|
||||
broadcast_tlb_a15_erratum();
|
||||
}
|
||||
|
||||
void flush_bp_all(void)
|
||||
|
|
|
@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
|
|||
lr, irq, vgic_cpu->vgic_lr[lr]);
|
||||
BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
|
||||
vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
|
||||
|
||||
goto out;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Try to use another LR for this interrupt */
|
||||
|
@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
|
|||
vgic_cpu->vgic_irq_lr_map[irq] = lr;
|
||||
set_bit(lr, vgic_cpu->lr_used);
|
||||
|
||||
out:
|
||||
if (!vgic_irq_is_edge(vcpu, irq))
|
||||
vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
|
||||
|
||||
|
@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
|
|||
|
||||
kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
|
||||
|
||||
/*
|
||||
* We do not need to take the distributor lock here, since the only
|
||||
* action we perform is clearing the irq_active_bit for an EOIed
|
||||
* level interrupt. There is a potential race with
|
||||
* the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we
|
||||
* check if the interrupt is already active. Two possibilities:
|
||||
*
|
||||
* - The queuing is occurring on the same vcpu: cannot happen,
|
||||
* as we're already in the context of this vcpu, and
|
||||
* executing the handler
|
||||
* - The interrupt has been migrated to another vcpu, and we
|
||||
* ignore this interrupt for this run. Big deal. It is still
|
||||
* pending though, and will get considered when this vcpu
|
||||
* exits.
|
||||
*/
|
||||
if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
|
||||
/*
|
||||
* Some level interrupts have been EOIed. Clear their
|
||||
|
@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
|
|||
} else {
|
||||
vgic_cpu_irq_clear(vcpu, irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* Despite being EOIed, the LR may not have
|
||||
* been marked as empty.
|
||||
*/
|
||||
set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
|
||||
vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
|
|||
}
|
||||
|
||||
/*
|
||||
* Sync back the VGIC state after a guest run. We do not really touch
|
||||
* the distributor here (the irq_pending_on_cpu bit is safe to set),
|
||||
* so there is no need for taking its lock.
|
||||
* Sync back the VGIC state after a guest run. The distributor lock is
|
||||
* needed so we don't get preempted in the middle of the state processing.
|
||||
*/
|
||||
static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
|
|||
|
||||
void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
|
||||
|
||||
if (!irqchip_in_kernel(vcpu->kvm))
|
||||
return;
|
||||
|
||||
spin_lock(&dist->lock);
|
||||
__kvm_vgic_sync_hwstate(vcpu);
|
||||
spin_unlock(&dist->lock);
|
||||
}
|
||||
|
||||
int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
|
||||
|
|
|
@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles)
|
|||
static void __timer_const_udelay(unsigned long xloops)
|
||||
{
|
||||
unsigned long long loops = xloops;
|
||||
loops *= loops_per_jiffy;
|
||||
loops *= arm_delay_ops.ticks_per_jiffy;
|
||||
__timer_delay(loops >> UDELAY_SHIFT);
|
||||
}
|
||||
|
||||
|
@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer)
|
|||
pr_info("Switching to timer-based delay loop\n");
|
||||
delay_timer = timer;
|
||||
lpj_fine = timer->freq / HZ;
|
||||
loops_per_jiffy = lpj_fine;
|
||||
|
||||
/* cpufreq may scale loops_per_jiffy, so keep a private copy */
|
||||
arm_delay_ops.ticks_per_jiffy = lpj_fine;
|
||||
arm_delay_ops.delay = __timer_delay;
|
||||
arm_delay_ops.const_udelay = __timer_const_udelay;
|
||||
arm_delay_ops.udelay = __timer_udelay;
|
||||
arm_delay_ops.const_clock = true;
|
||||
|
||||
delay_calibrated = true;
|
||||
} else {
|
||||
pr_info("Ignoring duplicate/late registration of read_current_timer delay\n");
|
||||
|
|
|
@ -22,19 +22,9 @@
|
|||
|
||||
static struct map_desc cns3xxx_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
|
||||
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
|
||||
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
|
||||
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
|
||||
.length = SZ_4K,
|
||||
.virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT,
|
||||
.pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE),
|
||||
.length = SZ_8K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
|
||||
|
|
|
@ -94,10 +94,10 @@
|
|||
#define RTC_INTR_STS_OFFSET 0x34
|
||||
|
||||
#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
|
||||
#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
|
||||
#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
|
||||
|
||||
#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
|
||||
#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
|
||||
#define CNS3XXX_PM_BASE_VIRT 0xFB001000
|
||||
|
||||
#define PM_CLK_GATE_OFFSET 0x00
|
||||
#define PM_SOFT_RST_OFFSET 0x04
|
||||
|
@ -109,7 +109,7 @@
|
|||
#define PM_PLL_HM_PD_OFFSET 0x1C
|
||||
|
||||
#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
|
||||
#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
|
||||
#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
|
||||
|
||||
#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
|
||||
#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
|
||||
|
@ -130,7 +130,7 @@
|
|||
#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
|
||||
|
||||
#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
|
||||
#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
|
||||
#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
|
||||
|
||||
#define TIMER1_COUNTER_OFFSET 0x00
|
||||
#define TIMER1_AUTO_RELOAD_OFFSET 0x04
|
||||
|
@ -227,16 +227,16 @@
|
|||
* Testchip peripheral and fpga gic regions
|
||||
*/
|
||||
#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
|
||||
#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
|
||||
#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
|
||||
|
||||
#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
|
||||
#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
|
||||
#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
|
||||
|
||||
#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
|
||||
#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
|
||||
#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600)
|
||||
|
||||
#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
|
||||
#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
|
||||
#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
|
||||
|
||||
#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
|
||||
#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
|
||||
|
|
|
@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr)
|
|||
|
||||
static inline void putc(int c)
|
||||
{
|
||||
/* Transmit fifo not full? */
|
||||
while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)
|
||||
;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 10000; i++) {
|
||||
/* Transmit fifo not full? */
|
||||
if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF))
|
||||
break;
|
||||
}
|
||||
|
||||
__raw_writeb(c, PHYS_UART_DATA);
|
||||
}
|
||||
|
|
|
@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *);
|
|||
|
||||
extern void imx_enable_cpu(int cpu, bool enable);
|
||||
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
|
||||
extern u32 imx_get_cpu_arg(int cpu);
|
||||
extern void imx_set_cpu_arg(int cpu, u32 arg);
|
||||
extern void v7_cpu_resume(void);
|
||||
extern u32 *pl310_get_save_ptr(void);
|
||||
#ifdef CONFIG_SMP
|
||||
|
|
|
@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void)
|
|||
void imx_cpu_die(unsigned int cpu)
|
||||
{
|
||||
cpu_enter_lowpower();
|
||||
/*
|
||||
* We use the cpu jumping argument register to sync with
|
||||
* imx_cpu_kill() which is running on cpu0 and waiting for
|
||||
* the register being cleared to kill the cpu.
|
||||
*/
|
||||
imx_set_cpu_arg(cpu, ~0);
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
int imx_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(50);
|
||||
|
||||
while (imx_get_cpu_arg(cpu) == 0)
|
||||
if (time_after(jiffies, timeout))
|
||||
return 0;
|
||||
imx_enable_cpu(cpu, false);
|
||||
imx_set_cpu_arg(cpu, 0);
|
||||
return 1;
|
||||
}
|
||||
|
|
|
@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
|
|||
src_base + SRC_GPR1 + cpu * 8);
|
||||
}
|
||||
|
||||
u32 imx_get_cpu_arg(int cpu)
|
||||
{
|
||||
cpu = cpu_logical_map(cpu);
|
||||
return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
|
||||
}
|
||||
|
||||
void imx_set_cpu_arg(int cpu, u32 arg)
|
||||
{
|
||||
cpu = cpu_logical_map(cpu);
|
||||
writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
|
||||
}
|
||||
|
||||
void imx_src_prepare_restart(void)
|
||||
{
|
||||
u32 val;
|
||||
|
|
|
@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = {
|
|||
|
||||
static struct mvsdio_platform_data guruplug_mvsdio_data = {
|
||||
/* unfortunately the CD signal has not been connected */
|
||||
.gpio_card_detect = -1,
|
||||
.gpio_write_protect = -1,
|
||||
};
|
||||
|
||||
static struct gpio_led guruplug_led_pins[] = {
|
||||
|
|
|
@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = {
|
|||
|
||||
static struct mvsdio_platform_data openrd_mvsdio_data = {
|
||||
.gpio_card_detect = 29, /* MPP29 used as SD card detect */
|
||||
.gpio_write_protect = -1,
|
||||
};
|
||||
|
||||
static unsigned int openrd_mpp_config[] __initdata = {
|
||||
|
|
|
@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = {
|
|||
|
||||
static struct mvsdio_platform_data rd88f6281_mvsdio_data = {
|
||||
.gpio_card_detect = 28,
|
||||
.gpio_write_protect = -1,
|
||||
};
|
||||
|
||||
static unsigned int rd88f6281_mpp_config[] __initdata = {
|
||||
|
|
|
@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles,
|
|||
{
|
||||
u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
|
||||
|
||||
writel_relaxed(0, event_base + TIMER_CLEAR);
|
||||
ctrl &= ~TIMER_ENABLE_EN;
|
||||
writel_relaxed(ctrl, event_base + TIMER_ENABLE);
|
||||
|
||||
writel_relaxed(ctrl, event_base + TIMER_CLEAR);
|
||||
writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
|
||||
writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
|
||||
return 0;
|
||||
|
|
|
@ -44,6 +44,8 @@
|
|||
|
||||
#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
|
||||
|
||||
#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
|
||||
|
||||
#define ACTIVE_DOORBELLS (8)
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(irq_controller_lock);
|
||||
|
@ -62,7 +64,7 @@ static void armada_370_xp_irq_mask(struct irq_data *d)
|
|||
#ifdef CONFIG_SMP
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
|
||||
if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
|
||||
if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
||||
writel(hwirq, main_int_base +
|
||||
ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
|
||||
else
|
||||
|
@ -79,7 +81,7 @@ static void armada_370_xp_irq_unmask(struct irq_data *d)
|
|||
#ifdef CONFIG_SMP
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
|
||||
if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
|
||||
if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
|
||||
writel(hwirq, main_int_base +
|
||||
ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
||||
else
|
||||
|
@ -147,7 +149,7 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
|
|||
writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
|
||||
irq_set_status_flags(virq, IRQ_LEVEL);
|
||||
|
||||
if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
|
||||
if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
|
||||
irq_set_percpu_devid(virq);
|
||||
irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
|
||||
handle_percpu_devid_irq);
|
||||
|
|
|
@ -41,8 +41,6 @@ static struct fb_videomode mx23evk_video_modes[] = {
|
|||
.lower_margin = 4,
|
||||
.hsync_len = 1,
|
||||
.vsync_len = 1,
|
||||
.sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
FB_SYNC_DOTCLK_FAILING_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -59,8 +57,6 @@ static struct fb_videomode mx28evk_video_modes[] = {
|
|||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
FB_SYNC_DOTCLK_FAILING_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -77,7 +73,6 @@ static struct fb_videomode m28evk_video_modes[] = {
|
|||
.lower_margin = 45,
|
||||
.hsync_len = 1,
|
||||
.vsync_len = 1,
|
||||
.sync = FB_SYNC_DATA_ENABLE_HIGH_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -94,9 +89,7 @@ static struct fb_videomode apx4devkit_video_modes[] = {
|
|||
.lower_margin = 13,
|
||||
.hsync_len = 48,
|
||||
.vsync_len = 3,
|
||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
|
||||
FB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
FB_SYNC_DOTCLK_FAILING_ACT,
|
||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -113,9 +106,7 @@ static struct fb_videomode apf28dev_video_modes[] = {
|
|||
.lower_margin = 0x15,
|
||||
.hsync_len = 64,
|
||||
.vsync_len = 4,
|
||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
|
||||
FB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
FB_SYNC_DOTCLK_FAILING_ACT,
|
||||
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -132,7 +123,6 @@ static struct fb_videomode cfa10049_video_modes[] = {
|
|||
.lower_margin = 2,
|
||||
.hsync_len = 15,
|
||||
.vsync_len = 15,
|
||||
.sync = FB_SYNC_DATA_ENABLE_HIGH_ACT
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -259,6 +249,8 @@ static void __init imx23_evk_init(void)
|
|||
mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
|
||||
mxsfb_pdata.default_bpp = 32;
|
||||
mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
|
||||
mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
MXSFB_SYNC_DOTCLK_FAILING_ACT;
|
||||
}
|
||||
|
||||
static inline void enable_clk_enet_out(void)
|
||||
|
@ -278,6 +270,8 @@ static void __init imx28_evk_init(void)
|
|||
mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
|
||||
mxsfb_pdata.default_bpp = 32;
|
||||
mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
|
||||
mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
MXSFB_SYNC_DOTCLK_FAILING_ACT;
|
||||
|
||||
mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
|
||||
}
|
||||
|
@ -297,6 +291,7 @@ static void __init m28evk_init(void)
|
|||
mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
|
||||
mxsfb_pdata.default_bpp = 16;
|
||||
mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
|
||||
mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
|
||||
}
|
||||
|
||||
static void __init sc_sps1_init(void)
|
||||
|
@ -322,6 +317,8 @@ static void __init apx4devkit_init(void)
|
|||
mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
|
||||
mxsfb_pdata.default_bpp = 32;
|
||||
mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
|
||||
mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
MXSFB_SYNC_DOTCLK_FAILING_ACT;
|
||||
}
|
||||
|
||||
#define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
|
||||
|
@ -407,6 +404,7 @@ static void __init cfa10049_init(void)
|
|||
mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
|
||||
mxsfb_pdata.default_bpp = 32;
|
||||
mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
|
||||
mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
|
||||
}
|
||||
|
||||
static void __init cfa10037_init(void)
|
||||
|
@ -423,6 +421,8 @@ static void __init apf28_init(void)
|
|||
mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
|
||||
mxsfb_pdata.default_bpp = 16;
|
||||
mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
|
||||
mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
|
||||
MXSFB_SYNC_DOTCLK_FAILING_ACT;
|
||||
}
|
||||
|
||||
static void __init mxs_machine_init(void)
|
||||
|
|
|
@ -538,15 +538,6 @@ static struct clk usb_hhc_ck16xx = {
|
|||
};
|
||||
|
||||
static struct clk usb_dc_ck = {
|
||||
.name = "usb_dc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
.rate = 48000000,
|
||||
.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
|
||||
.enable_bit = USB_REQ_EN_SHIFT,
|
||||
};
|
||||
|
||||
static struct clk usb_dc_ck7xx = {
|
||||
.name = "usb_dc_ck",
|
||||
.ops = &clkops_generic,
|
||||
/* Direct from ULPD, no parent */
|
||||
|
@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = {
|
|||
CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
|
||||
CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
|
||||
CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
|
||||
CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
|
||||
CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
|
||||
|
|
|
@ -52,6 +52,13 @@
|
|||
*/
|
||||
#define OMAP4_DPLL_ABE_DEFFREQ 98304000
|
||||
|
||||
/*
|
||||
* OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
|
||||
* "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
|
||||
* locked frequency for the USB DPLL is 960MHz.
|
||||
*/
|
||||
#define OMAP4_DPLL_USB_DEFFREQ 960000000
|
||||
|
||||
/* Root clocks */
|
||||
|
||||
DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
|
||||
|
@ -1011,6 +1018,10 @@ DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
|
|||
OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
|
||||
hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
|
||||
|
||||
DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
|
||||
OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
|
||||
OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
|
||||
|
||||
DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
|
||||
OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
|
||||
OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
|
||||
|
@ -1538,6 +1549,7 @@ static struct omap_clk omap44xx_clks[] = {
|
|||
CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
|
||||
CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
|
||||
CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
|
||||
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
|
||||
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
|
||||
CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
|
||||
CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
|
||||
|
@ -1705,5 +1717,13 @@ int __init omap4xxx_clk_init(void)
|
|||
if (rc)
|
||||
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
|
||||
|
||||
/*
|
||||
* Lock USB DPLL on OMAP4 devices so that the L3INIT power
|
||||
* domain can transition to retention state when not in use.
|
||||
*/
|
||||
rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
|
||||
if (rc)
|
||||
pr_err("%s: failed to configure USB DPLL!\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -293,5 +293,8 @@ extern void omap_reserve(void);
|
|||
struct omap_hwmod;
|
||||
extern int omap_dss_reset(struct omap_hwmod *);
|
||||
|
||||
/* SoC specific clock initializer */
|
||||
extern int (*omap_clk_init)(void);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
|
||||
|
|
|
@ -54,6 +54,12 @@
|
|||
#include "prm3xxx.h"
|
||||
#include "prm44xx.h"
|
||||
|
||||
/*
|
||||
* omap_clk_init: points to a function that does the SoC-specific
|
||||
* clock initializations
|
||||
*/
|
||||
int (*omap_clk_init)(void);
|
||||
|
||||
/*
|
||||
* The machine specific code may provide the extra mapping besides the
|
||||
* default mapping provided here.
|
||||
|
@ -397,7 +403,7 @@ void __init omap2420_init_early(void)
|
|||
omap242x_clockdomains_init();
|
||||
omap2420_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap2420_clk_init();
|
||||
omap_clk_init = omap2420_clk_init;
|
||||
}
|
||||
|
||||
void __init omap2420_init_late(void)
|
||||
|
@ -427,7 +433,7 @@ void __init omap2430_init_early(void)
|
|||
omap243x_clockdomains_init();
|
||||
omap2430_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap2430_clk_init();
|
||||
omap_clk_init = omap2430_clk_init;
|
||||
}
|
||||
|
||||
void __init omap2430_init_late(void)
|
||||
|
@ -462,7 +468,7 @@ void __init omap3_init_early(void)
|
|||
omap3xxx_clockdomains_init();
|
||||
omap3xxx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap3xxx_clk_init();
|
||||
omap_clk_init = omap3xxx_clk_init;
|
||||
}
|
||||
|
||||
void __init omap3430_init_early(void)
|
||||
|
@ -500,7 +506,7 @@ void __init ti81xx_init_early(void)
|
|||
omap3xxx_clockdomains_init();
|
||||
omap3xxx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap3xxx_clk_init();
|
||||
omap_clk_init = omap3xxx_clk_init;
|
||||
}
|
||||
|
||||
void __init omap3_init_late(void)
|
||||
|
@ -568,7 +574,7 @@ void __init am33xx_init_early(void)
|
|||
am33xx_clockdomains_init();
|
||||
am33xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
am33xx_clk_init();
|
||||
omap_clk_init = am33xx_clk_init;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -593,7 +599,7 @@ void __init omap4430_init_early(void)
|
|||
omap44xx_clockdomains_init();
|
||||
omap44xx_hwmod_init();
|
||||
omap_hwmod_init_postsetup();
|
||||
omap4xxx_clk_init();
|
||||
omap_clk_init = omap4xxx_clk_init;
|
||||
}
|
||||
|
||||
void __init omap4430_init_late(void)
|
||||
|
|
|
@ -1368,7 +1368,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
|
|||
}
|
||||
|
||||
if (sf & SYSC_HAS_MIDLEMODE) {
|
||||
if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
|
||||
if (oh->flags & HWMOD_FORCE_MSTANDBY) {
|
||||
idlemode = HWMOD_IDLEMODE_FORCE;
|
||||
} else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
|
||||
idlemode = HWMOD_IDLEMODE_NO;
|
||||
} else {
|
||||
if (sf & SYSC_HAS_ENAWAKEUP)
|
||||
|
@ -1440,7 +1442,8 @@ static void _idle_sysc(struct omap_hwmod *oh)
|
|||
}
|
||||
|
||||
if (sf & SYSC_HAS_MIDLEMODE) {
|
||||
if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
|
||||
if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
|
||||
(oh->flags & HWMOD_FORCE_MSTANDBY)) {
|
||||
idlemode = HWMOD_IDLEMODE_FORCE;
|
||||
} else {
|
||||
if (sf & SYSC_HAS_ENAWAKEUP)
|
||||
|
|
|
@ -427,8 +427,8 @@ struct omap_hwmod_omap4_prcm {
|
|||
*
|
||||
* HWMOD_SWSUP_SIDLE: omap_hwmod code should manually bring module in and out
|
||||
* of idle, rather than relying on module smart-idle
|
||||
* HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
|
||||
* of standby, rather than relying on module smart-standby
|
||||
* HWMOD_SWSUP_MSTANDBY: omap_hwmod code should manually bring module in and
|
||||
* out of standby, rather than relying on module smart-standby
|
||||
* HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
|
||||
* SDRAM controller, etc. XXX probably belongs outside the main hwmod file
|
||||
* XXX Should be HWMOD_SETUP_NO_RESET
|
||||
|
@ -459,6 +459,10 @@ struct omap_hwmod_omap4_prcm {
|
|||
* correctly, or this is being abused to deal with some PM latency
|
||||
* issues -- but we're currently suffering from a shortage of
|
||||
* folks who are able to track these issues down properly.
|
||||
* HWMOD_FORCE_MSTANDBY: Always keep MIDLEMODE bits cleared so that device
|
||||
* is kept in force-standby mode. Failing to do so causes PM problems
|
||||
* with musb on OMAP3630 at least. Note that musb has a dedicated register
|
||||
* to control MSTANDBY signal when MIDLEMODE is set to force-standby.
|
||||
*/
|
||||
#define HWMOD_SWSUP_SIDLE (1 << 0)
|
||||
#define HWMOD_SWSUP_MSTANDBY (1 << 1)
|
||||
|
@ -471,6 +475,7 @@ struct omap_hwmod_omap4_prcm {
|
|||
#define HWMOD_16BIT_REG (1 << 8)
|
||||
#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
|
||||
#define HWMOD_BLOCK_WFI (1 << 10)
|
||||
#define HWMOD_FORCE_MSTANDBY (1 << 11)
|
||||
|
||||
/*
|
||||
* omap_hwmod._int_flags definitions
|
||||
|
|
|
@ -1707,9 +1707,14 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
|
|||
* Erratum ID: i479 idle_req / idle_ack mechanism potentially
|
||||
* broken when autoidle is enabled
|
||||
* workaround is to disable the autoidle bit at module level.
|
||||
*
|
||||
* Enabling the device in any other MIDLEMODE setting but force-idle
|
||||
* causes core_pwrdm not enter idle states at least on OMAP3630.
|
||||
* Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
|
||||
* signal when MIDLEMODE is set to force-idle.
|
||||
*/
|
||||
.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
|
||||
| HWMOD_SWSUP_MSTANDBY,
|
||||
| HWMOD_FORCE_MSTANDBY,
|
||||
};
|
||||
|
||||
/* usb_otg_hs */
|
||||
|
|
|
@ -2714,6 +2714,10 @@ static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
|
|||
{ }
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
|
||||
{ .role = "48mhz", .clk = "ocp2scp_usb_phy_phy_48m" },
|
||||
};
|
||||
|
||||
/* ocp2scp_usb_phy */
|
||||
static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
|
||||
.name = "ocp2scp_usb_phy",
|
||||
|
@ -2728,6 +2732,8 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
|
|||
},
|
||||
},
|
||||
.dev_attr = ocp2scp_dev_attr,
|
||||
.opt_clks = ocp2scp_usb_phy_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
|
@ -547,6 +547,8 @@ static inline void __init realtime_counter_init(void)
|
|||
clksrc_nr, clksrc_src) \
|
||||
void __init omap##name##_gptimer_timer_init(void) \
|
||||
{ \
|
||||
if (omap_clk_init) \
|
||||
omap_clk_init(); \
|
||||
omap_dmtimer_init(); \
|
||||
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
|
||||
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
|
||||
|
@ -556,6 +558,8 @@ void __init omap##name##_gptimer_timer_init(void) \
|
|||
clksrc_nr, clksrc_src) \
|
||||
void __init omap##name##_sync32k_timer_init(void) \
|
||||
{ \
|
||||
if (omap_clk_init) \
|
||||
omap_clk_init(); \
|
||||
omap_dmtimer_init(); \
|
||||
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
|
||||
/* Enable the use of clocksource="gp_timer" kernel parameter */ \
|
||||
|
|
|
@ -81,7 +81,6 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
|
|||
#endif
|
||||
|
||||
struct mmci_platform_data mop500_sdi0_data = {
|
||||
.ios_handler = mop500_sdi0_ios_handler,
|
||||
.ocr_mask = MMC_VDD_29_30,
|
||||
.f_max = 50000000,
|
||||
.capabilities = MMC_CAP_4_BIT_DATA |
|
||||
|
|
|
@ -12,6 +12,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/platform_data/i2c-nomadik.h>
|
||||
|
@ -439,6 +440,15 @@ static void mop500_prox_deactivate(struct device *dev)
|
|||
regulator_put(prox_regulator);
|
||||
}
|
||||
|
||||
void mop500_snowball_ethernet_clock_enable(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
clk = clk_get_sys("fsmc", NULL);
|
||||
if (!IS_ERR(clk))
|
||||
clk_prepare_enable(clk);
|
||||
}
|
||||
|
||||
static struct cryp_platform_data u8500_cryp1_platform_data = {
|
||||
.mem_to_engine = {
|
||||
.dir = STEDMA40_MEM_TO_PERIPH,
|
||||
|
@ -683,6 +693,8 @@ static void __init snowball_init_machine(void)
|
|||
mop500_audio_init(parent);
|
||||
mop500_uart_init(parent);
|
||||
|
||||
mop500_snowball_ethernet_clock_enable();
|
||||
|
||||
/* This board has full regulator constraints */
|
||||
regulator_has_full_constraints();
|
||||
}
|
||||
|
|
|
@ -104,6 +104,7 @@ void __init mop500_pinmaps_init(void);
|
|||
void __init snowball_pinmaps_init(void);
|
||||
void __init hrefv60_pinmaps_init(void);
|
||||
void mop500_audio_init(struct device *parent);
|
||||
void mop500_snowball_ethernet_clock_enable(void);
|
||||
|
||||
int __init mop500_uib_init(void);
|
||||
void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
|
||||
|
|
|
@ -312,9 +312,10 @@ static void __init u8500_init_machine(void)
|
|||
/* Pinmaps must be in place before devices register */
|
||||
if (of_machine_is_compatible("st-ericsson,mop500"))
|
||||
mop500_pinmaps_init();
|
||||
else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
|
||||
else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
|
||||
snowball_pinmaps_init();
|
||||
else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
|
||||
mop500_snowball_ethernet_clock_enable();
|
||||
} else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
|
||||
hrefv60_pinmaps_init();
|
||||
else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
|
||||
/* TODO: Add pinmaps for ccu9540 board. */
|
||||
|
|
|
@ -299,7 +299,7 @@ static void l2x0_unlock(u32 cache_id)
|
|||
int lockregs;
|
||||
int i;
|
||||
|
||||
switch (cache_id) {
|
||||
switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
|
||||
case L2X0_CACHE_ID_PART_L310:
|
||||
lockregs = 8;
|
||||
break;
|
||||
|
@ -333,15 +333,14 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
|
|||
if (cache_id_part_number_from_dt)
|
||||
cache_id = cache_id_part_number_from_dt;
|
||||
else
|
||||
cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID)
|
||||
& L2X0_CACHE_ID_PART_MASK;
|
||||
cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
|
||||
aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
|
||||
|
||||
aux &= aux_mask;
|
||||
aux |= aux_val;
|
||||
|
||||
/* Determine the number of ways */
|
||||
switch (cache_id) {
|
||||
switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
|
||||
case L2X0_CACHE_ID_PART_L310:
|
||||
if (aux & (1 << 16))
|
||||
ways = 16;
|
||||
|
@ -725,7 +724,6 @@ static const struct l2x0_of_data pl310_data = {
|
|||
.flush_all = l2x0_flush_all,
|
||||
.inv_all = l2x0_inv_all,
|
||||
.disable = l2x0_disable,
|
||||
.set_debug = pl310_set_debug,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -814,9 +812,8 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
|
|||
data->save();
|
||||
|
||||
of_init = true;
|
||||
l2x0_init(l2x0_base, aux_val, aux_mask);
|
||||
|
||||
memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
|
||||
l2x0_init(l2x0_base, aux_val, aux_mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -48,7 +48,7 @@ static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
|
|||
static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
|
||||
static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
|
||||
|
||||
static DEFINE_PER_CPU(atomic64_t, active_asids);
|
||||
DEFINE_PER_CPU(atomic64_t, active_asids);
|
||||
static DEFINE_PER_CPU(u64, reserved_asids);
|
||||
static cpumask_t tlb_flush_pending;
|
||||
|
||||
|
@ -215,6 +215,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
|
|||
if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
|
||||
local_flush_bp_all();
|
||||
local_flush_tlb_all();
|
||||
dummy_flush_tlb_a15_erratum();
|
||||
}
|
||||
|
||||
atomic64_set(&per_cpu(active_asids, cpu), asid);
|
||||
|
|
|
@ -598,39 +598,60 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
|
|||
} while (pte++, addr += PAGE_SIZE, addr != end);
|
||||
}
|
||||
|
||||
static void __init alloc_init_section(pud_t *pud, unsigned long addr,
|
||||
static void __init map_init_section(pmd_t *pmd, unsigned long addr,
|
||||
unsigned long end, phys_addr_t phys,
|
||||
const struct mem_type *type)
|
||||
{
|
||||
#ifndef CONFIG_ARM_LPAE
|
||||
/*
|
||||
* In classic MMU format, puds and pmds are folded in to
|
||||
* the pgds. pmd_offset gives the PGD entry. PGDs refer to a
|
||||
* group of L1 entries making up one logical pointer to
|
||||
* an L2 table (2MB), where as PMDs refer to the individual
|
||||
* L1 entries (1MB). Hence increment to get the correct
|
||||
* offset for odd 1MB sections.
|
||||
* (See arch/arm/include/asm/pgtable-2level.h)
|
||||
*/
|
||||
if (addr & SECTION_SIZE)
|
||||
pmd++;
|
||||
#endif
|
||||
do {
|
||||
*pmd = __pmd(phys | type->prot_sect);
|
||||
phys += SECTION_SIZE;
|
||||
} while (pmd++, addr += SECTION_SIZE, addr != end);
|
||||
|
||||
flush_pmd_entry(pmd);
|
||||
}
|
||||
|
||||
static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
|
||||
unsigned long end, phys_addr_t phys,
|
||||
const struct mem_type *type)
|
||||
{
|
||||
pmd_t *pmd = pmd_offset(pud, addr);
|
||||
unsigned long next;
|
||||
|
||||
/*
|
||||
* Try a section mapping - end, addr and phys must all be aligned
|
||||
* to a section boundary. Note that PMDs refer to the individual
|
||||
* L1 entries, whereas PGDs refer to a group of L1 entries making
|
||||
* up one logical pointer to an L2 table.
|
||||
*/
|
||||
if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) {
|
||||
pmd_t *p = pmd;
|
||||
|
||||
#ifndef CONFIG_ARM_LPAE
|
||||
if (addr & SECTION_SIZE)
|
||||
pmd++;
|
||||
#endif
|
||||
|
||||
do {
|
||||
*pmd = __pmd(phys | type->prot_sect);
|
||||
phys += SECTION_SIZE;
|
||||
} while (pmd++, addr += SECTION_SIZE, addr != end);
|
||||
|
||||
flush_pmd_entry(p);
|
||||
} else {
|
||||
do {
|
||||
/*
|
||||
* No need to loop; pte's aren't interested in the
|
||||
* individual L1 entries.
|
||||
* With LPAE, we must loop over to map
|
||||
* all the pmds for the given range.
|
||||
*/
|
||||
alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
|
||||
}
|
||||
next = pmd_addr_end(addr, end);
|
||||
|
||||
/*
|
||||
* Try a section mapping - addr, next and phys must all be
|
||||
* aligned to a section boundary.
|
||||
*/
|
||||
if (type->prot_sect &&
|
||||
((addr | next | phys) & ~SECTION_MASK) == 0) {
|
||||
map_init_section(pmd, addr, next, phys, type);
|
||||
} else {
|
||||
alloc_init_pte(pmd, addr, next,
|
||||
__phys_to_pfn(phys), type);
|
||||
}
|
||||
|
||||
phys += next - addr;
|
||||
|
||||
} while (pmd++, addr = next, addr != end);
|
||||
}
|
||||
|
||||
static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
|
||||
|
@ -641,7 +662,7 @@ static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
|
|||
|
||||
do {
|
||||
next = pud_addr_end(addr, end);
|
||||
alloc_init_section(pud, addr, next, phys, type);
|
||||
alloc_init_pmd(pud, addr, next, phys, type);
|
||||
phys += next - addr;
|
||||
} while (pud++, addr = next, addr != end);
|
||||
}
|
||||
|
|
|
@ -420,7 +420,7 @@ __v7_pj4b_proc_info:
|
|||
__v7_ca7mp_proc_info:
|
||||
.long 0x410fc070
|
||||
.long 0xff0ffff0
|
||||
__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
|
||||
__v7_proc __v7_ca7mp_setup
|
||||
.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
|
||||
|
||||
/*
|
||||
|
@ -430,9 +430,24 @@ __v7_ca7mp_proc_info:
|
|||
__v7_ca15mp_proc_info:
|
||||
.long 0x410fc0f0
|
||||
.long 0xff0ffff0
|
||||
__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
|
||||
__v7_proc __v7_ca15mp_setup
|
||||
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
|
||||
|
||||
/*
|
||||
* Qualcomm Inc. Krait processors.
|
||||
*/
|
||||
.type __krait_proc_info, #object
|
||||
__krait_proc_info:
|
||||
.long 0x510f0400 @ Required ID value
|
||||
.long 0xff0ffc00 @ Mask for ID
|
||||
/*
|
||||
* Some Krait processors don't indicate support for SDIV and UDIV
|
||||
* instructions in the ARM instruction set, even though they actually
|
||||
* do support them.
|
||||
*/
|
||||
__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
|
||||
.size __krait_proc_info, . - __krait_proc_info
|
||||
|
||||
/*
|
||||
* Match any ARMv7 processor core.
|
||||
*/
|
||||
|
|
|
@ -261,7 +261,7 @@ static void __init create_mapping(phys_addr_t phys, unsigned long virt,
|
|||
void __iomem * __init early_io_map(phys_addr_t phys, unsigned long virt)
|
||||
{
|
||||
unsigned long size, mask;
|
||||
bool page64k = IS_ENABLED(ARM64_64K_PAGES);
|
||||
bool page64k = IS_ENABLED(CONFIG_ARM64_64K_PAGES);
|
||||
pgd_t *pgd;
|
||||
pud_t *pud;
|
||||
pmd_t *pmd;
|
||||
|
|
|
@ -291,7 +291,6 @@ cpu_idle (void)
|
|||
}
|
||||
|
||||
if (!need_resched()) {
|
||||
void (*idle)(void);
|
||||
#ifdef CONFIG_SMP
|
||||
min_xtp();
|
||||
#endif
|
||||
|
@ -299,9 +298,7 @@ cpu_idle (void)
|
|||
if (mark_idle)
|
||||
(*mark_idle)(1);
|
||||
|
||||
if (!idle)
|
||||
idle = default_idle;
|
||||
(*idle)();
|
||||
default_idle();
|
||||
if (mark_idle)
|
||||
(*mark_idle)(0);
|
||||
#ifdef CONFIG_SMP
|
||||
|
|
|
@ -18,7 +18,7 @@ config MIPS
|
|||
select HAVE_KRETPROBES
|
||||
select HAVE_DEBUG_KMEMLEAK
|
||||
select ARCH_BINFMT_ELF_RANDOMIZE_PIE
|
||||
select HAVE_ARCH_TRANSPARENT_HUGEPAGE
|
||||
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
|
||||
select RTC_LIB if !MACH_LOONGSON
|
||||
select GENERIC_ATOMIC64 if !64BIT
|
||||
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
|
||||
|
@ -657,7 +657,7 @@ config SNI_RM
|
|||
bool "SNI RM200/300/400"
|
||||
select FW_ARC if CPU_LITTLE_ENDIAN
|
||||
select FW_ARC32 if CPU_LITTLE_ENDIAN
|
||||
select SNIPROM if CPU_BIG_ENDIAN
|
||||
select FW_SNIPROM if CPU_BIG_ENDIAN
|
||||
select ARCH_MAY_HAVE_PC_FDC
|
||||
select BOOT_ELF32
|
||||
select CEVT_R4K
|
||||
|
@ -1144,7 +1144,7 @@ config DEFAULT_SGI_PARTITION
|
|||
config FW_ARC32
|
||||
bool
|
||||
|
||||
config SNIPROM
|
||||
config FW_SNIPROM
|
||||
bool
|
||||
|
||||
config BOOT_ELF32
|
||||
|
@ -1493,7 +1493,6 @@ config CPU_XLP
|
|||
select CPU_SUPPORTS_32BIT_KERNEL
|
||||
select CPU_SUPPORTS_64BIT_KERNEL
|
||||
select CPU_SUPPORTS_HIGHMEM
|
||||
select CPU_HAS_LLSC
|
||||
select WEAK_ORDERING
|
||||
select WEAK_REORDERING_BEYOND_LLSC
|
||||
select CPU_HAS_PREFETCH
|
||||
|
|
|
@ -745,10 +745,7 @@ void __init board_prom_init(void)
|
|||
strcpy(cfe_version, "unknown");
|
||||
printk(KERN_INFO PFX "CFE version: %s\n", cfe_version);
|
||||
|
||||
if (bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET)) {
|
||||
printk(KERN_ERR PFX "invalid nvram checksum\n");
|
||||
return;
|
||||
}
|
||||
bcm63xx_nvram_init(boot_addr + BCM963XX_NVRAM_OFFSET);
|
||||
|
||||
board_name = bcm63xx_nvram_get_name();
|
||||
/* find board by name */
|
||||
|
|
|
@ -38,7 +38,7 @@ struct bcm963xx_nvram {
|
|||
static struct bcm963xx_nvram nvram;
|
||||
static int mac_addr_used;
|
||||
|
||||
int __init bcm63xx_nvram_init(void *addr)
|
||||
void __init bcm63xx_nvram_init(void *addr)
|
||||
{
|
||||
unsigned int check_len;
|
||||
u32 crc, expected_crc;
|
||||
|
@ -60,9 +60,8 @@ int __init bcm63xx_nvram_init(void *addr)
|
|||
crc = crc32_le(~0, (u8 *)&nvram, check_len);
|
||||
|
||||
if (crc != expected_crc)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
pr_warn("nvram checksum failed, contents may be invalid (expected %08x, got %08x)\n",
|
||||
expected_crc, crc);
|
||||
}
|
||||
|
||||
u8 *bcm63xx_nvram_get_name(void)
|
||||
|
|
|
@ -157,4 +157,4 @@ int __init bcm63xx_register_devices(void)
|
|||
return board_register_devices();
|
||||
}
|
||||
|
||||
device_initcall(bcm63xx_register_devices);
|
||||
arch_initcall(bcm63xx_register_devices);
|
||||
|
|
|
@ -174,7 +174,10 @@ static int octeon_kexec_prepare(struct kimage *image)
|
|||
|
||||
static void octeon_generic_shutdown(void)
|
||||
{
|
||||
int cpu, i;
|
||||
int i;
|
||||
#ifdef CONFIG_SMP
|
||||
int cpu;
|
||||
#endif
|
||||
struct cvmx_bootmem_desc *bootmem_desc;
|
||||
void *named_block_array_ptr;
|
||||
|
||||
|
|
|
@ -9,10 +9,8 @@
|
|||
*
|
||||
* Initialized the local nvram copy from the target address and checks
|
||||
* its checksum.
|
||||
*
|
||||
* Returns 0 on success.
|
||||
*/
|
||||
int __init bcm63xx_nvram_init(void *nvram);
|
||||
void bcm63xx_nvram_init(void *nvram);
|
||||
|
||||
/**
|
||||
* bcm63xx_nvram_get_name() - returns the board name according to nvram
|
||||
|
|
|
@ -28,11 +28,7 @@
|
|||
/* #define cpu_has_prefetch ? */
|
||||
#define cpu_has_mcheck 1
|
||||
/* #define cpu_has_ejtag ? */
|
||||
#ifdef CONFIG_CPU_HAS_LLSC
|
||||
#define cpu_has_llsc 1
|
||||
#else
|
||||
#define cpu_has_llsc 0
|
||||
#endif
|
||||
/* #define cpu_has_vtag_icache ? */
|
||||
/* #define cpu_has_dc_aliases ? */
|
||||
/* #define cpu_has_ic_fills_f_dc ? */
|
||||
|
|
|
@ -1166,7 +1166,10 @@ do { \
|
|||
unsigned int __dspctl; \
|
||||
\
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" rddsp %0, %x1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (__dspctl) \
|
||||
: "i" (mask)); \
|
||||
__dspctl; \
|
||||
|
@ -1175,30 +1178,198 @@ do { \
|
|||
#define wrdsp(val, mask) \
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" wrdsp %0, %x1 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (val), "i" (mask)); \
|
||||
} while (0)
|
||||
|
||||
#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
|
||||
#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
|
||||
#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
|
||||
#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
|
||||
#define mflo0() \
|
||||
({ \
|
||||
long mflo0; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mflo %0, $ac0 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mflo0)); \
|
||||
mflo0; \
|
||||
})
|
||||
|
||||
#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
|
||||
#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
|
||||
#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
|
||||
#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
|
||||
#define mflo1() \
|
||||
({ \
|
||||
long mflo1; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mflo %0, $ac1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mflo1)); \
|
||||
mflo1; \
|
||||
})
|
||||
|
||||
#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
|
||||
#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
|
||||
#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
|
||||
#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
|
||||
#define mflo2() \
|
||||
({ \
|
||||
long mflo2; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mflo %0, $ac2 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mflo2)); \
|
||||
mflo2; \
|
||||
})
|
||||
|
||||
#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
|
||||
#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
|
||||
#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
|
||||
#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
|
||||
#define mflo3() \
|
||||
({ \
|
||||
long mflo3; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mflo %0, $ac3 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mflo3)); \
|
||||
mflo3; \
|
||||
})
|
||||
|
||||
#define mfhi0() \
|
||||
({ \
|
||||
long mfhi0; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mfhi %0, $ac0 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mfhi0)); \
|
||||
mfhi0; \
|
||||
})
|
||||
|
||||
#define mfhi1() \
|
||||
({ \
|
||||
long mfhi1; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mfhi %0, $ac1 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mfhi1)); \
|
||||
mfhi1; \
|
||||
})
|
||||
|
||||
#define mfhi2() \
|
||||
({ \
|
||||
long mfhi2; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mfhi %0, $ac2 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mfhi2)); \
|
||||
mfhi2; \
|
||||
})
|
||||
|
||||
#define mfhi3() \
|
||||
({ \
|
||||
long mfhi3; \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mfhi %0, $ac3 \n" \
|
||||
" .set pop \n" \
|
||||
: "=r" (mfhi3)); \
|
||||
mfhi3; \
|
||||
})
|
||||
|
||||
|
||||
#define mtlo0(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mtlo %0, $ac0 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mtlo1(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mtlo %0, $ac1 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mtlo2(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mtlo %0, $ac2 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mtlo3(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mtlo %0, $ac3 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mthi0(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mthi %0, $ac0 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mthi1(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mthi %0, $ac1 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mthi2(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mthi %0, $ac2 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#define mthi3(x) \
|
||||
({ \
|
||||
__asm__( \
|
||||
" .set push \n" \
|
||||
" .set dsp \n" \
|
||||
" mthi %0, $ac3 \n" \
|
||||
" .set pop \n" \
|
||||
: \
|
||||
: "r" (x)); \
|
||||
})
|
||||
|
||||
#else
|
||||
|
||||
|
|
|
@ -21,6 +21,6 @@
|
|||
#include <asm/sigcontext.h>
|
||||
#include <asm/siginfo.h>
|
||||
|
||||
#define __ARCH_HAS_ODD_SIGACTION
|
||||
#define __ARCH_HAS_IRIX_SIGACTION
|
||||
|
||||
#endif /* _ASM_SIGNAL_H */
|
||||
|
|
|
@ -72,6 +72,12 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
|
|||
*
|
||||
* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
|
||||
* Unix names RESETHAND and NODEFER respectively.
|
||||
*
|
||||
* SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
|
||||
* supported its use and no libc was using it, so the entire sa-restorer
|
||||
* functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
|
||||
* retaining only the SA_RESTORER definition as a reminder to avoid
|
||||
* accidental reuse of the mask bit.
|
||||
*/
|
||||
#define SA_ONSTACK 0x08000000
|
||||
#define SA_RESETHAND 0x80000000
|
||||
|
@ -84,8 +90,6 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */
|
|||
#define SA_NOMASK SA_NODEFER
|
||||
#define SA_ONESHOT SA_RESETHAND
|
||||
|
||||
#define SA_RESTORER 0x04000000 /* Only for o32 */
|
||||
|
||||
#define MINSIGSTKSZ 2048
|
||||
#define SIGSTKSZ 8192
|
||||
|
||||
|
|
|
@ -100,29 +100,16 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
|
|||
obj-$(CONFIG_JUMP_LABEL) += jump_label.o
|
||||
|
||||
#
|
||||
# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
|
||||
# to enable DSP assembler support here even if the MIPS Release 2 CPU we
|
||||
# are targetting does not support DSP because all code-paths making use of
|
||||
# it properly check that the running CPU *actually does* support these
|
||||
# instructions.
|
||||
# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
|
||||
# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
|
||||
# here because the compiler may use DSP ASE instructions (such as lwx) in
|
||||
# code paths where we cannot check that the CPU we are running on supports it.
|
||||
# Proper abstraction using HAVE_AS_DSP and macros is done in
|
||||
# arch/mips/include/asm/mipsregs.h.
|
||||
#
|
||||
ifeq ($(CONFIG_CPU_MIPSR2), y)
|
||||
CFLAGS_DSP = -DHAVE_AS_DSP
|
||||
|
||||
#
|
||||
# Check if assembler supports DSP ASE
|
||||
#
|
||||
ifeq ($(call cc-option-yn,-mdsp), y)
|
||||
CFLAGS_DSP += -mdsp
|
||||
endif
|
||||
|
||||
#
|
||||
# Check if assembler supports DSP ASE Rev2
|
||||
#
|
||||
ifeq ($(call cc-option-yn,-mdspr2), y)
|
||||
CFLAGS_DSP += -mdspr2
|
||||
endif
|
||||
|
||||
CFLAGS_signal.o = $(CFLAGS_DSP)
|
||||
CFLAGS_signal32.o = $(CFLAGS_DSP)
|
||||
CFLAGS_process.o = $(CFLAGS_DSP)
|
||||
|
|
|
@ -580,6 +580,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
c->tlbsize = 48;
|
||||
break;
|
||||
case PRID_IMP_VR41XX:
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS;
|
||||
c->tlbsize = 32;
|
||||
switch (c->processor_id & 0xf0) {
|
||||
case PRID_REV_VR4111:
|
||||
c->cputype = CPU_VR4111;
|
||||
|
@ -604,6 +607,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
__cpu_name[cpu] = "NEC VR4131";
|
||||
} else {
|
||||
c->cputype = CPU_VR4133;
|
||||
c->options |= MIPS_CPU_LLSC;
|
||||
__cpu_name[cpu] = "NEC VR4133";
|
||||
}
|
||||
break;
|
||||
|
@ -613,9 +617,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||
__cpu_name[cpu] = "NEC Vr41xx";
|
||||
break;
|
||||
}
|
||||
set_isa(c, MIPS_CPU_ISA_III);
|
||||
c->options = R4K_OPTS;
|
||||
c->tlbsize = 32;
|
||||
break;
|
||||
case PRID_IMP_R4300:
|
||||
c->cputype = CPU_R4300;
|
||||
|
@ -1226,10 +1227,8 @@ __cpuinit void cpu_probe(void)
|
|||
if (c->options & MIPS_CPU_FPU) {
|
||||
c->fpu_id = cpu_get_fpu_id();
|
||||
|
||||
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
||||
c->isa_level == MIPS_CPU_ISA_M32R2 ||
|
||||
c->isa_level == MIPS_CPU_ISA_M64R1 ||
|
||||
c->isa_level == MIPS_CPU_ISA_M64R2) {
|
||||
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
|
||||
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
|
||||
if (c->fpu_id & MIPS_FPIR_3D)
|
||||
c->ases |= MIPS_ASE_MIPS3D;
|
||||
}
|
||||
|
|
|
@ -171,7 +171,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
|
|||
err = compat_sys_shmctl(first, second, compat_ptr(ptr));
|
||||
break;
|
||||
default:
|
||||
err = -EINVAL;
|
||||
err = -ENOSYS;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -46,10 +46,9 @@
|
|||
PTR_L a5, PT_R9(sp)
|
||||
PTR_L a6, PT_R10(sp)
|
||||
PTR_L a7, PT_R11(sp)
|
||||
#else
|
||||
PTR_ADDIU sp, PT_SIZE
|
||||
#endif
|
||||
.endm
|
||||
PTR_ADDIU sp, PT_SIZE
|
||||
.endm
|
||||
|
||||
.macro RETURN_BACK
|
||||
jr ra
|
||||
|
@ -68,7 +67,11 @@ NESTED(ftrace_caller, PT_SIZE, ra)
|
|||
.globl _mcount
|
||||
_mcount:
|
||||
b ftrace_stub
|
||||
addiu sp,sp,8
|
||||
#ifdef CONFIG_32BIT
|
||||
addiu sp,sp,8
|
||||
#else
|
||||
nop
|
||||
#endif
|
||||
|
||||
/* When tracing is activated, it calls ftrace_caller+8 (aka here) */
|
||||
lw t1, function_trace_stop
|
||||
|
|
|
@ -67,7 +67,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||
if (cpu_has_mips_r) {
|
||||
seq_printf(m, "isa\t\t\t:");
|
||||
if (cpu_has_mips_1)
|
||||
seq_printf(m, "%s", "mips1");
|
||||
seq_printf(m, "%s", " mips1");
|
||||
if (cpu_has_mips_2)
|
||||
seq_printf(m, "%s", " mips2");
|
||||
if (cpu_has_mips_3)
|
||||
|
|
|
@ -1571,7 +1571,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
|
|||
#ifdef CONFIG_64BIT
|
||||
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
|
||||
#endif
|
||||
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
|
||||
if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
|
||||
status_set |= ST0_XX;
|
||||
if (cpu_has_dsp)
|
||||
status_set |= ST0_MX;
|
||||
|
|
|
@ -90,12 +90,12 @@ int __mips_test_and_set_bit(unsigned long nr,
|
|||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
int res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
res = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
|
@ -116,12 +116,12 @@ int __mips_test_and_set_bit_lock(unsigned long nr,
|
|||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
int res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
res = (mask & *a) != 0;
|
||||
*a |= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
|
@ -141,12 +141,12 @@ int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
|
|||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
int res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
res = (mask & *a) != 0;
|
||||
*a &= ~mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
|
@ -166,12 +166,12 @@ int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
|
|||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
int res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
res = (mask & *a) != 0;
|
||||
*a ^= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
|
|
|
@ -270,7 +270,7 @@ LEAF(csum_partial)
|
|||
#endif
|
||||
|
||||
/* odd buffer alignment? */
|
||||
#ifdef CPU_MIPSR2
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
wsbh v1, sum
|
||||
movn sum, v1, t7
|
||||
#else
|
||||
|
@ -670,7 +670,7 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc)
|
|||
addu sum, v1
|
||||
#endif
|
||||
|
||||
#ifdef CPU_MIPSR2
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
wsbh v1, sum
|
||||
movn sum, v1, odd
|
||||
#else
|
||||
|
|
|
@ -1247,10 +1247,8 @@ static void __cpuinit setup_scache(void)
|
|||
return;
|
||||
|
||||
default:
|
||||
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
|
||||
c->isa_level == MIPS_CPU_ISA_M32R2 ||
|
||||
c->isa_level == MIPS_CPU_ISA_M64R1 ||
|
||||
c->isa_level == MIPS_CPU_ISA_M64R2) {
|
||||
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
|
||||
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
|
||||
#ifdef CONFIG_MIPS_CPU_SCACHE
|
||||
if (mips_sc_init ()) {
|
||||
scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
|
||||
|
|
|
@ -98,10 +98,8 @@ static inline int __init mips_sc_probe(void)
|
|||
c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
|
||||
|
||||
/* Ignore anything but MIPSxx processors */
|
||||
if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
|
||||
c->isa_level != MIPS_CPU_ISA_M32R2 &&
|
||||
c->isa_level != MIPS_CPU_ISA_M64R1 &&
|
||||
c->isa_level != MIPS_CPU_ISA_M64R2)
|
||||
if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
|
||||
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
|
||||
return 0;
|
||||
|
||||
/* Does this MIPS32/MIPS64 CPU have a config2 register? */
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/tlbmisc.h>
|
||||
|
||||
#ifdef CONFIG_DEBUG_PCI
|
||||
#ifdef CONFIG_PCI_DEBUG
|
||||
#define DBG(x...) printk(KERN_DEBUG x)
|
||||
#else
|
||||
#define DBG(x...) do {} while (0)
|
||||
|
@ -162,7 +162,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
|
|||
if (status & (1 << 29)) {
|
||||
*data = 0xffffffff;
|
||||
error = -1;
|
||||
DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
|
||||
DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
|
||||
access_type, bus->number, device);
|
||||
} else if ((status >> 28) & 0xf) {
|
||||
DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",
|
||||
|
|
|
@ -23,8 +23,10 @@
|
|||
#include <asm/code-patching.h>
|
||||
#include <asm/machdep.h>
|
||||
|
||||
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
|
||||
extern void epapr_ev_idle(void);
|
||||
extern u32 epapr_ev_idle_start[];
|
||||
#endif
|
||||
|
||||
bool epapr_paravirt_enabled;
|
||||
|
||||
|
@ -47,11 +49,15 @@ static int __init epapr_paravirt_init(void)
|
|||
|
||||
for (i = 0; i < (len / 4); i++) {
|
||||
patch_instruction(epapr_hypercall_start + i, insts[i]);
|
||||
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
|
||||
patch_instruction(epapr_ev_idle_start + i, insts[i]);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
|
||||
if (of_get_property(hyper_node, "has-idle", NULL))
|
||||
ppc_md.power_save = epapr_ev_idle;
|
||||
#endif
|
||||
|
||||
epapr_paravirt_enabled = true;
|
||||
|
||||
|
|
|
@ -1066,78 +1066,6 @@ unrecov_user_slb:
|
|||
#endif /* __DISABLED__ */
|
||||
|
||||
|
||||
/*
|
||||
* r13 points to the PACA, r9 contains the saved CR,
|
||||
* r12 contain the saved SRR1, SRR0 is still ready for return
|
||||
* r3 has the faulting address
|
||||
* r9 - r13 are saved in paca->exslb.
|
||||
* r3 is saved in paca->slb_r3
|
||||
* We assume we aren't going to take any exceptions during this procedure.
|
||||
*/
|
||||
_GLOBAL(slb_miss_realmode)
|
||||
mflr r10
|
||||
#ifdef CONFIG_RELOCATABLE
|
||||
mtctr r11
|
||||
#endif
|
||||
|
||||
stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
|
||||
std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
|
||||
|
||||
bl .slb_allocate_realmode
|
||||
|
||||
/* All done -- return from exception. */
|
||||
|
||||
ld r10,PACA_EXSLB+EX_LR(r13)
|
||||
ld r3,PACA_EXSLB+EX_R3(r13)
|
||||
lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
|
||||
|
||||
mtlr r10
|
||||
|
||||
andi. r10,r12,MSR_RI /* check for unrecoverable exception */
|
||||
beq- 2f
|
||||
|
||||
.machine push
|
||||
.machine "power4"
|
||||
mtcrf 0x80,r9
|
||||
mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
|
||||
.machine pop
|
||||
|
||||
RESTORE_PPR_PACA(PACA_EXSLB, r9)
|
||||
ld r9,PACA_EXSLB+EX_R9(r13)
|
||||
ld r10,PACA_EXSLB+EX_R10(r13)
|
||||
ld r11,PACA_EXSLB+EX_R11(r13)
|
||||
ld r12,PACA_EXSLB+EX_R12(r13)
|
||||
ld r13,PACA_EXSLB+EX_R13(r13)
|
||||
rfid
|
||||
b . /* prevent speculative execution */
|
||||
|
||||
2: mfspr r11,SPRN_SRR0
|
||||
ld r10,PACAKBASE(r13)
|
||||
LOAD_HANDLER(r10,unrecov_slb)
|
||||
mtspr SPRN_SRR0,r10
|
||||
ld r10,PACAKMSR(r13)
|
||||
mtspr SPRN_SRR1,r10
|
||||
rfid
|
||||
b .
|
||||
|
||||
unrecov_slb:
|
||||
EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
|
||||
DISABLE_INTS
|
||||
bl .save_nvgprs
|
||||
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl .unrecoverable_exception
|
||||
b 1b
|
||||
|
||||
|
||||
#ifdef CONFIG_PPC_970_NAP
|
||||
power4_fixup_nap:
|
||||
andc r9,r9,r10
|
||||
std r9,TI_LOCAL_FLAGS(r11)
|
||||
ld r10,_LINK(r1) /* make idle task do the */
|
||||
std r10,_NIP(r1) /* equivalent of a blr */
|
||||
blr
|
||||
#endif
|
||||
|
||||
.align 7
|
||||
.globl alignment_common
|
||||
alignment_common:
|
||||
|
@ -1335,6 +1263,78 @@ _GLOBAL(opal_mc_secondary_handler)
|
|||
#endif /* CONFIG_PPC_POWERNV */
|
||||
|
||||
|
||||
/*
|
||||
* r13 points to the PACA, r9 contains the saved CR,
|
||||
* r12 contain the saved SRR1, SRR0 is still ready for return
|
||||
* r3 has the faulting address
|
||||
* r9 - r13 are saved in paca->exslb.
|
||||
* r3 is saved in paca->slb_r3
|
||||
* We assume we aren't going to take any exceptions during this procedure.
|
||||
*/
|
||||
_GLOBAL(slb_miss_realmode)
|
||||
mflr r10
|
||||
#ifdef CONFIG_RELOCATABLE
|
||||
mtctr r11
|
||||
#endif
|
||||
|
||||
stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
|
||||
std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
|
||||
|
||||
bl .slb_allocate_realmode
|
||||
|
||||
/* All done -- return from exception. */
|
||||
|
||||
ld r10,PACA_EXSLB+EX_LR(r13)
|
||||
ld r3,PACA_EXSLB+EX_R3(r13)
|
||||
lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
|
||||
|
||||
mtlr r10
|
||||
|
||||
andi. r10,r12,MSR_RI /* check for unrecoverable exception */
|
||||
beq- 2f
|
||||
|
||||
.machine push
|
||||
.machine "power4"
|
||||
mtcrf 0x80,r9
|
||||
mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
|
||||
.machine pop
|
||||
|
||||
RESTORE_PPR_PACA(PACA_EXSLB, r9)
|
||||
ld r9,PACA_EXSLB+EX_R9(r13)
|
||||
ld r10,PACA_EXSLB+EX_R10(r13)
|
||||
ld r11,PACA_EXSLB+EX_R11(r13)
|
||||
ld r12,PACA_EXSLB+EX_R12(r13)
|
||||
ld r13,PACA_EXSLB+EX_R13(r13)
|
||||
rfid
|
||||
b . /* prevent speculative execution */
|
||||
|
||||
2: mfspr r11,SPRN_SRR0
|
||||
ld r10,PACAKBASE(r13)
|
||||
LOAD_HANDLER(r10,unrecov_slb)
|
||||
mtspr SPRN_SRR0,r10
|
||||
ld r10,PACAKMSR(r13)
|
||||
mtspr SPRN_SRR1,r10
|
||||
rfid
|
||||
b .
|
||||
|
||||
unrecov_slb:
|
||||
EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
|
||||
DISABLE_INTS
|
||||
bl .save_nvgprs
|
||||
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl .unrecoverable_exception
|
||||
b 1b
|
||||
|
||||
|
||||
#ifdef CONFIG_PPC_970_NAP
|
||||
power4_fixup_nap:
|
||||
andc r9,r9,r10
|
||||
std r9,TI_LOCAL_FLAGS(r11)
|
||||
ld r10,_LINK(r1) /* make idle task do the */
|
||||
std r10,_NIP(r1) /* equivalent of a blr */
|
||||
blr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Hash table stuff
|
||||
*/
|
||||
|
|
|
@ -344,6 +344,7 @@ extern unsigned long MODULES_END;
|
|||
#define _REGION3_ENTRY_CO 0x100 /* change-recording override */
|
||||
|
||||
/* Bits in the segment table entry */
|
||||
#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
|
||||
#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
|
||||
#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
|
||||
#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
|
||||
|
@ -1531,7 +1532,8 @@ extern int s390_enable_sie(void);
|
|||
/*
|
||||
* No page table caches to initialise
|
||||
*/
|
||||
#define pgtable_cache_init() do { } while (0)
|
||||
static inline void pgtable_cache_init(void) { }
|
||||
static inline void check_pgt_cache(void) { }
|
||||
|
||||
#include <asm-generic/pgtable.h>
|
||||
|
||||
|
|
|
@ -77,42 +77,69 @@ static size_t copy_in_kernel(size_t count, void __user *to,
|
|||
* >= -4095 (IS_ERR_VALUE(x) returns true), a fault has occured and the address
|
||||
* contains the (negative) exception code.
|
||||
*/
|
||||
static __always_inline unsigned long follow_table(struct mm_struct *mm,
|
||||
unsigned long addr, int write)
|
||||
#ifdef CONFIG_64BIT
|
||||
static unsigned long follow_table(struct mm_struct *mm,
|
||||
unsigned long address, int write)
|
||||
{
|
||||
pgd_t *pgd;
|
||||
pud_t *pud;
|
||||
pmd_t *pmd;
|
||||
pte_t *ptep;
|
||||
unsigned long *table = (unsigned long *)__pa(mm->pgd);
|
||||
|
||||
pgd = pgd_offset(mm, addr);
|
||||
if (pgd_none(*pgd) || unlikely(pgd_bad(*pgd)))
|
||||
return -0x3aUL;
|
||||
|
||||
pud = pud_offset(pgd, addr);
|
||||
if (pud_none(*pud) || unlikely(pud_bad(*pud)))
|
||||
return -0x3bUL;
|
||||
|
||||
pmd = pmd_offset(pud, addr);
|
||||
if (pmd_none(*pmd))
|
||||
return -0x10UL;
|
||||
if (pmd_large(*pmd)) {
|
||||
if (write && (pmd_val(*pmd) & _SEGMENT_ENTRY_RO))
|
||||
return -0x04UL;
|
||||
return (pmd_val(*pmd) & HPAGE_MASK) + (addr & ~HPAGE_MASK);
|
||||
switch (mm->context.asce_bits & _ASCE_TYPE_MASK) {
|
||||
case _ASCE_TYPE_REGION1:
|
||||
table = table + ((address >> 53) & 0x7ff);
|
||||
if (unlikely(*table & _REGION_ENTRY_INV))
|
||||
return -0x39UL;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
case _ASCE_TYPE_REGION2:
|
||||
table = table + ((address >> 42) & 0x7ff);
|
||||
if (unlikely(*table & _REGION_ENTRY_INV))
|
||||
return -0x3aUL;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
case _ASCE_TYPE_REGION3:
|
||||
table = table + ((address >> 31) & 0x7ff);
|
||||
if (unlikely(*table & _REGION_ENTRY_INV))
|
||||
return -0x3bUL;
|
||||
table = (unsigned long *)(*table & _REGION_ENTRY_ORIGIN);
|
||||
case _ASCE_TYPE_SEGMENT:
|
||||
table = table + ((address >> 20) & 0x7ff);
|
||||
if (unlikely(*table & _SEGMENT_ENTRY_INV))
|
||||
return -0x10UL;
|
||||
if (unlikely(*table & _SEGMENT_ENTRY_LARGE)) {
|
||||
if (write && (*table & _SEGMENT_ENTRY_RO))
|
||||
return -0x04UL;
|
||||
return (*table & _SEGMENT_ENTRY_ORIGIN_LARGE) +
|
||||
(address & ~_SEGMENT_ENTRY_ORIGIN_LARGE);
|
||||
}
|
||||
table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
|
||||
}
|
||||
if (unlikely(pmd_bad(*pmd)))
|
||||
return -0x10UL;
|
||||
|
||||
ptep = pte_offset_map(pmd, addr);
|
||||
if (!pte_present(*ptep))
|
||||
table = table + ((address >> 12) & 0xff);
|
||||
if (unlikely(*table & _PAGE_INVALID))
|
||||
return -0x11UL;
|
||||
if (write && (!pte_write(*ptep) || !pte_dirty(*ptep)))
|
||||
if (write && (*table & _PAGE_RO))
|
||||
return -0x04UL;
|
||||
|
||||
return (pte_val(*ptep) & PAGE_MASK) + (addr & ~PAGE_MASK);
|
||||
return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
|
||||
}
|
||||
|
||||
#else /* CONFIG_64BIT */
|
||||
|
||||
static unsigned long follow_table(struct mm_struct *mm,
|
||||
unsigned long address, int write)
|
||||
{
|
||||
unsigned long *table = (unsigned long *)__pa(mm->pgd);
|
||||
|
||||
table = table + ((address >> 20) & 0x7ff);
|
||||
if (unlikely(*table & _SEGMENT_ENTRY_INV))
|
||||
return -0x10UL;
|
||||
table = (unsigned long *)(*table & _SEGMENT_ENTRY_ORIGIN);
|
||||
table = table + ((address >> 12) & 0xff);
|
||||
if (unlikely(*table & _PAGE_INVALID))
|
||||
return -0x11UL;
|
||||
if (write && (*table & _PAGE_RO))
|
||||
return -0x04UL;
|
||||
return (*table & PAGE_MASK) + (address & ~PAGE_MASK);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_64BIT */
|
||||
|
||||
static __always_inline size_t __user_copy_pt(unsigned long uaddr, void *kptr,
|
||||
size_t n, int write_user)
|
||||
{
|
||||
|
@ -197,7 +224,7 @@ size_t copy_to_user_pt(size_t n, void __user *to, const void *from)
|
|||
|
||||
static size_t clear_user_pt(size_t n, void __user *to)
|
||||
{
|
||||
void *zpage = &empty_zero_page;
|
||||
void *zpage = (void *) empty_zero_page;
|
||||
long done, size, ret;
|
||||
|
||||
done = 0;
|
||||
|
|
|
@ -1004,15 +1004,8 @@ void __cpuinit setup_cpu(int boot)
|
|||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
|
||||
/*
|
||||
* Note that the kernel can potentially support other compression
|
||||
* techniques than gz, though we don't do so by default. If we ever
|
||||
* decide to do so we can either look for other filename extensions,
|
||||
* or just allow a file with this name to be compressed with an
|
||||
* arbitrary compressor (somewhat counterintuitively).
|
||||
*/
|
||||
static int __initdata set_initramfs_file;
|
||||
static char __initdata initramfs_file[128] = "initramfs.cpio.gz";
|
||||
static char __initdata initramfs_file[128] = "initramfs";
|
||||
|
||||
static int __init setup_initramfs_file(char *str)
|
||||
{
|
||||
|
@ -1026,9 +1019,9 @@ static int __init setup_initramfs_file(char *str)
|
|||
early_param("initramfs_file", setup_initramfs_file);
|
||||
|
||||
/*
|
||||
* We look for an "initramfs.cpio.gz" file in the hvfs.
|
||||
* If there is one, we allocate some memory for it and it will be
|
||||
* unpacked to the initramfs.
|
||||
* We look for a file called "initramfs" in the hvfs. If there is one, we
|
||||
* allocate some memory for it and it will be unpacked to the initramfs.
|
||||
* If it's compressed, the initd code will uncompress it first.
|
||||
*/
|
||||
static void __init load_hv_initrd(void)
|
||||
{
|
||||
|
@ -1038,10 +1031,16 @@ static void __init load_hv_initrd(void)
|
|||
|
||||
fd = hv_fs_findfile((HV_VirtAddr) initramfs_file);
|
||||
if (fd == HV_ENOENT) {
|
||||
if (set_initramfs_file)
|
||||
if (set_initramfs_file) {
|
||||
pr_warning("No such hvfs initramfs file '%s'\n",
|
||||
initramfs_file);
|
||||
return;
|
||||
return;
|
||||
} else {
|
||||
/* Try old backwards-compatible name. */
|
||||
fd = hv_fs_findfile((HV_VirtAddr)"initramfs.cpio.gz");
|
||||
if (fd == HV_ENOENT)
|
||||
return;
|
||||
}
|
||||
}
|
||||
BUG_ON(fd < 0);
|
||||
stat = hv_fs_fstat(fd);
|
||||
|
|
|
@ -4,7 +4,7 @@
|
|||
# create a compressed vmlinux image from the original vmlinux
|
||||
#
|
||||
|
||||
targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo head_$(BITS).o misc.o string.o cmdline.o early_serial_console.o piggy.o
|
||||
targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.xz vmlinux.bin.lzo
|
||||
|
||||
KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2
|
||||
KBUILD_CFLAGS += -fno-strict-aliasing -fPIC
|
||||
|
@ -29,7 +29,6 @@ VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \
|
|||
$(obj)/piggy.o
|
||||
|
||||
$(obj)/eboot.o: KBUILD_CFLAGS += -fshort-wchar -mno-red-zone
|
||||
$(obj)/efi_stub_$(BITS).o: KBUILD_CLFAGS += -fshort-wchar -mno-red-zone
|
||||
|
||||
ifeq ($(CONFIG_EFI_STUB), y)
|
||||
VMLINUX_OBJS += $(obj)/eboot.o $(obj)/efi_stub_$(BITS).o
|
||||
|
@ -43,7 +42,7 @@ OBJCOPYFLAGS_vmlinux.bin := -R .comment -S
|
|||
$(obj)/vmlinux.bin: vmlinux FORCE
|
||||
$(call if_changed,objcopy)
|
||||
|
||||
targets += vmlinux.bin.all vmlinux.relocs
|
||||
targets += $(patsubst $(obj)/%,%,$(VMLINUX_OBJS)) vmlinux.bin.all vmlinux.relocs
|
||||
|
||||
CMD_RELOCS = arch/x86/tools/relocs
|
||||
quiet_cmd_relocs = RELOCS $@
|
||||
|
|
|
@ -29,13 +29,13 @@ extern const unsigned long sys_call_table[];
|
|||
*/
|
||||
static inline int syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
|
||||
{
|
||||
return regs->orig_ax & __SYSCALL_MASK;
|
||||
return regs->orig_ax;
|
||||
}
|
||||
|
||||
static inline void syscall_rollback(struct task_struct *task,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
regs->ax = regs->orig_ax & __SYSCALL_MASK;
|
||||
regs->ax = regs->orig_ax;
|
||||
}
|
||||
|
||||
static inline long syscall_get_error(struct task_struct *task,
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue