gianfar: Add flow control support
eTSEC has Rx and Tx flow control capabilities that may be enabled through MACCFG1[Rx_Flow, Tx_Flow] bits. These bits must not be set however when eTSEC is operated in Half-Duplex mode. Unfortunately, the driver currently sets these bits unconditionally. This patch adds the proper handling of the PAUSE frame capability register bits by implementing the ethtool -A interface. When pause autoneg is enabled, the controller uses the phy's capability to negotiate PAUSE frame settings with the link partner and reconfigures its Rx_Flow and Tx_Flow settings to match the capabilities of the link partner. If pause autoneg is off, the PAUSE frame generation may be forced manually (ethtool -A). Flow control is disabled by default now. This implementation is inspired by the tg3 driver. Signed-off-by: Lutz Jaenicke <ljaenicke@innominate.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1016,7 +1016,14 @@ static int gfar_probe(struct platform_device *ofdev)
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/* We need to delay at least 3 TX clocks */
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udelay(2);
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tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
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tempval = 0;
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if (!priv->pause_aneg_en && priv->tx_pause_en)
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tempval |= MACCFG1_TX_FLOW;
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if (!priv->pause_aneg_en && priv->rx_pause_en)
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tempval |= MACCFG1_RX_FLOW;
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/* the soft reset bit is not self-resetting, so we need to
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* clear it before resuming normal operation
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*/
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gfar_write(®s->maccfg1, tempval);
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/* Initialize MACCFG2. */
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@ -1460,7 +1467,7 @@ static int init_phy(struct net_device *dev)
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struct gfar_private *priv = netdev_priv(dev);
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uint gigabit_support =
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priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
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SUPPORTED_1000baseT_Full : 0;
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GFAR_SUPPORTED_GBIT : 0;
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phy_interface_t interface;
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priv->oldlink = 0;
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@ -3023,6 +3030,41 @@ static irqreturn_t gfar_interrupt(int irq, void *grp_id)
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return IRQ_HANDLED;
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}
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static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
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{
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struct phy_device *phydev = priv->phydev;
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u32 val = 0;
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if (!phydev->duplex)
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return val;
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if (!priv->pause_aneg_en) {
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if (priv->tx_pause_en)
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val |= MACCFG1_TX_FLOW;
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if (priv->rx_pause_en)
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val |= MACCFG1_RX_FLOW;
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} else {
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u16 lcl_adv, rmt_adv;
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u8 flowctrl;
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/* get link partner capabilities */
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rmt_adv = 0;
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if (phydev->pause)
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rmt_adv = LPA_PAUSE_CAP;
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if (phydev->asym_pause)
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rmt_adv |= LPA_PAUSE_ASYM;
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lcl_adv = mii_advertise_flowctrl(phydev->advertising);
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flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
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if (flowctrl & FLOW_CTRL_TX)
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val |= MACCFG1_TX_FLOW;
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if (flowctrl & FLOW_CTRL_RX)
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val |= MACCFG1_RX_FLOW;
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}
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return val;
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}
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/* Called every time the controller might need to be made
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* aware of new link state. The PHY code conveys this
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* information through variables in the phydev structure, and this
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@ -3041,6 +3083,7 @@ static void adjust_link(struct net_device *dev)
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lock_tx_qs(priv);
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if (phydev->link) {
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u32 tempval1 = gfar_read(®s->maccfg1);
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u32 tempval = gfar_read(®s->maccfg2);
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u32 ecntrl = gfar_read(®s->ecntrl);
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@ -3089,6 +3132,10 @@ static void adjust_link(struct net_device *dev)
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priv->oldspeed = phydev->speed;
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}
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tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
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tempval1 |= gfar_get_flowctrl_cfg(priv);
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gfar_write(®s->maccfg1, tempval1);
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gfar_write(®s->maccfg2, tempval);
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gfar_write(®s->ecntrl, ecntrl);
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@ -146,6 +146,10 @@ extern const char gfar_driver_version[];
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| SUPPORTED_Autoneg \
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| SUPPORTED_MII)
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#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \
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| SUPPORTED_Pause \
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| SUPPORTED_Asym_Pause)
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/* TBI register addresses */
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#define MII_TBICON 0x11
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@ -1100,7 +1104,11 @@ struct gfar_private {
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/* Wake-on-LAN enabled */
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wol_en:1,
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/* Enable priorty based Tx scheduling in Hw */
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prio_sched_en:1;
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prio_sched_en:1,
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/* Flow control flags */
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pause_aneg_en:1,
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tx_pause_en:1,
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rx_pause_en:1;
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/* The total tx and rx ring size for the enabled queues */
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unsigned int total_tx_ring_size;
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@ -535,6 +535,78 @@ static int gfar_sringparam(struct net_device *dev,
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return err;
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}
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static void gfar_gpauseparam(struct net_device *dev,
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struct ethtool_pauseparam *epause)
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{
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struct gfar_private *priv = netdev_priv(dev);
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epause->autoneg = !!priv->pause_aneg_en;
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epause->rx_pause = !!priv->rx_pause_en;
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epause->tx_pause = !!priv->tx_pause_en;
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}
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static int gfar_spauseparam(struct net_device *dev,
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struct ethtool_pauseparam *epause)
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{
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struct gfar_private *priv = netdev_priv(dev);
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struct phy_device *phydev = priv->phydev;
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struct gfar __iomem *regs = priv->gfargrp[0].regs;
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u32 oldadv, newadv;
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if (!(phydev->supported & SUPPORTED_Pause) ||
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(!(phydev->supported & SUPPORTED_Asym_Pause) &&
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(epause->rx_pause != epause->tx_pause)))
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return -EINVAL;
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priv->rx_pause_en = priv->tx_pause_en = 0;
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if (epause->rx_pause) {
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priv->rx_pause_en = 1;
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if (epause->tx_pause) {
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priv->tx_pause_en = 1;
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/* FLOW_CTRL_RX & TX */
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newadv = ADVERTISED_Pause;
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} else /* FLOW_CTLR_RX */
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newadv = ADVERTISED_Pause | ADVERTISED_Asym_Pause;
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} else if (epause->tx_pause) {
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priv->tx_pause_en = 1;
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/* FLOW_CTLR_TX */
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newadv = ADVERTISED_Asym_Pause;
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} else
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newadv = 0;
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if (epause->autoneg)
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priv->pause_aneg_en = 1;
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else
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priv->pause_aneg_en = 0;
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oldadv = phydev->advertising &
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(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
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if (oldadv != newadv) {
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phydev->advertising &=
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~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
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phydev->advertising |= newadv;
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if (phydev->autoneg)
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/* inform link partner of our
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* new flow ctrl settings
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*/
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return phy_start_aneg(phydev);
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if (!epause->autoneg) {
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u32 tempval;
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tempval = gfar_read(®s->maccfg1);
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tempval &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
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if (priv->tx_pause_en)
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tempval |= MACCFG1_TX_FLOW;
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if (priv->rx_pause_en)
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tempval |= MACCFG1_RX_FLOW;
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gfar_write(®s->maccfg1, tempval);
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}
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}
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return 0;
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}
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int gfar_set_features(struct net_device *dev, netdev_features_t features)
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{
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struct gfar_private *priv = netdev_priv(dev);
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@ -1806,6 +1878,8 @@ const struct ethtool_ops gfar_ethtool_ops = {
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.set_coalesce = gfar_scoalesce,
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.get_ringparam = gfar_gringparam,
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.set_ringparam = gfar_sringparam,
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.get_pauseparam = gfar_gpauseparam,
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.set_pauseparam = gfar_spauseparam,
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.get_strings = gfar_gstrings,
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.get_sset_count = gfar_sset_count,
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.get_ethtool_stats = gfar_fill_stats,
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