clk: sunxi: Add A10s gates
The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Emilio López <emilio@elopez.com.ar>
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@ -14,13 +14,16 @@ Required properties:
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"allwinner,sun4i-ahb-clk" - for the AHB clock
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"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
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"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
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"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
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"allwinner,sun4i-apb0-clk" - for the APB0 clock
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"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
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"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
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"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
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"allwinner,sun4i-apb1-clk" - for the APB1 clock
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"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
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"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
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"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
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"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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@ -0,0 +1,75 @@
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Gate clock outputs
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------------------
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* AXI gates ("allwinner,sun4i-axi-gates-clk")
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DRAM 0
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* AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
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USB0 0
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EHCI0 1
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OHCI0 2
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SS 5
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DMA 6
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BIST 7
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MMC0 8
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MMC1 9
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MMC2 10
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NAND 13
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SDRAM 14
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EMAC 17
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TS 18
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SPI0 20
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SPI1 21
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SPI2 22
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GPS 26
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HSTIMER 28
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VE 32
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TVE 34
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LCD 36
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CSI 40
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HDMI 43
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DE_BE 44
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DE_FE 46
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IEP 51
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MALI400 52
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* APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
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CODEC 0
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IIS 3
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PIO 5
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IR 6
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KEYPAD 10
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* APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
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I2C0 0
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I2C1 1
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I2C2 2
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UART0 16
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UART1 17
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UART2 18
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UART3 19
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Notation:
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[*]: The datasheet didn't mention these, but they are present on AW code
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[**]: The datasheet had this marked as "NC" but they are used on AW code
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@ -342,6 +342,10 @@ static const __initconst struct gates_data sun4i_ahb_gates_data = {
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.mask = {0x7F77FFF, 0x14FB3F},
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};
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static const __initconst struct gates_data sun5i_a10s_ahb_gates_data = {
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.mask = {0x147667e7, 0x185915},
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};
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static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
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.mask = {0x107067e7, 0x185111},
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};
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@ -350,6 +354,10 @@ static const __initconst struct gates_data sun4i_apb0_gates_data = {
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.mask = {0x4EF},
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};
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static const __initconst struct gates_data sun5i_a10s_apb0_gates_data = {
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.mask = {0x469},
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};
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static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
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.mask = {0x61},
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};
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@ -358,6 +366,10 @@ static const __initconst struct gates_data sun4i_apb1_gates_data = {
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.mask = {0xFF00F7},
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};
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static const __initconst struct gates_data sun5i_a10s_apb1_gates_data = {
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.mask = {0xf0007},
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};
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static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
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.mask = {0xa0007},
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};
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@ -443,10 +455,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
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static const __initconst struct of_device_id clk_gates_match[] = {
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{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
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{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
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{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
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{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
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{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
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{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
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{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
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{}
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};
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