Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86/pti updates from Thomas Gleixner: "Two small fixes correcting the handling of SSB mitigations on AMD processors" * 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSR x86/bugs: Update when to check for the LS_CFG SSBD mitigation
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commit
23adbe6fb5
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@ -543,7 +543,9 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
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nodes_per_socket = ((value >> 3) & 7) + 1;
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}
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if (c->x86 >= 0x15 && c->x86 <= 0x17) {
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if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
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!boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
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c->x86 >= 0x15 && c->x86 <= 0x17) {
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unsigned int bit;
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switch (c->x86) {
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@ -155,7 +155,8 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
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guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
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/* SSBD controlled in MSR_SPEC_CTRL */
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if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
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if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
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static_cpu_has(X86_FEATURE_AMD_SSBD))
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hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
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if (hostval != guestval) {
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@ -533,9 +534,10 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
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* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
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* use a completely different MSR and bit dependent on family.
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*/
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if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
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!static_cpu_has(X86_FEATURE_AMD_SSBD)) {
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x86_amd_ssb_disable();
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else {
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} else {
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x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
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x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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