[SPARC64]: Fix unaligned access winfxup handling on SUN4V.
Another case where we have to force ourselves into global register level one. Also make sure the arguments passed to sun4v_do_mna() are correct. This area actually needs some more work, for example spill fixup is not necessarily going to do the right thing for this case. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -137,7 +137,7 @@ sun4v_dtlb_load:
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sun4v_dtlb_prot:
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SET_GL(1)
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/* Load MMU Miss base into %g2. */
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/* Load MMU Miss base into %g5. */
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ldxa [%g0] ASI_SCRATCHPAD, %g5
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ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
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@ -148,9 +148,10 @@ sun4v_dtlb_prot:
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
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/* Called from trap table with TAG TARGET placed into
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* %g6, SCRATCHPAD_UTSBREG1 contents in %g1, and
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* SCRATCHPAD_MMU_MISS contents in %g2.
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/* Called from trap table:
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* %g4: vaddr
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* %g5: context
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* %g6: TAG TARGET
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*/
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sun4v_itsb_miss:
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mov SCRATCHPAD_UTSBREG1, %g1
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@ -159,8 +160,10 @@ sun4v_itsb_miss:
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mov FAULT_CODE_ITLB, %g3
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ba,a,pt %xcc, sun4v_tsb_miss_common
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/* Called from trap table with TAG TARGET placed into
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* %g6 and SCRATCHPAD_UTSBREG1 contents in %g1.
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/* Called from trap table:
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* %g4: vaddr
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* %g5: context
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* %g6: TAG TARGET
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*/
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sun4v_dtsb_miss:
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mov SCRATCHPAD_UTSBREG1, %g1
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@ -168,6 +171,8 @@ sun4v_dtsb_miss:
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brz,pn %g5, kvmap_dtlb_4v
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mov FAULT_CODE_DTLB, %g3
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/* fallthrough */
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/* Create TSB pointer into %g1. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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@ -304,19 +309,30 @@ sun4v_dacc_tl1:
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/* Memory Address Unaligned. */
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sun4v_mna:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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/* Window fixup? */
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rdpr %tl, %g2
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cmp %g2, 1
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ble,pt %icc, 1f
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nop
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SET_GL(1)
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ldxa [%g0] ASI_SCRATCHPAD, %g5
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ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
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mov HV_FAULT_TYPE_UNALIGNED, %g3
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ldx [%g5 + HV_FAULT_D_CTX_OFFSET], %g4
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sllx %g3, 16, %g3
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or %g4, %g3, %g4
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ba,pt %xcc, winfix_mna
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rdpr %tpc, %g3
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/* not reached */
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1: ldxa [%g0] ASI_SCRATCHPAD, %g2
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mov HV_FAULT_TYPE_UNALIGNED, %g3
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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/* Window fixup? */
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rdpr %tl, %g2
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cmp %g2, 1
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bgu,pn %icc, winfix_mna
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rdpr %tpc, %g3
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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@ -115,16 +115,17 @@ fill_fixup_mna:
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ba,pt %xcc, etrap
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rd %pc, %g7
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sethi %hi(tlb_type), %g1
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mov %l4, %o1
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lduw [%g1 + %lo(tlb_type)], %g1
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mov %l5, %o2
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cmp %g1, 3
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bne,pt %icc, 1f
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add %sp, PTREGS_OFF, %o0
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mov %l4, %o2
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call sun4v_do_mna
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nop
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mov %l5, %o1
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ba,a,pt %xcc, rtrap_clr_l6
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1: call mem_address_unaligned
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1: mov %l4, %o1
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mov %l5, %o2
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call mem_address_unaligned
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nop
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ba,a,pt %xcc, rtrap_clr_l6
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