clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
Perform upwards rounding when calculating dividers for periph clks on Tegra30 and Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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@ -791,50 +791,53 @@ static unsigned long tegra114_input_freq[] = {
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#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id, \
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_parents##_idx, 0)
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
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_regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\
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_clk_id, _parents##_idx, 0)
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#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
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_clk_num, _regs, _gate_flags, _clk_id, flags)\
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id, \
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_parents##_idx, flags)
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
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_regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\
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_clk_id, _parents##_idx, flags)
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#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id, \
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_parents##_idx, 0)
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
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_regs, _clk_num, periph_clk_enb_refcnt, _gate_flags,\
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_clk_id, _parents##_idx, 0)
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#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\
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_clk_num, _regs, _gate_flags, _clk_id, flags)\
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
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_clk_num, periph_clk_enb_refcnt, _gate_flags, \
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_clk_id, _parents##_idx, flags)
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30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id, \
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_parents##_idx, flags)
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#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
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_clk_num, periph_clk_enb_refcnt, _gate_flags, \
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_clk_id, _parents##_idx, 0)
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id, \
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_parents##_idx, 0)
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#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
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_clk_num, _regs, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\
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_clk_num, periph_clk_enb_refcnt, 0, _clk_id, \
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_parents##_idx, 0)
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30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
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#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\
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_clk_num, _regs, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\
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30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \
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periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0)
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30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
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_regs, _clk_num, periph_clk_enb_refcnt, 0, _clk_id,\
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_parents##_idx, 0)
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#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
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_mux_shift, _mux_mask, _clk_num, _regs, \
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@ -847,14 +850,16 @@ static unsigned long tegra114_input_freq[] = {
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#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
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_clk_num, periph_clk_enb_refcnt, _gate_flags, \
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_clk_id, _parents##_idx, 0)
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29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id, \
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_parents##_idx, 0)
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#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\
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_regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \
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_offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \
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_offset, 16, 0xE01F, 0, 0, 8, 1, \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags , _clk_id, \
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mux_d_audio_clk_idx, 0)
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@ -282,8 +282,8 @@ static DEFINE_SPINLOCK(sysrate_lock);
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#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
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30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id)
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30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs, \
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_clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id)
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#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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@ -295,21 +295,22 @@ static DEFINE_SPINLOCK(sysrate_lock);
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#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
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29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id)
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29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs,\
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_clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id)
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#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \
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_clk_num, _regs, _gate_flags, _clk_id) \
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TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
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30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
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_clk_num, periph_clk_enb_refcnt, _gate_flags, \
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_clk_id)
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30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, _gate_flags, _clk_id)
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#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\
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_clk_num, _regs, _clk_id) \
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TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \
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30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \
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_clk_num, periph_clk_enb_refcnt, 0, _clk_id)
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30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \
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TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \
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periph_clk_enb_refcnt, 0, _clk_id)
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#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \
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_mux_shift, _mux_width, _clk_num, _regs, \
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