ath9k: remove ath9k_ht_macmode
This is used just to determine how to program the MAC, either for 20 MHz operation of 40 MHz so just use conf_is_ht40() Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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6420014ca4
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25c56eec92
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@ -592,7 +592,6 @@ struct ath_softc {
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bool ps_enabled;
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unsigned long ps_usecount;
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enum ath9k_int imask;
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enum ath9k_ht_macmode tx_chan_width;
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struct ath_config config;
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struct ath_rx rx;
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@ -26,8 +26,7 @@
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#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
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enum ath9k_ht_macmode macmode);
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
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static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
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struct ar5416_eeprom_def *pEepData,
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u32 reg, u32 value);
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@ -1352,8 +1351,7 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
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}
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static int ath9k_hw_process_ini(struct ath_hw *ah,
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struct ath9k_channel *chan,
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enum ath9k_ht_macmode macmode)
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struct ath9k_channel *chan)
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{
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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int i, regWrites = 0;
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@ -1455,7 +1453,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
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}
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ath9k_hw_override_ini(ah, chan);
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ath9k_hw_set_regs(ah, chan, macmode);
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ath9k_hw_set_regs(ah, chan);
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ath9k_hw_init_chain_masks(ah);
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if (OLC_FOR_AR9280_20_LATER)
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@ -1738,8 +1736,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
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}
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}
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
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enum ath9k_ht_macmode macmode)
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static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
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{
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u32 phymode;
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u32 enableDacFifo = 0;
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@ -1761,7 +1758,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
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}
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REG_WRITE(ah, AR_PHY_TURBO, phymode);
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ath9k_hw_set11nmac2040(ah, macmode);
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ath9k_hw_set11nmac2040(ah);
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REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
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REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
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@ -1787,8 +1784,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah,
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}
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static bool ath9k_hw_channel_change(struct ath_hw *ah,
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struct ath9k_channel *chan,
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enum ath9k_ht_macmode macmode)
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struct ath9k_channel *chan)
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{
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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struct ath_common *common = ath9k_hw_common(ah);
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@ -1812,7 +1808,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
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return false;
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}
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ath9k_hw_set_regs(ah, chan, macmode);
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ath9k_hw_set_regs(ah, chan);
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if (AR_SREV_9280_10_OR_LATER(ah)) {
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ath9k_hw_ar9280_set_channel(ah, chan);
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@ -2323,7 +2319,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 saveLedState;
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struct ath_softc *sc = ah->ah_sc;
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struct ath9k_channel *curchan = ah->curchan;
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u32 saveDefAntenna;
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u32 macStaId1;
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@ -2348,7 +2343,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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!(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
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IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
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if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
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if (ath9k_hw_channel_change(ah, chan)) {
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ath9k_hw_loadnf(ah, ah->curchan);
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ath9k_hw_start_nfcal(ah);
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return 0;
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@ -2408,7 +2403,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
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}
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r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
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r = ath9k_hw_process_ini(ah, chan);
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if (r)
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return r;
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@ -4063,12 +4058,12 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
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}
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}
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void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
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void ath9k_hw_set11nmac2040(struct ath_hw *ah)
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{
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struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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u32 macmode;
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if (mode == ATH9K_HT_MACMODE_2040 &&
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!ah->config.cwm_ignore_extcca)
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if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
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macmode = AR_2040_JOINED_RX_CLEAR;
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else
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macmode = 0;
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@ -662,7 +662,7 @@ void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
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void ath9k_hw_reset_tsf(struct ath_hw *ah);
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void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
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bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
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void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
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void ath9k_hw_set11nmac2040(struct ath_hw *ah);
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void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
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void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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const struct ath9k_beacon_state *bs);
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@ -614,11 +614,6 @@ enum ath9k_cipher {
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ATH9K_CIPHER_MIC = 127
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};
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enum ath9k_ht_macmode {
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ATH9K_HT_MACMODE_20 = 0,
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ATH9K_HT_MACMODE_2040 = 1,
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};
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struct ath_hw;
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struct ath9k_channel;
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struct ath_rate_table;
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@ -299,6 +299,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ieee80211_conf *conf = &common->hw->conf;
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bool fastcc = true, stopped;
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struct ieee80211_channel *channel = hw->conf.channel;
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int r;
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@ -329,9 +330,9 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
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fastcc = false;
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ath_print(common, ATH_DBG_CONFIG,
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"(%u MHz) -> (%u MHz), chanwidth: %d\n",
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"(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
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sc->sc_ah->curchan->channel,
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channel->center_freq, sc->tx_chan_width);
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channel->center_freq, conf_is_ht40(conf));
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spin_lock_bh(&sc->sc_resetlock);
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@ -2191,16 +2192,10 @@ void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
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ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
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}
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sc->tx_chan_width = ATH9K_HT_MACMODE_20;
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if (conf_is_ht(conf)) {
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if (conf_is_ht40(conf))
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sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
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if (conf_is_ht(conf))
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ichan->chanmode = ath_get_extchanmode(sc, chan,
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conf->channel_type);
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}
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}
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/**********************/
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/* mac80211 callbacks */
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