Staging: winbond: wb35reg_s.h Coding styls fixes.
I fixed all problems reported by checkpatch.pl except some long lines. I also removed commented away code and revision comments. Checked for regressions with Dan Carpenters strip_whitespace.pl and diff. Signed-off-by: Lars Lindley <lindley@coyote.org> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>wifi-calibration
Lars Lindley
Greg Kroah-Hartman
parent
d4279a9f2c
commit
25e47dfc86
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@ -5,98 +5,100 @@
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#include <linux/types.h>
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#include <asm/atomic.h>
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//=======================================================================================
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/*
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HAL setting function
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/* =========================================================================
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*
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* HAL setting function
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*
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* ========================================
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* |Uxx| |Dxx| |Mxx| |BB| |RF|
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* ========================================
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* | |
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* Wb35Reg_Read Wb35Reg_Write
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*
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* ----------------------------------------
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* WbUsb_CallUSBDASync supplied By WbUsb module
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* ==========================================================================
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*/
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#define GetBit(dwData, i) (dwData & (0x00000001 << i))
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#define SetBit(dwData, i) (dwData | (0x00000001 << i))
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#define ClearBit(dwData, i) (dwData & ~(0x00000001 << i))
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========================================
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|Uxx| |Dxx| |Mxx| |BB| |RF|
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========================================
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| |
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Wb35Reg_Read Wb35Reg_Write
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#define IGNORE_INCREMENT 0
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#define AUTO_INCREMENT 0
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#define NO_INCREMENT 1
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#define REG_DIRECTION(_x, _y) ((_y)->DIRECT == 0 ? usb_rcvctrlpipe(_x, 0) : usb_sndctrlpipe(_x, 0))
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#define REG_BUF_SIZE(_x) ((_x)->bRequest == 0x04 ? cpu_to_le16((_x)->wLength) : 4)
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----------------------------------------
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WbUsb_CallUSBDASync supplied By WbUsb module
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*/
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//=======================================================================================
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#define GetBit( dwData, i) ( dwData & (0x00000001 << i))
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#define SetBit( dwData, i) ( dwData | (0x00000001 << i))
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#define ClearBit( dwData, i) ( dwData & ~(0x00000001 << i))
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#define IGNORE_INCREMENT 0
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#define AUTO_INCREMENT 0
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#define NO_INCREMENT 1
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#define REG_DIRECTION(_x,_y) ((_y)->DIRECT ==0 ? usb_rcvctrlpipe(_x,0) : usb_sndctrlpipe(_x,0))
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#define REG_BUF_SIZE(_x) ((_x)->bRequest== 0x04 ? cpu_to_le16((_x)->wLength) : 4)
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// 20060613.2 Add the follow definition
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#define BB48_DEFAULT_AL2230_11B 0x0033447c
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#define BB4C_DEFAULT_AL2230_11B 0x0A00FEFF
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#define BB48_DEFAULT_AL2230_11G 0x00332C1B
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#define BB4C_DEFAULT_AL2230_11G 0x0A00FEFF
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#define BB48_DEFAULT_WB242_11B 0x00292315 //backoff 2dB
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#define BB4C_DEFAULT_WB242_11B 0x0800FEFF //backoff 2dB
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//#define BB48_DEFAULT_WB242_11B 0x00201B11 //backoff 4dB
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//#define BB4C_DEFAULT_WB242_11B 0x0600FF00 //backoff 4dB
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#define BB48_DEFAULT_WB242_11B 0x00292315 /* backoff 2dB */
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#define BB4C_DEFAULT_WB242_11B 0x0800FEFF /* backoff 2dB */
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#define BB48_DEFAULT_WB242_11G 0x00453B24
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#define BB4C_DEFAULT_WB242_11G 0x0E00FEFF
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//====================================
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// Default setting for Mxx
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//====================================
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#define DEFAULT_CWMIN 31 //(M2C) CWmin. Its value is in the range 0-31.
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#define DEFAULT_CWMAX 1023 //(M2C) CWmax. Its value is in the range 0-1023.
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#define DEFAULT_AID 1 //(M34) AID. Its value is in the range 1-2007.
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/*
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* ====================================
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* Default setting for Mxx
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* ====================================
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*/
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#define DEFAULT_CWMIN 31 /* (M2C) CWmin. Its value is in the range 0-31. */
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#define DEFAULT_CWMAX 1023 /* (M2C) CWmax. Its value is in the range 0-1023. */
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#define DEFAULT_AID 1 /* (M34) AID. Its value is in the range 1-2007. */
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#ifdef _USE_FALLBACK_RATE_
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#define DEFAULT_RATE_RETRY_LIMIT 2 //(M38) as named
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#define DEFAULT_RATE_RETRY_LIMIT 2 /* (M38) as named */
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#else
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#define DEFAULT_RATE_RETRY_LIMIT 7 //(M38) as named
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#define DEFAULT_RATE_RETRY_LIMIT 7 /* (M38) as named */
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#endif
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#define DEFAULT_LONG_RETRY_LIMIT 7 //(M38) LongRetryLimit. Its value is in the range 0-15.
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#define DEFAULT_SHORT_RETRY_LIMIT 7 //(M38) ShortRetryLimit. Its value is in the range 0-15.
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#define DEFAULT_PIFST 25 //(M3C) PIFS Time. Its value is in the range 0-65535.
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#define DEFAULT_EIFST 354 //(M3C) EIFS Time. Its value is in the range 0-1048575.
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#define DEFAULT_DIFST 45 //(M3C) DIFS Time. Its value is in the range 0-65535.
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#define DEFAULT_SIFST 5 //(M3C) SIFS Time. Its value is in the range 0-65535.
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#define DEFAULT_OSIFST 10 //(M3C) Original SIFS Time. Its value is in the range 0-15.
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#define DEFAULT_ATIMWD 0 //(M40) ATIM Window. Its value is in the range 0-65535.
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#define DEFAULT_SLOT_TIME 20 //(M40) ($) SlotTime. Its value is in the range 0-255.
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#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 //(M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295.
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#define DEFAULT_BEACON_INTERVAL 500 //(M48) Beacon Interval. Its value is in the range 0-65535.
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#define DEFAULT_PROBE_DELAY_TIME 200 //(M48) Probe Delay Time. Its value is in the range 0-65535.
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#define DEFAULT_PROTOCOL_VERSION 0 //(M4C)
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#define DEFAULT_MAC_POWER_STATE 2 //(M4C) 2: MAC at power active
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#define DEFAULT_DTIM_ALERT_TIME 0
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#define DEFAULT_LONG_RETRY_LIMIT 7 /* (M38) LongRetryLimit. Its value is in the range 0-15. */
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#define DEFAULT_SHORT_RETRY_LIMIT 7 /* (M38) ShortRetryLimit. Its value is in the range 0-15. */
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#define DEFAULT_PIFST 25 /* (M3C) PIFS Time. Its value is in the range 0-65535. */
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#define DEFAULT_EIFST 354 /* (M3C) EIFS Time. Its value is in the range 0-1048575. */
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#define DEFAULT_DIFST 45 /* (M3C) DIFS Time. Its value is in the range 0-65535. */
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#define DEFAULT_SIFST 5 /* (M3C) SIFS Time. Its value is in the range 0-65535. */
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#define DEFAULT_OSIFST 10 /* (M3C) Original SIFS Time. Its value is in the range 0-15. */
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#define DEFAULT_ATIMWD 0 /* (M40) ATIM Window. Its value is in the range 0-65535. */
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#define DEFAULT_SLOT_TIME 20 /* (M40) ($) SlotTime. Its value is in the range 0-255. */
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#define DEFAULT_MAX_TX_MSDU_LIFE_TIME 512 /* (M44) MaxTxMSDULifeTime. Its value is in the range 0-4294967295. */
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#define DEFAULT_BEACON_INTERVAL 500 /* (M48) Beacon Interval. Its value is in the range 0-65535. */
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#define DEFAULT_PROBE_DELAY_TIME 200 /* (M48) Probe Delay Time. Its value is in the range 0-65535. */
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#define DEFAULT_PROTOCOL_VERSION 0 /* (M4C) */
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#define DEFAULT_MAC_POWER_STATE 2 /* (M4C) 2: MAC at power active */
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#define DEFAULT_DTIM_ALERT_TIME 0
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struct wb35_reg_queue {
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struct urb *urb;
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struct urb *urb;
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void *pUsbReq;
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void *Next;
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union {
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u32 VALUE;
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u32 *pBuffer;
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};
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u8 RESERVED[4]; // space reserved for communication
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u16 INDEX; // For storing the register index
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u8 RESERVED_VALID; // Indicate whether the RESERVED space is valid at this command.
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u8 DIRECT; // 0:In 1:Out
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u8 RESERVED[4]; /* space reserved for communication */
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u16 INDEX; /* For storing the register index */
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u8 RESERVED_VALID; /* Indicate whether the RESERVED space is valid at this command. */
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u8 DIRECT; /* 0:In 1:Out */
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};
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//====================================
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// Internal variable for module
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//====================================
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/*
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* ====================================
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* Internal variable for module
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* ====================================
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*/
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#define MAX_SQ3_FILTER_SIZE 5
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struct wb35_reg {
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//============================
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// Register Bank backup
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//============================
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u32 U1B0; //bit16 record the h/w radio on/off status
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/*
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* ============================
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* Register Bank backup
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* ============================
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*/
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u32 U1B0; /* bit16 record the h/w radio on/off status */
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u32 U1BC_LEDConfigure;
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u32 D00_DmaControl;
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u32 M00_MacControl;
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@ -105,68 +107,65 @@ struct wb35_reg {
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u32 M04_MulticastAddress1;
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u32 M08_MulticastAddress2;
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};
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u8 Multicast[8]; // contents of card multicast registers
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u8 Multicast[8]; /* contents of card multicast registers */
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};
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u32 M24_MacControl;
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u32 M28_MacControl;
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u32 M2C_MacControl;
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u32 M38_MacControl;
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u32 M3C_MacControl; // 20060214 backup only
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u32 M3C_MacControl;
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u32 M40_MacControl;
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u32 M44_MacControl; // 20060214 backup only
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u32 M48_MacControl; // 20060214 backup only
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u32 M44_MacControl;
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u32 M48_MacControl;
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u32 M4C_MacStatus;
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u32 M60_MacControl; // 20060214 backup only
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u32 M68_MacControl; // 20060214 backup only
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u32 M70_MacControl; // 20060214 backup only
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u32 M74_MacControl; // 20060214 backup only
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u32 M78_ERPInformation;//930206.2.b
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u32 M7C_MacControl; // 20060214 backup only
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u32 M80_MacControl; // 20060214 backup only
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u32 M84_MacControl; // 20060214 backup only
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u32 M88_MacControl; // 20060214 backup only
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u32 M98_MacControl; // 20060214 backup only
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u32 M60_MacControl;
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u32 M68_MacControl;
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u32 M70_MacControl;
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u32 M74_MacControl;
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u32 M78_ERPInformation;
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u32 M7C_MacControl;
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u32 M80_MacControl;
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u32 M84_MacControl;
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u32 M88_MacControl;
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u32 M98_MacControl;
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//[20040722 WK]
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//Baseband register
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u32 BB0C; // Used for LNA calculation
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u32 BB2C; //
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u32 BB30; //11b acquisition control register
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/* Baseband register */
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u32 BB0C; /* Used for LNA calculation */
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u32 BB2C;
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u32 BB30; /* 11b acquisition control register */
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u32 BB3C;
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u32 BB48; // 20051221.1.a 20060613.1 Fix OBW issue of 11b/11g rate
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u32 BB4C; // 20060613.1 Fix OBW issue of 11b/11g rate
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u32 BB50; //mode control register
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u32 BB48;
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u32 BB4C;
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u32 BB50; /* mode control register */
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u32 BB54;
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u32 BB58; //IQ_ALPHA
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u32 BB5C; // For test
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u32 BB60; // for WTO read value
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u32 BB58; /* IQ_ALPHA */
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u32 BB5C; /* For test */
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u32 BB60; /* for WTO read value */
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//-------------------
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// VM
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//-------------------
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spinlock_t EP0VM_spin_lock; // 4B
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u32 EP0VM_status;//$$
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/* VM */
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spinlock_t EP0VM_spin_lock; /* 4B */
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u32 EP0VM_status; /* $$ */
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struct wb35_reg_queue *reg_first;
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struct wb35_reg_queue *reg_last;
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atomic_t RegFireCount;
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atomic_t RegFireCount;
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// Hardware status
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/* Hardware status */
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u8 EP0vm_state;
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u8 mac_power_save;
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u8 EEPROMPhyType; // 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
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// 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
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// 32 ~ Reserved
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// 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
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// 48 ~ 255 ARE RESERVED.
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u8 EEPROMRegion; //Region setting in EEPROM
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u8 EEPROMPhyType; /*
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* 0 ~ 15 for Maxim (0 ĄV MAX2825, 1 ĄV MAX2827, 2 ĄV MAX2828, 3 ĄV MAX2829),
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* 16 ~ 31 for Airoha (16 ĄV AL2230, 11 - AL7230)
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* 32 ~ Reserved
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* 33 ~ 47 For WB242 ( 33 - WB242, 34 - WB242 with new Txvga 0.5 db step)
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* 48 ~ 255 ARE RESERVED.
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*/
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u8 EEPROMRegion; /* Region setting in EEPROM */
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u32 SyncIoPause; // If user use the Sync Io to access Hw, then pause the async access
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u32 SyncIoPause; /* If user use the Sync Io to access Hw, then pause the async access */
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u8 LNAValue[4]; //Table for speed up running
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u8 LNAValue[4]; /* Table for speed up running */
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u32 SQ3_filter[MAX_SQ3_FILTER_SIZE];
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u32 SQ3_index;
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};
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#endif
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