[POWERPC] pasemi: PA6T oprofile support
Oprofile support for PA6T, kernel side. Also rename the PA6T_SPRN.* defines to SPRN_PA6T.*. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>wifi-calibration
Olof Johansson
Paul Mackerras
parent
7e8bddf566
commit
25fc530eed
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@ -389,6 +389,8 @@ static struct cpu_spec cpu_specs[] = {
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.pmc_type = PPC_PMC_PA6T,
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.cpu_setup = __setup_cpu_pa6t,
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.cpu_restore = __restore_cpu_pa6t,
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.oprofile_cpu_type = "ppc64/pa6t",
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.oprofile_type = PPC_OPROFILE_PA6T,
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.platform = "pa6t",
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},
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{ /* default match */
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@ -189,12 +189,12 @@ SYSFS_PMCSETUP(purr, SPRN_PURR);
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SYSFS_PMCSETUP(spurr, SPRN_SPURR);
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SYSFS_PMCSETUP(dscr, SPRN_DSCR);
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SYSFS_PMCSETUP(pa6t_pmc0, PA6T_SPRN_PMC0);
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SYSFS_PMCSETUP(pa6t_pmc1, PA6T_SPRN_PMC1);
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SYSFS_PMCSETUP(pa6t_pmc2, PA6T_SPRN_PMC2);
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SYSFS_PMCSETUP(pa6t_pmc3, PA6T_SPRN_PMC3);
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SYSFS_PMCSETUP(pa6t_pmc4, PA6T_SPRN_PMC4);
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SYSFS_PMCSETUP(pa6t_pmc5, PA6T_SPRN_PMC5);
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SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
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SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
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SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
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SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
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SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
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SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
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static SYSDEV_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
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@ -12,6 +12,6 @@ DRIVER_OBJS := $(addprefix ../../../drivers/oprofile/, \
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oprofile-y := $(DRIVER_OBJS) common.o backtrace.o
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oprofile-$(CONFIG_PPC_CELL_NATIVE) += op_model_cell.o
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oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o
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oprofile-$(CONFIG_PPC64) += op_model_rs64.o op_model_power4.o op_model_pa6t.o
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oprofile-$(CONFIG_FSL_BOOKE) += op_model_fsl_booke.o
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oprofile-$(CONFIG_6xx) += op_model_7450.o
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@ -160,6 +160,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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case PPC_OPROFILE_POWER4:
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model = &op_model_power4;
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break;
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case PPC_OPROFILE_PA6T:
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model = &op_model_pa6t;
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break;
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#endif
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#ifdef CONFIG_6xx
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case PPC_OPROFILE_G4:
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@ -0,0 +1,234 @@
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/*
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* Copyright (C) 2006-2007 PA Semi, Inc
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*
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* Author: Shashi Rao, PA Semi
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*
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* Maintained by: Olof Johansson <olof@lixom.net>
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*
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* Based on arch/powerpc/oprofile/op_model_power4.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/percpu.h>
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/oprofile_impl.h>
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#include <asm/reg.h>
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static unsigned char oprofile_running;
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/* mmcr values are set in pa6t_reg_setup, used in pa6t_cpu_setup */
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static u64 mmcr0_val;
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static u64 mmcr1_val;
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/* inited in pa6t_reg_setup */
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static u64 reset_value[OP_MAX_COUNTER];
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static inline u64 ctr_read(unsigned int i)
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{
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switch (i) {
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case 0:
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return mfspr(SPRN_PA6T_PMC0);
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case 1:
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return mfspr(SPRN_PA6T_PMC1);
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case 2:
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return mfspr(SPRN_PA6T_PMC2);
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case 3:
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return mfspr(SPRN_PA6T_PMC3);
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case 4:
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return mfspr(SPRN_PA6T_PMC4);
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case 5:
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return mfspr(SPRN_PA6T_PMC5);
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default:
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printk(KERN_ERR "ctr_read called with bad arg %u\n", i);
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return 0;
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}
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}
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static inline void ctr_write(unsigned int i, u64 val)
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{
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switch (i) {
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case 0:
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mtspr(SPRN_PA6T_PMC0, val);
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break;
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case 1:
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mtspr(SPRN_PA6T_PMC1, val);
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break;
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case 2:
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mtspr(SPRN_PA6T_PMC2, val);
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break;
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case 3:
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mtspr(SPRN_PA6T_PMC3, val);
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break;
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case 4:
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mtspr(SPRN_PA6T_PMC4, val);
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break;
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case 5:
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mtspr(SPRN_PA6T_PMC5, val);
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break;
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default:
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printk(KERN_ERR "ctr_write called with bad arg %u\n", i);
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break;
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}
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}
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/* precompute the values to stuff in the hardware registers */
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static void pa6t_reg_setup(struct op_counter_config *ctr,
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struct op_system_config *sys,
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int num_ctrs)
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{
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int pmc;
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/*
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* adjust the mmcr0.en[0-5] and mmcr0.inten[0-5] values obtained from the
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* event_mappings file by turning off the counters that the user doesn't
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* care about
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*
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* setup user and kernel profiling
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*/
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for (pmc = 0; pmc < cur_cpu_spec->num_pmcs; pmc++)
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if (!ctr[pmc].enabled) {
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sys->mmcr0 &= ~(0x1UL << pmc);
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sys->mmcr0 &= ~(0x1UL << (pmc+12));
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pr_debug("turned off counter %u\n", pmc);
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}
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if (sys->enable_kernel)
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sys->mmcr0 |= PA6T_MMCR0_SUPEN | PA6T_MMCR0_HYPEN;
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else
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sys->mmcr0 &= ~(PA6T_MMCR0_SUPEN | PA6T_MMCR0_HYPEN);
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if (sys->enable_user)
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sys->mmcr0 |= PA6T_MMCR0_PREN;
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else
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sys->mmcr0 &= ~PA6T_MMCR0_PREN;
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/*
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* The performance counter event settings are given in the mmcr0 and
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* mmcr1 values passed from the user in the op_system_config
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* structure (sys variable).
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*/
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mmcr0_val = sys->mmcr0;
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mmcr1_val = sys->mmcr1;
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pr_debug("mmcr0_val inited to %016lx\n", sys->mmcr0);
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pr_debug("mmcr1_val inited to %016lx\n", sys->mmcr1);
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for (pmc = 0; pmc < cur_cpu_spec->num_pmcs; pmc++) {
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/* counters are 40 bit. Move to cputable at some point? */
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reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count;
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pr_debug("reset_value for pmc%u inited to 0x%lx\n",
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pmc, reset_value[pmc]);
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}
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}
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/* configure registers on this cpu */
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static void pa6t_cpu_setup(struct op_counter_config *ctr)
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{
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u64 mmcr0 = mmcr0_val;
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u64 mmcr1 = mmcr1_val;
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/* Default is all PMCs off */
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mmcr0 &= ~(0x3FUL);
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mtspr(SPRN_PA6T_MMCR0, mmcr0);
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/* program selected programmable events in */
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mtspr(SPRN_PA6T_MMCR1, mmcr1);
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pr_debug("setup on cpu %d, mmcr0 %016lx\n", smp_processor_id(),
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mfspr(SPRN_PA6T_MMCR0));
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pr_debug("setup on cpu %d, mmcr1 %016lx\n", smp_processor_id(),
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mfspr(SPRN_PA6T_MMCR1));
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}
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static void pa6t_start(struct op_counter_config *ctr)
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{
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int i;
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/* Hold off event counting until rfid */
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u64 mmcr0 = mmcr0_val | PA6T_MMCR0_HANDDIS;
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for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
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if (ctr[i].enabled)
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ctr_write(i, reset_value[i]);
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else
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ctr_write(i, 0UL);
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mtspr(SPRN_PA6T_MMCR0, mmcr0);
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oprofile_running = 1;
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pr_debug("start on cpu %d, mmcr0 %lx\n", smp_processor_id(), mmcr0);
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}
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static void pa6t_stop(void)
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{
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u64 mmcr0;
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/* freeze counters */
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mmcr0 = mfspr(SPRN_PA6T_MMCR0);
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mmcr0 |= PA6T_MMCR0_FCM0;
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mtspr(SPRN_PA6T_MMCR0, mmcr0);
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oprofile_running = 0;
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pr_debug("stop on cpu %d, mmcr0 %lx\n", smp_processor_id(), mmcr0);
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}
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/* handle the perfmon overflow vector */
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static void pa6t_handle_interrupt(struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pc = mfspr(SPRN_PA6T_SIAR);
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int is_kernel = is_kernel_addr(pc);
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u64 val;
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int i;
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u64 mmcr0;
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/* disable perfmon counting until rfid */
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mmcr0 = mfspr(SPRN_PA6T_MMCR0);
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mtspr(SPRN_PA6T_MMCR0, mmcr0 | PA6T_MMCR0_HANDDIS);
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/* Record samples. We've got one global bit for whether a sample
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* was taken, so add it for any counter that triggered overflow.
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*/
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for (i = 0; i < cur_cpu_spec->num_pmcs; i++) {
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val = ctr_read(i);
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if (val & (0x1UL << 39)) { /* Overflow bit set */
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if (oprofile_running && ctr[i].enabled) {
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if (mmcr0 & PA6T_MMCR0_SIARLOG)
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oprofile_add_ext_sample(pc, regs, i, is_kernel);
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ctr_write(i, reset_value[i]);
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} else {
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ctr_write(i, 0UL);
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}
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}
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}
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/* Restore mmcr0 to a good known value since the PMI changes it */
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mmcr0 = mmcr0_val | PA6T_MMCR0_HANDDIS;
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mtspr(SPRN_PA6T_MMCR0, mmcr0);
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}
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struct op_powerpc_model op_model_pa6t = {
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.reg_setup = pa6t_reg_setup,
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.cpu_setup = pa6t_cpu_setup,
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.start = pa6t_start,
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.stop = pa6t_stop,
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.handle_interrupt = pa6t_handle_interrupt,
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};
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@ -48,6 +48,7 @@ enum powerpc_oprofile_type {
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PPC_OPROFILE_G4 = 3,
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PPC_OPROFILE_BOOKE = 4,
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PPC_OPROFILE_CELL = 5,
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PPC_OPROFILE_PA6T = 6,
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};
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enum powerpc_pmc_type {
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@ -57,6 +57,8 @@ extern struct op_powerpc_model op_model_rs64;
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extern struct op_powerpc_model op_model_power4;
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extern struct op_powerpc_model op_model_7450;
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extern struct op_powerpc_model op_model_cell;
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extern struct op_powerpc_model op_model_pa6t;
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/* All the classic PPC parts use these */
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static inline unsigned int classic_ctr_read(unsigned int i)
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@ -30,6 +30,7 @@ void release_pmc_hardware(void);
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#ifdef CONFIG_PPC64
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void power4_enable_pmcs(void);
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void pasemi_enable_pmcs(void);
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#endif
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#endif /* __KERNEL__ */
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@ -469,12 +469,68 @@
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#define SPRN_SIAR 780
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#define SPRN_SDAR 781
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#define PA6T_SPRN_PMC0 787
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#define PA6T_SPRN_PMC1 788
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#define PA6T_SPRN_PMC2 789
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#define PA6T_SPRN_PMC3 790
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#define PA6T_SPRN_PMC4 791
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#define PA6T_SPRN_PMC5 792
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#define SPRN_PA6T_MMCR0 795
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#define PA6T_MMCR0_EN0 0x0000000000000001UL
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#define PA6T_MMCR0_EN1 0x0000000000000002UL
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#define PA6T_MMCR0_EN2 0x0000000000000004UL
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#define PA6T_MMCR0_EN3 0x0000000000000008UL
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#define PA6T_MMCR0_EN4 0x0000000000000010UL
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#define PA6T_MMCR0_EN5 0x0000000000000020UL
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#define PA6T_MMCR0_SUPEN 0x0000000000000040UL
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#define PA6T_MMCR0_PREN 0x0000000000000080UL
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#define PA6T_MMCR0_HYPEN 0x0000000000000100UL
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#define PA6T_MMCR0_FCM0 0x0000000000000200UL
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#define PA6T_MMCR0_FCM1 0x0000000000000400UL
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#define PA6T_MMCR0_INTGEN 0x0000000000000800UL
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#define PA6T_MMCR0_INTEN0 0x0000000000001000UL
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#define PA6T_MMCR0_INTEN1 0x0000000000002000UL
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#define PA6T_MMCR0_INTEN2 0x0000000000004000UL
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#define PA6T_MMCR0_INTEN3 0x0000000000008000UL
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#define PA6T_MMCR0_INTEN4 0x0000000000010000UL
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#define PA6T_MMCR0_INTEN5 0x0000000000020000UL
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#define PA6T_MMCR0_DISCNT 0x0000000000040000UL
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#define PA6T_MMCR0_UOP 0x0000000000080000UL
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#define PA6T_MMCR0_TRG 0x0000000000100000UL
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#define PA6T_MMCR0_TRGEN 0x0000000000200000UL
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#define PA6T_MMCR0_TRGREG 0x0000000001600000UL
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#define PA6T_MMCR0_SIARLOG 0x0000000002000000UL
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#define PA6T_MMCR0_SDARLOG 0x0000000004000000UL
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#define PA6T_MMCR0_PROEN 0x0000000008000000UL
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#define PA6T_MMCR0_PROLOG 0x0000000010000000UL
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#define PA6T_MMCR0_DAMEN2 0x0000000020000000UL
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#define PA6T_MMCR0_DAMEN3 0x0000000040000000UL
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#define PA6T_MMCR0_DAMEN4 0x0000000080000000UL
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#define PA6T_MMCR0_DAMEN5 0x0000000100000000UL
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#define PA6T_MMCR0_DAMSEL2 0x0000000200000000UL
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#define PA6T_MMCR0_DAMSEL3 0x0000000400000000UL
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#define PA6T_MMCR0_DAMSEL4 0x0000000800000000UL
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#define PA6T_MMCR0_DAMSEL5 0x0000001000000000UL
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#define PA6T_MMCR0_HANDDIS 0x0000002000000000UL
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#define PA6T_MMCR0_PCTEN 0x0000004000000000UL
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#define PA6T_MMCR0_SOCEN 0x0000008000000000UL
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#define PA6T_MMCR0_SOCMOD 0x0000010000000000UL
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#define SPRN_PA6T_MMCR1 798
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#define PA6T_MMCR1_ES2 0x00000000000000ffUL
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#define PA6T_MMCR1_ES3 0x000000000000ff00UL
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#define PA6T_MMCR1_ES4 0x0000000000ff0000UL
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#define PA6T_MMCR1_ES5 0x00000000ff000000UL
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#define SPRN_PA6T_SIAR 780
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#define SPRN_PA6T_UPMC0 771
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#define SPRN_PA6T_UPMC1 772
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#define SPRN_PA6T_UPMC2 773
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#define SPRN_PA6T_UPMC3 774
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#define SPRN_PA6T_UPMC4 775
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#define SPRN_PA6T_UPMC5 776
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#define SPRN_PA6T_UMMCR0 779
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#define SPRN_PA6T_UMMCR1 782
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#define SPRN_PA6T_PMC0 787
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#define SPRN_PA6T_PMC1 788
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#define SPRN_PA6T_PMC2 789
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#define SPRN_PA6T_PMC3 790
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#define SPRN_PA6T_PMC4 791
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#define SPRN_PA6T_PMC5 792
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#else /* 32-bit */
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#define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */
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