ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores
HS release 3.0 provides for even more flexibility in specifying the volatile address space for mapping peripherals. With HS 2.1 @start was made flexible / programmable - with HS 3.0 even @end can be setup (vs. fixed to 0xFFFF_FFFF before). So add code to reflect that and while at it remove an unused struct defintion Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -95,7 +95,7 @@
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/* Auxiliary registers */
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#define AUX_IDENTITY 4
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#define AUX_INTR_VEC_BASE 0x25
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#define AUX_NON_VOL 0x5e
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#define AUX_VOL 0x5e
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/*
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* Floating Pt Registers
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@ -240,14 +240,6 @@ struct bcr_extn_xymem {
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#endif
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};
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struct bcr_perip {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int start:8, pad2:8, sz:8, ver:8;
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#else
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unsigned int ver:8, sz:8, pad2:8, start:8;
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#endif
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};
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struct bcr_iccm_arcompact {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int base:16, pad:5, sz:3, ver:8;
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@ -54,7 +54,7 @@ extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
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extern void read_decode_cache_bcr(void);
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extern int ioc_exists;
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extern unsigned long perip_base;
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extern unsigned long perip_base, perip_end;
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#endif /* !__ASSEMBLY__ */
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@ -273,8 +273,8 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
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FIX_PTR(cpu);
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n += scnprintf(buf + n, len - n,
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"Vector Table\t: %#x\nUncached Base\t: %#lx\n",
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cpu->vec_base, perip_base);
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"Vector Table\t: %#x\nPeripherals\t: %#lx:%#lx\n",
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cpu->vec_base, perip_base, perip_end);
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if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
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n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
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@ -25,6 +25,7 @@ static int l2_line_sz;
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int ioc_exists;
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volatile int slc_enable = 1, ioc_enable = 1;
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unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
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unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
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void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
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unsigned long sz, const int cacheop);
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@ -76,7 +77,6 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
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static void read_decode_cache_bcr_arcv2(int cpu)
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{
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struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
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struct bcr_generic uncached_space;
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struct bcr_generic sbcr;
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struct bcr_slc_cfg {
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@ -95,6 +95,15 @@ static void read_decode_cache_bcr_arcv2(int cpu)
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#endif
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} cbcr;
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struct bcr_volatile {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int start:4, limit:4, pad:22, order:1, disable:1;
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#else
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unsigned int disable:1, order:1, pad:22, limit:4, start:4;
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#endif
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} vol;
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READ_BCR(ARC_REG_SLC_BCR, sbcr);
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if (sbcr.ver) {
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READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
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@ -107,10 +116,14 @@ static void read_decode_cache_bcr_arcv2(int cpu)
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if (cbcr.c && ioc_enable)
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ioc_exists = 1;
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/* Legacy Data Uncached BCR is deprecated from v3 onwards */
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READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
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if (uncached_space.ver > 2)
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perip_base = read_aux_reg(AUX_NON_VOL) & 0xF0000000;
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/* HS 2.0 didn't have AUX_VOL */
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if (cpuinfo_arc700[cpu].core.family > 0x51) {
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READ_BCR(AUX_VOL, vol);
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perip_base = vol.start << 28;
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/* HS 3.0 has limit and strict-ordering fields */
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if (cpuinfo_arc700[cpu].core.family > 0x52)
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perip_end = (vol.limit << 28) - 1;
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}
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}
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void read_decode_cache_bcr(void)
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@ -19,7 +19,7 @@ static inline bool arc_uncached_addr_space(phys_addr_t paddr)
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if (is_isa_arcompact()) {
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if (paddr >= ARC_UNCACHED_ADDR_SPACE)
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return true;
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} else if (paddr >= perip_base && paddr <= 0xFFFFFFFF) {
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} else if (paddr >= perip_base && paddr <= perip_end) {
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return true;
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}
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