Merge branch 'omap-for-v4.6/dt-gpmc' into omap-for-v4.6/dt
This commit is contained in:
commit
26c23ee657
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@ -236,7 +236,11 @@
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||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
reg = <0 0 0>; /* CS0, offset 0 */
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,nand-xfer-type = "polled";
|
ti,nand-xfer-type = "polled";
|
||||||
|
@ -257,12 +261,9 @@
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
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||||||
gpmc,rd-cycle-ns = <82>;
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gpmc,rd-cycle-ns = <82>;
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||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
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||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
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gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
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gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
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gpmc,wr-access-ns = <40>;
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||||||
gpmc,wr-data-mux-bus-ns = <0>;
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gpmc,wr-data-mux-bus-ns = <0>;
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||||||
|
|
||||||
|
|
|
@ -7,6 +7,7 @@
|
||||||
* published by the Free Software Foundation.
|
* published by the Free Software Foundation.
|
||||||
*/
|
*/
|
||||||
#include "am33xx.dtsi"
|
#include "am33xx.dtsi"
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||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
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||||||
|
|
||||||
/ {
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/ {
|
||||||
model = "Grinn AM335x ChiliSOM";
|
model = "Grinn AM335x ChiliSOM";
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||||||
|
@ -218,7 +219,11 @@
|
||||||
pinctrl-0 = <&nandflash_pins>;
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pinctrl-0 = <&nandflash_pins>;
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||||||
ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
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ranges = <0 0 0x08000000 0x01000000>; /* CS0 0 @addr 0x08000000, size 0x01000000 */
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||||||
nand@0,0 {
|
nand@0,0 {
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||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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||||||
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<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
|
@ -237,12 +242,9 @@
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
|
||||||
gpmc,rd-cycle-ns = <82>;
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gpmc,rd-cycle-ns = <82>;
|
||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -406,7 +406,11 @@ status = "okay";
|
||||||
pinctrl-0 = <&nandflash_pins>;
|
pinctrl-0 = <&nandflash_pins>;
|
||||||
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
reg = <0 0 0>; /* CS0, offset 0 */
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
|
@ -425,12 +429,9 @@ status = "okay";
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
|
||||||
gpmc,rd-cycle-ns = <82>;
|
gpmc,rd-cycle-ns = <82>;
|
||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
|
|
|
@ -519,7 +519,11 @@
|
||||||
pinctrl-0 = <&nandflash_pins_s0>;
|
pinctrl-0 = <&nandflash_pins_s0>;
|
||||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
|
@ -538,12 +542,9 @@
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
|
||||||
gpmc,rd-cycle-ns = <82>;
|
gpmc,rd-cycle-ns = <82>;
|
||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
|
|
|
@ -11,6 +11,7 @@
|
||||||
/dts-v1/;
|
/dts-v1/;
|
||||||
|
|
||||||
#include "am33xx.dtsi"
|
#include "am33xx.dtsi"
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
cpus {
|
cpus {
|
||||||
|
@ -129,7 +130,11 @@
|
||||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
gpmc,device-width = <1>;
|
gpmc,device-width = <1>;
|
||||||
|
@ -147,12 +152,9 @@
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
|
||||||
gpmc,rd-cycle-ns = <82>;
|
gpmc,rd-cycle-ns = <82>;
|
||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
|
|
||||||
|
|
|
@ -8,6 +8,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "am33xx.dtsi"
|
#include "am33xx.dtsi"
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "Phytec AM335x phyCORE";
|
model = "Phytec AM335x phyCORE";
|
||||||
|
@ -165,7 +166,11 @@
|
||||||
pinctrl-0 = <&nandflash_pins>;
|
pinctrl-0 = <&nandflash_pins>;
|
||||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
|
ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
|
||||||
nandflash: nand@0,0 {
|
nandflash: nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
gpmc,device-nand = "true";
|
gpmc,device-nand = "true";
|
||||||
|
@ -184,13 +189,10 @@
|
||||||
gpmc,access-ns = <30>;
|
gpmc,access-ns = <30>;
|
||||||
gpmc,rd-cycle-ns = <30>;
|
gpmc,rd-cycle-ns = <30>;
|
||||||
gpmc,wr-cycle-ns = <30>;
|
gpmc,wr-cycle-ns = <30>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <50>;
|
gpmc,cycle2cycle-delay-ns = <50>;
|
||||||
gpmc,cycle2cycle-diffcsen;
|
gpmc,cycle2cycle-diffcsen;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <30>;
|
gpmc,wr-access-ns = <30>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
|
|
||||||
|
|
|
@ -865,6 +865,8 @@
|
||||||
gpmc,num-waitpins = <2>;
|
gpmc,num-waitpins = <2>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -893,6 +893,8 @@
|
||||||
gpmc,num-waitpins = <2>;
|
gpmc,num-waitpins = <2>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -146,7 +146,11 @@
|
||||||
pinctrl-0 = <&nand_flash_x8>;
|
pinctrl-0 = <&nand_flash_x8>;
|
||||||
ranges = <0 0 0x08000000 0x1000000>;
|
ranges = <0 0 0x08000000 0x1000000>;
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
reg = <0 0 0>;
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
|
|
||||||
|
@ -166,17 +170,12 @@
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
|
||||||
gpmc,rd-cycle-ns = <82>;
|
gpmc,rd-cycle-ns = <82>;
|
||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
|
|
||||||
gpmc,wait-pin = <0>;
|
|
||||||
|
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
|
|
|
@ -812,9 +812,13 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&nand_flash_x8>;
|
pinctrl-0 = <&nand_flash_x8>;
|
||||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* device IO registers */
|
reg = <0 0 4>; /* device IO registers */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch16";
|
ti,nand-ecc-opt = "bch16";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
|
@ -833,11 +837,9 @@
|
||||||
gpmc,access-ns = <30>;
|
gpmc,access-ns = <30>;
|
||||||
gpmc,rd-cycle-ns = <40>;
|
gpmc,rd-cycle-ns = <40>;
|
||||||
gpmc,wr-cycle-ns = <40>;
|
gpmc,wr-cycle-ns = <40>;
|
||||||
gpmc,wait-pin = <0>;
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
|
|
|
@ -561,9 +561,13 @@
|
||||||
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
|
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&nand_flash_x8>;
|
pinctrl-0 = <&nand_flash_x8>;
|
||||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch16";
|
ti,nand-ecc-opt = "bch16";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
|
@ -582,11 +586,9 @@
|
||||||
gpmc,access-ns = <30>; /* tCEA + 4*/
|
gpmc,access-ns = <30>; /* tCEA + 4*/
|
||||||
gpmc,rd-cycle-ns = <40>;
|
gpmc,rd-cycle-ns = <40>;
|
||||||
gpmc,wr-cycle-ns = <40>;
|
gpmc,wr-cycle-ns = <40>;
|
||||||
gpmc,wait-pin = <0>;
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
|
|
|
@ -6,6 +6,7 @@
|
||||||
/dts-v1/;
|
/dts-v1/;
|
||||||
|
|
||||||
#include "dm816x.dtsi"
|
#include "dm816x.dtsi"
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "DM8168 EVM";
|
model = "DM8168 EVM";
|
||||||
|
@ -85,8 +86,12 @@
|
||||||
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
linux,mtd-name= "micron,mt29f2g16aadwp";
|
linux,mtd-name= "micron,mt29f2g16aadwp";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
@ -106,12 +111,9 @@
|
||||||
gpmc,access-ns = <64>;
|
gpmc,access-ns = <64>;
|
||||||
gpmc,rd-cycle-ns = <82>;
|
gpmc,rd-cycle-ns = <82>;
|
||||||
gpmc,wr-cycle-ns = <82>;
|
gpmc,wr-cycle-ns = <82>;
|
||||||
gpmc,wait-on-read = "true";
|
|
||||||
gpmc,wait-on-write = "true";
|
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-access-ns = <40>;
|
gpmc,wr-access-ns = <40>;
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
partition@0 {
|
partition@0 {
|
||||||
|
|
|
@ -183,6 +183,8 @@
|
||||||
dma-names = "rxtx";
|
dma-names = "rxtx";
|
||||||
gpmc,num-cs = <6>;
|
gpmc,num-cs = <6>;
|
||||||
gpmc,num-waitpins = <2>;
|
gpmc,num-waitpins = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c1: i2c@48028000 {
|
i2c1: i2c@48028000 {
|
||||||
|
|
|
@ -741,9 +741,13 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&nand_flash_x16>;
|
pinctrl-0 = <&nand_flash_x16>;
|
||||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* device IO registers */
|
reg = <0 0 4>; /* device IO registers */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
|
@ -766,7 +770,6 @@
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
/* All SPL-* partitions are sized to minimal length
|
/* All SPL-* partitions are sized to minimal length
|
||||||
|
|
|
@ -1402,6 +1402,8 @@
|
||||||
gpmc,num-waitpins = <2>;
|
gpmc,num-waitpins = <2>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -492,13 +492,17 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&nand_default>;
|
pinctrl-0 = <&nand_default>;
|
||||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
/* To use NAND, DIP switch SW5 must be set like so:
|
/* To use NAND, DIP switch SW5 must be set like so:
|
||||||
* SW5.1 (NAND_SELn) = ON (LOW)
|
* SW5.1 (NAND_SELn) = ON (LOW)
|
||||||
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
||||||
*/
|
*/
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* device IO registers */
|
reg = <0 0 4>; /* device IO registers */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
ti,elm-id = <&elm>;
|
ti,elm-id = <&elm>;
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
|
@ -521,7 +525,6 @@
|
||||||
gpmc,bus-turnaround-ns = <0>;
|
gpmc,bus-turnaround-ns = <0>;
|
||||||
gpmc,cycle2cycle-delay-ns = <0>;
|
gpmc,cycle2cycle-delay-ns = <0>;
|
||||||
gpmc,clk-activation-ns = <0>;
|
gpmc,clk-activation-ns = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
|
||||||
gpmc,wr-data-mux-bus-ns = <0>;
|
gpmc,wr-data-mux-bus-ns = <0>;
|
||||||
/* MTD partition table */
|
/* MTD partition table */
|
||||||
/* All SPL-* partitions are sized to minimal length
|
/* All SPL-* partitions are sized to minimal length
|
||||||
|
|
|
@ -102,7 +102,8 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */
|
ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
|
||||||
|
1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */
|
||||||
|
|
||||||
ethernet@gpmc {
|
ethernet@gpmc {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
|
@ -35,11 +35,15 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
|
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
gpmc,sync-clk-ps = <0>;
|
gpmc,sync-clk-ps = <0>;
|
||||||
|
|
|
@ -384,8 +384,11 @@
|
||||||
|
|
||||||
/* Chip select 0 */
|
/* Chip select 0 */
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
|
reg = <0 0 4>; /* NAND I/O window, 4 bytes */
|
||||||
interrupts = <20>;
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
ti,nand-ecc-opt = "ham1";
|
ti,nand-ecc-opt = "ham1";
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
|
@ -261,10 +261,14 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x00000000 0x01000000>;
|
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
gpmc,device-width = <1>;
|
gpmc,device-width = <1>;
|
||||||
ti,nand-ecc-opt = "sw";
|
ti,nand-ecc-opt = "sw";
|
||||||
|
|
|
@ -204,7 +204,11 @@
|
||||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
ti,nand-ecc-opt = "sw";
|
ti,nand-ecc-opt = "sw";
|
||||||
|
|
|
@ -154,12 +154,16 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
|
ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */
|
||||||
<5 0 0x2c000000 0x01000000>;
|
<5 0 0x2c000000 0x01000000>;
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
linux,mtd-name= "hynix,h8kds0un0mer-4em";
|
linux,mtd-name= "hynix,h8kds0un0mer-4em";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
|
|
@ -492,7 +492,11 @@
|
||||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
|
||||||
|
|
|
@ -99,8 +99,12 @@
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
linux,mtd-name= "micron,mt29c4g96maz";
|
linux,mtd-name= "micron,mt29c4g96maz";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
|
|
@ -210,8 +210,8 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x00000000 0x20000000>,
|
ranges = <0 0 0x30000000 0x01000000>, /* CS0: 16MB for NAND */
|
||||||
<5 0 0x2c000000 0x01000000>;
|
<5 0 0x2c000000 0x01000000>; /* CS5: 16MB for ethernet */
|
||||||
|
|
||||||
ethernet@gpmc {
|
ethernet@gpmc {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
|
@ -99,3 +99,7 @@
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&uart2_pins>;
|
pinctrl-0 = <&uart2_pins>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&gpmc {
|
||||||
|
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||||
|
};
|
||||||
|
|
|
@ -97,12 +97,16 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x00000000 0x01000000>,
|
ranges = <0 0 0x30000000 0x1000000>, /* CS0 space, 16MB */
|
||||||
<1 0 0x08000000 0x01000000>;
|
<1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
linux,mtd-name= "micron,nand";
|
linux,mtd-name= "micron,nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
|
|
@ -362,7 +362,11 @@
|
||||||
<7 0 0x15000000 0x01000000>;
|
<7 0 0x15000000 0x01000000>;
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
/* no elm on omap3 */
|
/* no elm on omap3 */
|
||||||
|
|
|
@ -226,8 +226,12 @@
|
||||||
ranges = <0 0 0x00000000 0x20000000>;
|
ranges = <0 0 0x00000000 0x20000000>;
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
linux,mtd-name= "micron,mt29c4g96maz";
|
linux,mtd-name= "micron,mt29c4g96maz";
|
||||||
reg = <0 0 0>;
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
||||||
|
|
|
@ -546,7 +546,11 @@
|
||||||
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
ti,nand-ecc-opt = "sw";
|
ti,nand-ecc-opt = "sw";
|
||||||
|
|
||||||
|
|
|
@ -275,10 +275,14 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
&gpmc {
|
&gpmc {
|
||||||
ranges = <0 0 0x00000000 0x01000000>;
|
ranges = <0 0 0x30000000 0x01000000>; /* CS0: 16MB for NAND */
|
||||||
|
|
||||||
nand@0,0 {
|
nand@0,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
|
gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
|
||||||
ti,nand-ecc-opt = "sw";
|
ti,nand-ecc-opt = "sw";
|
||||||
|
|
|
@ -723,6 +723,8 @@
|
||||||
gpmc,num-waitpins = <4>;
|
gpmc,num-waitpins = <4>;
|
||||||
#address-cells = <2>;
|
#address-cells = <2>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
usb_otg_hs: usb_otg_hs@480ab000 {
|
usb_otg_hs: usb_otg_hs@480ab000 {
|
||||||
|
|
|
@ -103,10 +103,14 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
nand@1,0 {
|
nand@1,0 {
|
||||||
|
compatible = "ti,omap2-nand";
|
||||||
|
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||||
|
interrupt-parent = <&gpmc>;
|
||||||
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||||
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||||
linux,mtd-name= "micron,mt29f1g08abb";
|
linux,mtd-name= "micron,mt29f1g08abb";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
|
|
||||||
ti,nand-ecc-opt = "sw";
|
ti,nand-ecc-opt = "sw";
|
||||||
nand-bus-width = <8>;
|
nand-bus-width = <8>;
|
||||||
gpmc,cs-on-ns = <0>;
|
gpmc,cs-on-ns = <0>;
|
||||||
|
|
Loading…
Reference in a new issue