[SPARC64]: Temporary workaround for PCI-E slot on T1000.
The PCI-E slot on T1000 connects directly to the Fire PCI chip with no intervening bridges visible in the OBP tree. Unfortunately the bus numbering of the device in that slot is different (2) from the PCI host controller (0), and thus the pci_bus_{read,write}_config_*() calls don't work out. Complicating things further the Fire PCI controller has no config space it responds to either. For now treat this case specially so that devices in the slot work. Longer term we need to perhaps cons up a dummy bridge between the Fire and the PCI-E slot so that the bus hierarchy is complete inside of the kernel and thus the bus numbering all works out right. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -264,7 +264,7 @@ static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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unsigned int func = PCI_FUNC(devfn);
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unsigned long ret;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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if (!bus && devfn == 0x00)
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return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
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size, value);
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if (config_out_of_range(pbm, bus, devfn, where)) {
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@ -300,7 +300,7 @@ static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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unsigned int func = PCI_FUNC(devfn);
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unsigned long ret;
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if (bus_dev == pbm->pci_bus && devfn == 0x00)
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if (!bus && devfn == 0x00)
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return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
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size, value);
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if (config_out_of_range(pbm, bus, devfn, where)) {
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