xtensa: support highmem in aliasing cache flushing code
Use __flush_invalidate_dcache_page_alias with alias set to color of the page physical address instead of __flush_invalidate_dcache_page: this works for high memory pages and mapping/unmapping to the TLBTEMP area is virtually free. Allow building configurations with aliasing cache and highmem enabled. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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@ -59,10 +59,6 @@
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*
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && defined(CONFIG_HIGHMEM)
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#error "HIGHMEM is not supported on cores with aliasing cache."
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#endif
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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static inline void kmap_invalidate_coherent(struct page *page,
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unsigned long vaddr)
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@ -166,7 +162,8 @@ void flush_dcache_page(struct page *page)
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if (!alias && !mapping)
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return;
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__flush_invalidate_dcache_page((long)page_address(page));
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virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(virt, phys);
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virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
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@ -231,13 +228,12 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
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if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
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unsigned long paddr = (unsigned long) page_address(page);
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unsigned long phys = page_to_phys(page);
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unsigned long tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page(paddr);
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unsigned long tmp;
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tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(tmp, phys);
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tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
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__flush_invalidate_dcache_page_alias(tmp, phys);
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__invalidate_icache_page_alias(tmp, phys);
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