Merge branch 'drm-fixes-3.18' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
- fix missing crtc unlock in MC setup - set optimal CE ram config - use gart rather than vram for DMA IB tests to avoid coherency issues with HDP - fix a crasher with laptop mode and TDP scripts * 'drm-fixes-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: add missing crtc unlock when setting up the MC drm/radeon: use gart for DMA IB tests drm/radeon: make sure mode init is complete in bandwidth_update drm/radeon: set correct CE ram size for CIK
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commit
2730fa0d8d
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@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev)
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/* init the CE partitions. CE only used for gfx on CIK */
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radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
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radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0xc000);
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radeon_ring_write(ring, 0x8000);
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radeon_ring_write(ring, 0x8000);
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/* setup clear context state */
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radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon_device *rdev)
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u32 num_heads = 0, lb_size;
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int i;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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for (i = 0; i < rdev->num_crtc; i++) {
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@ -667,17 +667,20 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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unsigned index;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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gpu_addr = rdev->wb.gpu_addr + index;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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rdev->wb.wb[index/4] = cpu_to_le32(tmp);
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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@ -686,8 +689,8 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
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ib.ptr[1] = lower_32_bits(gpu_addr);
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ib.ptr[2] = upper_32_bits(gpu_addr);
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ib.ptr[3] = 1;
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ib.ptr[4] = 0xDEADBEEF;
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ib.length_dw = 5;
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@ -704,7 +707,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -2345,6 +2345,9 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
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u32 num_heads = 0, lb_size;
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int i;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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for (i = 0; i < rdev->num_crtc; i++) {
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@ -2552,6 +2555,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
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tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
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WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
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WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
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}
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} else {
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tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
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@ -3207,6 +3207,9 @@ void r100_bandwidth_update(struct radeon_device *rdev)
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uint32_t pixel_bytes1 = 0;
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uint32_t pixel_bytes2 = 0;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled) {
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@ -338,17 +338,17 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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struct radeon_ib ib;
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unsigned i;
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unsigned index;
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int r;
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void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
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u32 tmp = 0;
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u64 gpu_addr;
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if (!ptr) {
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DRM_ERROR("invalid vram scratch pointer\n");
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return -EINVAL;
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}
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if (ring->idx == R600_RING_TYPE_DMA_INDEX)
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index = R600_WB_DMA_RING_TEST_OFFSET;
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else
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index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
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tmp = 0xCAFEDEAD;
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writel(tmp, ptr);
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gpu_addr = rdev->wb.gpu_addr + index;
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r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
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if (r) {
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@ -357,8 +357,8 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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}
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ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
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ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
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ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
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ib.ptr[1] = lower_32_bits(gpu_addr);
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ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff;
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ib.ptr[3] = 0xDEADBEEF;
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ib.length_dw = 4;
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@ -374,7 +374,7 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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tmp = readl(ptr);
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tmp = le32_to_cpu(rdev->wb.wb[index/4]);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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@ -879,6 +879,9 @@ void rs600_bandwidth_update(struct radeon_device *rdev)
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u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
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/* FIXME: implement full support */
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled)
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@ -579,6 +579,9 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
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u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
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u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled)
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@ -1277,6 +1277,9 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
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struct drm_display_mode *mode0 = NULL;
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struct drm_display_mode *mode1 = NULL;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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if (rdev->mode_info.crtcs[0]->base.enabled)
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@ -2384,6 +2384,9 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
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u32 num_heads = 0, lb_size;
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int i;
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if (!rdev->mode_info.mode_config_initialized)
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return;
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radeon_update_display_priority(rdev);
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for (i = 0; i < rdev->num_crtc; i++) {
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