x86, asmlinkage: Make several variables used from assembler/linker script visible
Plus one function, load_gs_index(). Signed-off-by: Andi Kleen <ak@linux.intel.com> Link: http://lkml.kernel.org/r/1375740170-7446-10-git-send-email-andi@firstfloor.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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@ -22,7 +22,8 @@
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]
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__visible;
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern spinlock_t pgd_lock;
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@ -412,7 +412,7 @@ union irq_stack_union {
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};
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};
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DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
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DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
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DECLARE_INIT_PER_CPU(irq_stack_union);
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DECLARE_PER_CPU(char *, irq_stack_ptr);
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@ -101,7 +101,7 @@ static inline void native_wbinvd(void)
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asm volatile("wbinvd": : :"memory");
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}
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extern void native_load_gs_index(unsigned);
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extern asmlinkage void native_load_gs_index(unsigned);
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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@ -66,8 +66,8 @@ static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
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* performance at the same time..
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*/
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extern void vide(void);
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__asm__(".align 4\nvide: ret");
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extern __visible void vide(void);
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__asm__(".globl vide\n\t.align 4\nvide: ret");
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static void init_amd_k5(struct cpuinfo_x86 *c)
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{
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@ -1076,7 +1076,7 @@ struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
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(unsigned long) debug_idt_table };
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DEFINE_PER_CPU_FIRST(union irq_stack_union,
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irq_stack_union) __aligned(PAGE_SIZE);
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irq_stack_union) __aligned(PAGE_SIZE) __visible;
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/*
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* The following four percpu variables are hot. Align current_task to
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@ -1093,7 +1093,7 @@ EXPORT_PER_CPU_SYMBOL(kernel_stack);
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DEFINE_PER_CPU(char *, irq_stack_ptr) =
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init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
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DEFINE_PER_CPU(unsigned int, irq_count) = -1;
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DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
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DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
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@ -36,7 +36,7 @@
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* section. Since TSS's are completely CPU-local, we want them
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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*/
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DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
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__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
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#ifdef CONFIG_X86_64
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static DEFINE_PER_CPU(unsigned char, is_idle);
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@ -52,7 +52,7 @@
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asmlinkage extern void ret_from_fork(void);
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DEFINE_PER_CPU(unsigned long, old_rsp);
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asmlinkage DEFINE_PER_CPU(unsigned long, old_rsp);
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/* Prints also some state that isn't saved in the pt_regs */
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void __show_regs(struct pt_regs *regs, int all)
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@ -206,9 +206,9 @@ EXPORT_SYMBOL(boot_cpu_data);
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#if !defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64)
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unsigned long mmu_cr4_features;
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__visible unsigned long mmu_cr4_features;
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#else
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unsigned long mmu_cr4_features = X86_CR4_PAE;
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__visible unsigned long mmu_cr4_features = X86_CR4_PAE;
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#endif
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/* Boot loader ID and version as integers, for the benefit of proc_dointvec */
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@ -728,7 +728,7 @@ static void do_signal(struct pt_regs *regs)
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* notification of userspace execution resumption
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* - triggered by the TIF_WORK_MASK flags
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*/
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void
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__visible void
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do_notify_resume(struct pt_regs *regs, void *unused, __u32 thread_info_flags)
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{
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user_exit();
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@ -68,7 +68,7 @@ EXPORT_SYMBOL(copy_in_user);
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* Since protection fault in copy_from/to_user is not a normal situation,
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* it is not necessary to optimize tail handling.
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*/
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unsigned long
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__visible unsigned long
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copy_user_handle_tail(char *to, char *from, unsigned len, unsigned zerorest)
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{
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char c;
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