[SCSI] pm80xx: Phy settings support for motherboard controller.
Phy profile implementation to support phy settings feature for motherboard controllers. [jejb: checkpatch fixes] Signed-off-by: Anandkumar.Santhanam@pmcs.com Reviewed-by: Jack Wang <jinpu.wang@profitbricks.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
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@ -4831,6 +4831,16 @@ int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
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cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
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cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
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break;
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break;
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}
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}
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case IOP_RDUMP: {
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nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
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nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
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nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
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nvmd_req.resp_addr_hi =
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cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
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nvmd_req.resp_addr_lo =
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cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
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break;
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}
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default:
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default:
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break;
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break;
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}
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}
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@ -667,6 +667,31 @@ static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
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#endif
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#endif
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}
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}
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/*
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* pm8001_get_phy_settings_info : Read phy setting values.
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* @pm8001_ha : our hba.
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*/
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void pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
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{
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#ifdef PM8001_READ_VPD
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/*OPTION ROM FLASH read for the SPC cards */
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DECLARE_COMPLETION_ONSTACK(completion);
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struct pm8001_ioctl_payload payload;
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pm8001_ha->nvmd_completion = &completion;
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/* SAS ADDRESS read from flash / EEPROM */
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payload.minor_function = 6;
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payload.offset = 0;
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payload.length = 4096;
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payload.func_specific = kzalloc(4096, GFP_KERNEL);
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/* Read phy setting values from flash */
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PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
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wait_for_completion(&completion);
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pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
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#endif
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}
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#ifdef PM8001_USE_MSIX
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#ifdef PM8001_USE_MSIX
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/**
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/**
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* pm8001_setup_msix - enable MSI-X interrupt
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* pm8001_setup_msix - enable MSI-X interrupt
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@ -847,6 +872,10 @@ static int pm8001_pci_probe(struct pci_dev *pdev,
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}
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}
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pm8001_init_sas_add(pm8001_ha);
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pm8001_init_sas_add(pm8001_ha);
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/* phy setting support for motherboard controller */
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if (pdev->subsystem_vendor != PCI_VENDOR_ID_ADAPTEC2 &&
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pdev->subsystem_vendor != 0)
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pm8001_get_phy_settings_info(pm8001_ha);
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pm8001_post_sas_ha_init(shost, chip);
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pm8001_post_sas_ha_init(shost, chip);
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rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
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rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
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if (rc)
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if (rc)
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@ -632,7 +632,8 @@ struct pm8001_device *pm8001_find_dev(struct pm8001_hba_info *pm8001_ha,
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int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
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int pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha);
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int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue);
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void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
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u32 length, u8 *buf);
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/* ctl shared API */
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/* ctl shared API */
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extern struct device_attribute *pm8001_host_attrs[];
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extern struct device_attribute *pm8001_host_attrs[];
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@ -3183,9 +3183,27 @@ static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
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static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
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static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
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void *piomb)
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void *piomb)
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{
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{
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PM8001_MSG_DBG(pm8001_ha,
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u8 page_code;
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pm8001_printk(" pm80xx_addition_functionality\n"));
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struct set_phy_profile_resp *pPayload =
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(struct set_phy_profile_resp *)(piomb + 4);
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u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
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u32 status = le32_to_cpu(pPayload->status);
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page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
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if (status) {
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/* status is FAILED */
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("PhyProfile command failed with status "
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"0x%08X \n", status));
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return -1;
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} else {
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if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
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PM8001_FAIL_DBG(pm8001_ha,
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pm8001_printk("Invalid page code 0x%X\n",
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page_code));
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return -1;
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}
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}
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return 0;
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return 0;
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}
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}
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@ -4281,6 +4299,45 @@ pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
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u32 operation, u32 phyid, u32 length, u32 *buf)
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{
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u32 tag , i, j = 0;
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int rc;
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struct set_phy_profile_req payload;
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struct inbound_queue_table *circularQ;
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u32 opc = OPC_INB_SET_PHY_PROFILE;
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memset(&payload, 0, sizeof(payload));
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rc = pm8001_tag_alloc(pm8001_ha, &tag);
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if (rc)
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PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
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circularQ = &pm8001_ha->inbnd_q_tbl[0];
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payload.tag = cpu_to_le32(tag);
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payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
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PM8001_INIT_DBG(pm8001_ha,
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pm8001_printk(" phy profile command for phy %x ,length is %d\n",
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payload.ppc_phyid, length));
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for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
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payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
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j++;
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}
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pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
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}
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void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
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u32 length, u8 *buf)
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{
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u32 page_code, i;
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page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
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for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
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mpi_set_phy_profile_req(pm8001_ha,
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SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
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length = length + PHY_DWORD_LENGTH;
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}
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PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
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}
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const struct pm8001_dispatch pm8001_80xx_dispatch = {
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const struct pm8001_dispatch pm8001_80xx_dispatch = {
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.name = "pmc80xx",
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.name = "pmc80xx",
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.chip_init = pm80xx_chip_init,
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.chip_init = pm80xx_chip_init,
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@ -170,6 +170,10 @@
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#define LINKRATE_60 (0x06 << 8)
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#define LINKRATE_60 (0x06 << 8)
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#define LINKRATE_120 (0x08 << 8)
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#define LINKRATE_120 (0x08 << 8)
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/* phy_profile */
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#define SAS_PHY_ANALOG_SETTINGS_PAGE 0x04
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#define PHY_DWORD_LENGTH 0xC
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/* Thermal related */
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/* Thermal related */
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#define THERMAL_ENABLE 0x1
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#define THERMAL_ENABLE 0x1
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#define THERMAL_LOG_ENABLE 0x1
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#define THERMAL_LOG_ENABLE 0x1
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