crypto: marvell - Remove the old mv_cesa driver
All defconfigs selecting the old driver have been patched to select the new one instead. We can now remove the old driver along with the allhwsupports module parameter in the new driver that was used to check whether the new driver was allowed to take control of the CESA engine or not. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Boris BREZILLON
Herbert Xu
parent
729ec4c57d
commit
27b43fd95b
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@ -199,22 +199,8 @@ config CRYPTO_CRC32_S390
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It is available with IBM z13 or later.
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config CRYPTO_DEV_MV_CESA
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tristate "Marvell's Cryptographic Engine"
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depends on PLAT_ORION
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select CRYPTO_AES
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select CRYPTO_BLKCIPHER
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select CRYPTO_HASH
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select SRAM
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help
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This driver allows you to utilize the Cryptographic Engines and
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Security Accelerator (CESA) which can be found on the Marvell Orion
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and Kirkwood SoCs, such as QNAP's TS-209.
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Currently the driver supports AES in ECB and CBC mode without DMA.
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config CRYPTO_DEV_MARVELL_CESA
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tristate "New Marvell's Cryptographic Engine driver"
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tristate "Marvell's Cryptographic Engine driver"
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depends on PLAT_ORION || ARCH_MVEBU
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select CRYPTO_AES
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select CRYPTO_DES
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@ -223,12 +209,10 @@ config CRYPTO_DEV_MARVELL_CESA
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select SRAM
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help
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This driver allows you to utilize the Cryptographic Engines and
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Security Accelerator (CESA) which can be found on the Armada 370.
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Security Accelerator (CESA) which can be found on MVEBU and ORION
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platforms.
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This driver supports CPU offload through DMA transfers.
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This driver is aimed at replacing the mv_cesa driver. This will only
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happen once it has received proper testing.
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config CRYPTO_DEV_NIAGARA2
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tristate "Niagara2 Stream Processing Unit driver"
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select CRYPTO_DES
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@ -14,7 +14,6 @@ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
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obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
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obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
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obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
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obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
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obj-$(CONFIG_CRYPTO_DEV_MARVELL_CESA) += marvell/
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obj-$(CONFIG_CRYPTO_DEV_MEDIATEK) += mediatek/
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obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
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@ -34,10 +34,6 @@
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/* Limit of the crypto queue before reaching the backlog */
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#define CESA_CRYPTO_DEFAULT_MAX_QLEN 128
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static int allhwsupport = !IS_ENABLED(CONFIG_CRYPTO_DEV_MV_CESA);
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module_param_named(allhwsupport, allhwsupport, int, 0444);
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MODULE_PARM_DESC(allhwsupport, "Enable support for all hardware (even it if overlaps with the mv_cesa driver)");
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struct mv_cesa_dev *cesa_dev;
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struct crypto_async_request *
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@ -457,9 +453,6 @@ static int mv_cesa_probe(struct platform_device *pdev)
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caps = match->data;
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}
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if ((caps == &orion_caps || caps == &kirkwood_caps) && !allhwsupport)
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return -ENOTSUPP;
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cesa = devm_kzalloc(dev, sizeof(*cesa), GFP_KERNEL);
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if (!cesa)
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return -ENOMEM;
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File diff suppressed because it is too large
Load diff
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@ -1,150 +0,0 @@
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#ifndef __MV_CRYPTO_H__
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#define __MV_CRYPTO_H__
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#define DIGEST_INITIAL_VAL_A 0xdd00
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#define DIGEST_INITIAL_VAL_B 0xdd04
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#define DIGEST_INITIAL_VAL_C 0xdd08
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#define DIGEST_INITIAL_VAL_D 0xdd0c
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#define DIGEST_INITIAL_VAL_E 0xdd10
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#define DES_CMD_REG 0xdd58
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#define SEC_ACCEL_CMD 0xde00
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#define SEC_CMD_EN_SEC_ACCL0 (1 << 0)
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#define SEC_CMD_EN_SEC_ACCL1 (1 << 1)
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#define SEC_CMD_DISABLE_SEC (1 << 2)
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#define SEC_ACCEL_DESC_P0 0xde04
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#define SEC_DESC_P0_PTR(x) (x)
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#define SEC_ACCEL_DESC_P1 0xde14
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#define SEC_DESC_P1_PTR(x) (x)
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#define SEC_ACCEL_CFG 0xde08
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#define SEC_CFG_STOP_DIG_ERR (1 << 0)
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#define SEC_CFG_CH0_W_IDMA (1 << 7)
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#define SEC_CFG_CH1_W_IDMA (1 << 8)
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#define SEC_CFG_ACT_CH0_IDMA (1 << 9)
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#define SEC_CFG_ACT_CH1_IDMA (1 << 10)
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#define SEC_ACCEL_STATUS 0xde0c
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#define SEC_ST_ACT_0 (1 << 0)
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#define SEC_ST_ACT_1 (1 << 1)
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/*
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* FPGA_INT_STATUS looks like a FPGA leftover and is documented only in Errata
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* 4.12. It looks like that it was part of an IRQ-controller in FPGA and
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* someone forgot to remove it while switching to the core and moving to
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* SEC_ACCEL_INT_STATUS.
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*/
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#define FPGA_INT_STATUS 0xdd68
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#define SEC_ACCEL_INT_STATUS 0xde20
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#define SEC_INT_AUTH_DONE (1 << 0)
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#define SEC_INT_DES_E_DONE (1 << 1)
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#define SEC_INT_AES_E_DONE (1 << 2)
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#define SEC_INT_AES_D_DONE (1 << 3)
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#define SEC_INT_ENC_DONE (1 << 4)
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#define SEC_INT_ACCEL0_DONE (1 << 5)
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#define SEC_INT_ACCEL1_DONE (1 << 6)
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#define SEC_INT_ACC0_IDMA_DONE (1 << 7)
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#define SEC_INT_ACC1_IDMA_DONE (1 << 8)
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#define SEC_ACCEL_INT_MASK 0xde24
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#define AES_KEY_LEN (8 * 4)
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struct sec_accel_config {
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u32 config;
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#define CFG_OP_MAC_ONLY 0
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#define CFG_OP_CRYPT_ONLY 1
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#define CFG_OP_MAC_CRYPT 2
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#define CFG_OP_CRYPT_MAC 3
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#define CFG_MACM_MD5 (4 << 4)
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#define CFG_MACM_SHA1 (5 << 4)
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#define CFG_MACM_HMAC_MD5 (6 << 4)
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#define CFG_MACM_HMAC_SHA1 (7 << 4)
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#define CFG_ENCM_DES (1 << 8)
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#define CFG_ENCM_3DES (2 << 8)
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#define CFG_ENCM_AES (3 << 8)
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#define CFG_DIR_ENC (0 << 12)
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#define CFG_DIR_DEC (1 << 12)
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#define CFG_ENC_MODE_ECB (0 << 16)
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#define CFG_ENC_MODE_CBC (1 << 16)
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#define CFG_3DES_EEE (0 << 20)
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#define CFG_3DES_EDE (1 << 20)
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#define CFG_AES_LEN_128 (0 << 24)
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#define CFG_AES_LEN_192 (1 << 24)
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#define CFG_AES_LEN_256 (2 << 24)
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#define CFG_NOT_FRAG (0 << 30)
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#define CFG_FIRST_FRAG (1 << 30)
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#define CFG_LAST_FRAG (2 << 30)
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#define CFG_MID_FRAG (3 << 30)
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u32 enc_p;
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#define ENC_P_SRC(x) (x)
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#define ENC_P_DST(x) ((x) << 16)
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u32 enc_len;
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#define ENC_LEN(x) (x)
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u32 enc_key_p;
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#define ENC_KEY_P(x) (x)
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u32 enc_iv;
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#define ENC_IV_POINT(x) ((x) << 0)
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#define ENC_IV_BUF_POINT(x) ((x) << 16)
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u32 mac_src_p;
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#define MAC_SRC_DATA_P(x) (x)
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#define MAC_SRC_TOTAL_LEN(x) ((x) << 16)
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u32 mac_digest;
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#define MAC_DIGEST_P(x) (x)
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#define MAC_FRAG_LEN(x) ((x) << 16)
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u32 mac_iv;
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#define MAC_INNER_IV_P(x) (x)
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#define MAC_OUTER_IV_P(x) ((x) << 16)
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}__attribute__ ((packed));
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/*
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* /-----------\ 0
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* | ACCEL CFG | 4 * 8
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* |-----------| 0x20
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* | CRYPT KEY | 8 * 4
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* |-----------| 0x40
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* | IV IN | 4 * 4
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* |-----------| 0x40 (inplace)
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* | IV BUF | 4 * 4
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* |-----------| 0x80
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* | DATA IN | 16 * x (max ->max_req_size)
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* |-----------| 0x80 (inplace operation)
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* | DATA OUT | 16 * x (max ->max_req_size)
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* \-----------/ SRAM size
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*/
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/* Hashing memory map:
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* /-----------\ 0
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* | ACCEL CFG | 4 * 8
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* |-----------| 0x20
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* | Inner IV | 5 * 4
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* |-----------| 0x34
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* | Outer IV | 5 * 4
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* |-----------| 0x48
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* | Output BUF| 5 * 4
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* |-----------| 0x80
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* | DATA IN | 64 * x (max ->max_req_size)
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* \-----------/ SRAM size
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*/
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#define SRAM_CONFIG 0x00
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#define SRAM_DATA_KEY_P 0x20
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#define SRAM_DATA_IV 0x40
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#define SRAM_DATA_IV_BUF 0x40
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#define SRAM_DATA_IN_START 0x80
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#define SRAM_DATA_OUT_START 0x80
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#define SRAM_HMAC_IV_IN 0x20
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#define SRAM_HMAC_IV_OUT 0x34
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#define SRAM_DIGEST_BUF 0x48
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#define SRAM_CFG_SPACE 0x80
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#endif
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