[CPUFREQ] EXYNOS4210: cpufreq code is changed for stable working
This patch is modify code for stable working 1. Remove unused register access code 2. Change sequence for frequency changing Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Jongpill Lee <boyko.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Dave Jones <davej@redhat.com>
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@ -36,6 +36,10 @@ static struct regulator *arm_regulator;
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static struct cpufreq_freqs freqs;
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struct cpufreq_clkdiv {
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unsigned int clkdiv;
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};
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static unsigned int locking_frequency;
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static bool frequency_locked;
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static DEFINE_MUTEX(cpufreq_lock);
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@ -44,6 +48,8 @@ enum cpufreq_level_index {
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L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
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};
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static struct cpufreq_clkdiv exynos4_clkdiv_table[CPUFREQ_LEVEL_END];
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static struct cpufreq_frequency_table exynos4_freq_table[] = {
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{L0, 1200*1000},
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{L1, 1000*1000},
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@ -155,20 +161,7 @@ static void exynos4_set_clkdiv(unsigned int div_index)
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/* Change Divider - CPU0 */
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tmp = __raw_readl(S5P_CLKDIV_CPU);
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tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
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S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
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S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
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S5P_CLKDIV_CPU0_APLL_MASK);
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tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
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(clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
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(clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
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(clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
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(clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
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(clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
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(clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
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tmp = exynos4_clkdiv_table[div_index].clkdiv;
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__raw_writel(tmp, S5P_CLKDIV_CPU);
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@ -233,14 +226,12 @@ static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index
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unsigned int tmp;
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if (old_index > new_index) {
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/* The frequency changing to L0 needs to change apll */
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if (freqs.new == exynos4_freq_table[L0].frequency) {
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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} else {
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/*
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* L1/L3, L2/L4 Level change require
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* to only change s divider value
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*/
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if (((old_index == L3) && (new_index == L1)) ||
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((old_index == L4) && (new_index == L2))) {
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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@ -249,24 +240,32 @@ static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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}
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}
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else if (old_index < new_index) {
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/* The frequency changing from L0 needs to change apll */
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if (freqs.old == exynos4_freq_table[L0].frequency) {
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/* 1. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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/* 2. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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}
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} else if (old_index < new_index) {
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/*
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* L1/L3, L2/L4 Level change require
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* to only change s divider value
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*/
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if (((old_index == L1) && (new_index == L3)) ||
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((old_index == L2) && (new_index == L4))) {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(S5P_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, S5P_APLL_CON0);
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/* 2. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the apll m,p,s value */
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exynos4_set_apll(new_index);
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/* 2. Change the system clock divider values */
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exynos4_set_clkdiv(new_index);
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}
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@ -320,14 +319,14 @@ static int exynos4_target(struct cpufreq_policy *policy,
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/* Clock Configuration Procedure */
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exynos4_set_frequency(old_index, index);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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/* control regulator */
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if (freqs.new < freqs.old) {
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/* Voltage down */
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regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
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}
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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out:
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mutex_unlock(&cpufreq_lock);
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return err;
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@ -438,7 +437,12 @@ static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
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* Each cpu is bound to the same speed.
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* So the affected cpu is all of the cpus.
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*/
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cpumask_setall(policy->cpus);
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if (!cpu_online(1)) {
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cpumask_copy(policy->related_cpus, cpu_possible_mask);
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cpumask_copy(policy->cpus, cpu_online_mask);
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} else {
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cpumask_setall(policy->cpus);
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}
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ret = cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
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if (ret)
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@ -477,6 +481,9 @@ static struct cpufreq_driver exynos4_driver = {
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static int __init exynos4_cpufreq_init(void)
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{
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int i;
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unsigned int tmp;
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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@ -503,6 +510,28 @@ static int __init exynos4_cpufreq_init(void)
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register_pm_notifier(&exynos4_cpufreq_nb);
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tmp = __raw_readl(S5P_CLKDIV_CPU);
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for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
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tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK |
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S5P_CLKDIV_CPU0_COREM0_MASK |
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S5P_CLKDIV_CPU0_COREM1_MASK |
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S5P_CLKDIV_CPU0_PERIPH_MASK |
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S5P_CLKDIV_CPU0_ATB_MASK |
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S5P_CLKDIV_CPU0_PCLKDBG_MASK |
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S5P_CLKDIV_CPU0_APLL_MASK);
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tmp |= ((clkdiv_cpu0[i][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
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(clkdiv_cpu0[i][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
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(clkdiv_cpu0[i][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
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(clkdiv_cpu0[i][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
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(clkdiv_cpu0[i][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
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(clkdiv_cpu0[i][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
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(clkdiv_cpu0[i][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
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exynos4_clkdiv_table[i].clkdiv = tmp;
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}
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return cpufreq_register_driver(&exynos4_driver);
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out:
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