[SPARC64]: Removal of trivial pci_controller_info uses.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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6c108f1299
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28113a9941
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@ -921,10 +921,8 @@ static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struc
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enum pci_mmap_state mmap_state)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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struct pci_controller_info *p;
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unsigned long space_size, user_offset, user_size;
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p = pbm->parent;
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if (mmap_state == pci_mmap_io) {
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space_size = (pbm->io_space.end -
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pbm->io_space.start) + 1;
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@ -98,13 +98,8 @@ static int psycho_out_of_range(struct pci_pbm_info *pbm,
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unsigned char bus,
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unsigned char devfn)
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{
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return ((pbm->parent == 0) ||
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((pbm == &pbm->parent->pbm_B) &&
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(bus == pbm->pci_first_busno) &&
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PCI_SLOT(devfn) > 8) ||
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((pbm == &pbm->parent->pbm_A) &&
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(bus == pbm->pci_first_busno) &&
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PCI_SLOT(devfn) > 8));
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return ((bus == pbm->pci_first_busno) &&
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PCI_SLOT(devfn) > 8);
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}
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/* PSYCHO PCI configuration space accessors. */
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@ -918,33 +913,33 @@ static void psycho_scan_bus(struct pci_pbm_info *pbm)
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psycho_register_error_handlers(pbm);
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}
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static void psycho_iommu_init(struct pci_controller_info *p)
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static void psycho_iommu_init(struct pci_pbm_info *pbm)
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{
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struct iommu *iommu = p->pbm_A.iommu;
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struct iommu *iommu = pbm->iommu;
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unsigned long i;
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u64 control;
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/* Register addresses. */
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iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
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iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
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iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
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iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL;
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iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE;
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iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH;
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/* PSYCHO's IOMMU lacks ctx flushing. */
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iommu->iommu_ctxflush = 0;
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/* We use the main control register of PSYCHO as the write
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* completion register.
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*/
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iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
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iommu->write_complete_reg = pbm->controller_regs + PSYCHO_CONTROL;
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/*
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* Invalidate TLB Entries.
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*/
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control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
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control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
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control |= PSYCHO_IOMMU_CTRL_DENAB;
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psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
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psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
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for(i = 0; i < 16; i++) {
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psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
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psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
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psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
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psycho_write(pbm->controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
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}
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/* Leave diag mode enabled for full-flushing done
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@ -952,17 +947,17 @@ static void psycho_iommu_init(struct pci_controller_info *p)
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*/
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pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
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psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
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psycho_write(pbm->controller_regs + PSYCHO_IOMMU_TSBBASE,
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__pa(iommu->page_table));
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control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
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control = psycho_read(pbm->controller_regs + PSYCHO_IOMMU_CONTROL);
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control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
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control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
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psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
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psycho_write(pbm->controller_regs + PSYCHO_IOMMU_CONTROL, control);
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/* If necessary, hook us up for starfire IRQ translations. */
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if (this_is_starfire)
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starfire_hookup(p->pbm_A.portid);
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starfire_hookup(pbm->portid);
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}
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#define PSYCHO_IRQ_RETRY 0x1a00UL
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@ -977,36 +972,35 @@ static void psycho_iommu_init(struct pci_controller_info *p)
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#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
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#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
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static void psycho_controller_hwinit(struct pci_controller_info *p)
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static void psycho_controller_hwinit(struct pci_pbm_info *pbm)
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{
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u64 tmp;
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psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
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psycho_write(pbm->controller_regs + PSYCHO_IRQ_RETRY, 5);
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/* Enable arbiter for all PCI slots. */
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tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
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tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_CTRL);
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tmp |= PSYCHO_PCICTRL_AEN;
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psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
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psycho_write(pbm->controller_regs + PSYCHO_PCIA_CTRL, tmp);
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tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
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tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_CTRL);
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tmp |= PSYCHO_PCICTRL_AEN;
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psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
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psycho_write(pbm->controller_regs + PSYCHO_PCIB_CTRL, tmp);
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/* Disable DMA write / PIO read synchronization on
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* both PCI bus segments.
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* [ U2P Erratum 1243770, STP2223BGA data sheet ]
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*/
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tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
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tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIA_DIAG);
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tmp |= PSYCHO_PCIDIAG_DDWSYNC;
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psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
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psycho_write(pbm->controller_regs + PSYCHO_PCIA_DIAG, tmp);
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tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
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tmp = psycho_read(pbm->controller_regs + PSYCHO_PCIB_DIAG);
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tmp |= PSYCHO_PCIDIAG_DDWSYNC;
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psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
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psycho_write(pbm->controller_regs + PSYCHO_PCIB_DIAG, tmp);
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}
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static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
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struct pci_pbm_info *pbm,
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static void psycho_pbm_strbuf_init(struct pci_pbm_info *pbm,
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int is_pbm_a)
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{
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unsigned long base = pbm->controller_regs;
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@ -1105,7 +1099,7 @@ static void psycho_pbm_init(struct pci_controller_info *p,
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pci_get_pbm_props(pbm);
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psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
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psycho_pbm_strbuf_init(pbm, is_pbm_a);
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}
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#define PSYCHO_CONFIGSPACE 0x001000000UL
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@ -1165,9 +1159,9 @@ void psycho_init(struct device_node *dp, char *model_name)
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*/
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pci_memspace_mask = 0x7fffffffUL;
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psycho_controller_hwinit(p);
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psycho_controller_hwinit(&p->pbm_A);
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psycho_iommu_init(p);
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psycho_iommu_init(&p->pbm_A);
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is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
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psycho_pbm_init(p, dp, is_pbm_a);
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@ -942,30 +942,30 @@ static void sabre_scan_bus(struct pci_pbm_info *pbm)
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sabre_register_error_handlers(pbm);
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}
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static void sabre_iommu_init(struct pci_controller_info *p,
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static void sabre_iommu_init(struct pci_pbm_info *pbm,
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int tsbsize, unsigned long dvma_offset,
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u32 dma_mask)
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{
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struct iommu *iommu = p->pbm_A.iommu;
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struct iommu *iommu = pbm->iommu;
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unsigned long i;
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u64 control;
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/* Register addresses. */
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iommu->iommu_control = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
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iommu->iommu_tsbbase = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
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iommu->iommu_flush = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
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iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
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iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL;
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iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE;
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iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH;
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iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;
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/* Sabre's IOMMU lacks ctx flushing. */
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iommu->iommu_ctxflush = 0;
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/* Invalidate TLB Entries. */
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control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
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control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
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control |= SABRE_IOMMUCTRL_DENAB;
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sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
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sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
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for(i = 0; i < 16; i++) {
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sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
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sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
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sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
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sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
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}
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/* Leave diag mode enabled for full-flushing done
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@ -973,10 +973,10 @@ static void sabre_iommu_init(struct pci_controller_info *p,
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*/
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pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
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sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
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sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,
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__pa(iommu->page_table));
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control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
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control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
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control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
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control |= SABRE_IOMMUCTRL_ENAB;
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switch(tsbsize) {
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@ -991,14 +991,11 @@ static void sabre_iommu_init(struct pci_controller_info *p,
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prom_halt();
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break;
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}
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sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
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sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
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}
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static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp)
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static void sabre_pbm_init(struct pci_controller_info *p, struct pci_pbm_info *pbm, struct device_node *dp)
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{
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struct pci_pbm_info *pbm;
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pbm = &p->pbm_A;
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pbm->name = dp->full_name;
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printk("%s: SABRE PCI Bus Module\n", pbm->name);
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@ -1019,6 +1016,7 @@ void sabre_init(struct device_node *dp, char *model_name)
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{
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const struct linux_prom64_registers *pr_regs;
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struct pci_controller_info *p;
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struct pci_pbm_info *pbm;
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struct iommu *iommu;
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int tsbsize;
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const u32 *vdma;
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@ -1055,14 +1053,15 @@ void sabre_init(struct device_node *dp, char *model_name)
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prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
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prom_halt();
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}
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p->pbm_A.iommu = iommu;
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pbm = &p->pbm_A;
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pbm->iommu = iommu;
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upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
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p->pbm_A.next = pci_pbm_root;
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pci_pbm_root = &p->pbm_A;
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pbm->next = pci_pbm_root;
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pci_pbm_root = pbm;
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p->pbm_A.portid = upa_portid;
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pbm->portid = upa_portid;
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/*
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* Map in SABRE register set and report the presence of this SABRE.
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@ -1073,26 +1072,26 @@ void sabre_init(struct device_node *dp, char *model_name)
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/*
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* First REG in property is base of entire SABRE register space.
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*/
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p->pbm_A.controller_regs = pr_regs[0].phys_addr;
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pbm->controller_regs = pr_regs[0].phys_addr;
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/* Clear interrupts */
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/* PCI first */
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for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
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sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
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sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
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/* Then OBIO */
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for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
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sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
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sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
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/* Error interrupts are enabled later after the bus scan. */
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sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
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sabre_write(pbm->controller_regs + SABRE_PCICTRL,
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(SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
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SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
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/* Now map in PCI config space for entire SABRE. */
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p->pbm_A.config_space =
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(p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
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pbm->config_space =
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(pbm->controller_regs + SABRE_CONFIGSPACE);
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vdma = of_get_property(dp, "virtual-dma", NULL);
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@ -1116,10 +1115,10 @@ void sabre_init(struct device_node *dp, char *model_name)
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prom_halt();
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}
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sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
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sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask);
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/*
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* Look for APB underneath.
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*/
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sabre_pbm_init(p, dp);
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sabre_pbm_init(p, pbm, dp);
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}
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