x86: move GART TLB flushing options to generic code
The GART currently implements the iommu=[no]fullflush command line parameters which influence its IO/TLB flushing strategy. This patch makes these parameters generic so that they can be used by the AMD IOMMU too. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -893,6 +893,10 @@ and is between 256 and 4096 characters. It is defined in the file
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nomerge
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forcesac
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soft
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fullflush
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Flush IO/TLB at every deallocation
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nofullflush
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Flush IO/TLB only when addresses are reused (default)
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intel_iommu= [DMAR] Intel IOMMU driver (DMAR) option
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@ -233,8 +233,6 @@ IOMMU (input/output memory management unit)
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iommu options only relevant to the AMD GART hardware IOMMU:
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<size> Set the size of the remapping area in bytes.
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allowed Overwrite iommu off workarounds for specific chipsets.
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fullflush Flush IOMMU on each allocation (default).
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nofullflush Don't use IOMMU fullflush.
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leak Turn on simple iommu leak tracing (only when
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CONFIG_IOMMU_LEAK is on). Default number of leak pages
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is 20.
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@ -16,6 +16,15 @@ EXPORT_SYMBOL(dma_ops);
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static int iommu_sac_force __read_mostly;
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/*
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* If this is disabled the IOMMU will use an optimized flushing strategy
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* of only flushing when an mapping is reused. With it true the GART is
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* flushed for every mapping. Problem is that doing the lazy flush seems
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* to trigger bugs with some popular PCI cards, in particular 3ware (but
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* has been also also seen with Qlogic at least).
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*/
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int iommu_fullflush;
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#ifdef CONFIG_IOMMU_DEBUG
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int panic_on_overflow __read_mostly = 1;
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int force_iommu __read_mostly = 1;
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@ -171,6 +180,10 @@ static __init int iommu_setup(char *p)
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}
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if (!strncmp(p, "nomerge", 7))
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iommu_merge = 0;
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if (!strncmp(p, "fullflush", 8))
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iommu_fullflush = 1;
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if (!strncmp(p, "nofullflush", 11))
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iommu_fullflush = 0;
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if (!strncmp(p, "forcesac", 8))
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iommu_sac_force = 1;
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if (!strncmp(p, "allowdac", 8))
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@ -45,15 +45,6 @@ static unsigned long iommu_pages; /* .. and in pages */
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static u32 *iommu_gatt_base; /* Remapping table */
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/*
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* If this is disabled the IOMMU will use an optimized flushing strategy
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* of only flushing when an mapping is reused. With it true the GART is
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* flushed for every mapping. Problem is that doing the lazy flush seems
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* to trigger bugs with some popular PCI cards, in particular 3ware (but
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* has been also also seen with Qlogic at least).
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*/
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int iommu_fullflush = 1;
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/* Allocation bitmap for the remapping area: */
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static DEFINE_SPINLOCK(iommu_bitmap_lock);
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/* Guarded by iommu_bitmap_lock: */
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@ -901,10 +892,6 @@ void __init gart_parse_options(char *p)
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#endif
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if (isdigit(*p) && get_option(&p, &arg))
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iommu_size = arg;
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if (!strncmp(p, "fullflush", 8))
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iommu_fullflush = 1;
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if (!strncmp(p, "nofullflush", 11))
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iommu_fullflush = 0;
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if (!strncmp(p, "noagp", 5))
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no_agp = 1;
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if (!strncmp(p, "noaperture", 10))
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@ -7,6 +7,7 @@ extern struct dma_mapping_ops nommu_dma_ops;
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extern int force_iommu, no_iommu;
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extern int iommu_detected;
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extern int dmar_disabled;
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extern int iommu_fullflush;
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extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);
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