Linux 3.3-rc2
.. several days delayed. No reason, I just didn't think of it. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.18 (GNU/Linux) iQEcBAABAgAGBQJPKF4KAAoJEHm+PkMAQRiGw/YH+wXg2DpZUuHeBK52zMGlJBPc DzX11/Uan3Y07gM0JbDzuVxwjX4vdxR2bV6r1qsLP8JEUnE8jyFC32DBGi5WAht7 F4KU/Uov2Ds5/wzvY4Iuo01C+JftQHXuy/Sbhck1d0LI0yjLejRaw+zuJv0x2/eS 7YqV+KTGE1lDuJs/Gyq1Vqr1g9831AuS1tv/g3gaqBuN6TcPBFCocaVxzwrUc+y6 94h26XbbOhQRIz38oqUkiqAGnvYS61ocyBcEiRHf0dXkNSDIINqlgukvd7YTXouA jj/w/DWpMRcQuYAgqkrurr9+yWC9hVQcsvvQ5sAQnIPcxoR868sg1pO8Oheq+1g= =kUzV -----END PGP SIGNATURE----- Merge tag 'v3.3-rc2' into perf/core Linux 3.3-rc2 Pick up the latest fixes. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
commit
290436c9c6
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@ -233,6 +233,10 @@ certainly invest a bit more effort into libata core layer).
|
|||
6. List of managed interfaces
|
||||
-----------------------------
|
||||
|
||||
MEM
|
||||
devm_kzalloc()
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||||
devm_kfree()
|
||||
|
||||
IO region
|
||||
devm_request_region()
|
||||
devm_request_mem_region()
|
||||
|
|
|
@ -510,3 +510,17 @@ Why: The pci_scan_bus_parented() interface creates a new root bus. The
|
|||
convert to using pci_scan_root_bus() so they can supply a list of
|
||||
bus resources when the bus is created.
|
||||
Who: Bjorn Helgaas <bhelgaas@google.com>
|
||||
|
||||
----------------------------
|
||||
|
||||
What: The CAP9 SoC family will be removed
|
||||
When: 3.4
|
||||
Files: arch/arm/mach-at91/at91cap9.c
|
||||
arch/arm/mach-at91/at91cap9_devices.c
|
||||
arch/arm/mach-at91/include/mach/at91cap9.h
|
||||
arch/arm/mach-at91/include/mach/at91cap9_matrix.h
|
||||
arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
|
||||
arch/arm/mach-at91/board-cap9adk.c
|
||||
Why: The code is not actively maintained and platforms are now hard to find.
|
||||
Who: Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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|
|
|
@ -857,42 +857,41 @@ case), we define a mapping like this:
|
|||
|
||||
...
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{
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.name "2bit"
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.name = "2bit"
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.ctrl_dev_name = "pinctrl-foo",
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.function = "mmc0",
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||||
.group = "mmc0_1_grp",
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||||
.dev_name = "foo-mmc.0",
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||||
},
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||||
{
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.name "4bit"
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.name = "4bit"
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||||
.ctrl_dev_name = "pinctrl-foo",
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.function = "mmc0",
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.group = "mmc0_1_grp",
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.dev_name = "foo-mmc.0",
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||||
},
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{
|
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.name "4bit"
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.name = "4bit"
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.ctrl_dev_name = "pinctrl-foo",
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.function = "mmc0",
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.group = "mmc0_2_grp",
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.dev_name = "foo-mmc.0",
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},
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{
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.name "8bit"
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.name = "8bit"
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.ctrl_dev_name = "pinctrl-foo",
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.function = "mmc0",
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.group = "mmc0_1_grp",
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.dev_name = "foo-mmc.0",
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},
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{
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.name "8bit"
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.name = "8bit"
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.ctrl_dev_name = "pinctrl-foo",
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.function = "mmc0",
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||||
.group = "mmc0_2_grp",
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||||
.dev_name = "foo-mmc.0",
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||||
},
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{
|
||||
.name "8bit"
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.name = "8bit"
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||||
.ctrl_dev_name = "pinctrl-foo",
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||||
.function = "mmc0",
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||||
.group = "mmc0_3_grp",
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||||
|
@ -995,7 +994,7 @@ This is enabled by simply setting the .hog_on_boot field in the map to true,
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|||
like this:
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{
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.name "POWERMAP"
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.name = "POWERMAP"
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||||
.ctrl_dev_name = "pinctrl-foo",
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||||
.function = "power_func",
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||||
.hog_on_boot = true,
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||||
|
@ -1025,7 +1024,7 @@ it, disables and releases it, and muxes it in on the pins defined by group B:
|
|||
|
||||
foo_switch()
|
||||
{
|
||||
struct pinmux pmx;
|
||||
struct pinmux *pmx;
|
||||
|
||||
/* Enable on position A */
|
||||
pmx = pinmux_get(&device, "spi0-pos-A");
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|
|
|
@ -25,7 +25,8 @@ Procedure for submitting patches to the -stable tree:
|
|||
|
||||
- Send the patch, after verifying that it follows the above rules, to
|
||||
stable@vger.kernel.org. You must note the upstream commit ID in the
|
||||
changelog of your submission.
|
||||
changelog of your submission, as well as the kernel version you wish
|
||||
it to be applied to.
|
||||
- To have the patch automatically included in the stable tree, add the tag
|
||||
Cc: stable@vger.kernel.org
|
||||
in the sign-off area. Once the patch is merged it will be applied to
|
||||
|
|
|
@ -4,8 +4,6 @@ Virtualization support in the Linux kernel.
|
|||
- this file.
|
||||
kvm/
|
||||
- Kernel Virtual Machine. See also http://linux-kvm.org
|
||||
lguest/
|
||||
- Extremely simple hypervisor for experimental/educational use.
|
||||
uml/
|
||||
- User Mode Linux, builds/runs Linux kernel as a userspace program.
|
||||
virtio.txt
|
||||
|
|
14
MAINTAINERS
14
MAINTAINERS
|
@ -2350,6 +2350,9 @@ F: include/drm/i915*
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|||
|
||||
DRM DRIVERS FOR EXYNOS
|
||||
M: Inki Dae <inki.dae@samsung.com>
|
||||
M: Joonyoung Shim <jy0922.shim@samsung.com>
|
||||
M: Seung-Woo Kim <sw0312.kim@samsung.com>
|
||||
M: Kyungmin Park <kyungmin.park@samsung.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Supported
|
||||
F: drivers/gpu/drm/exynos
|
||||
|
@ -4137,6 +4140,7 @@ F: fs/partitions/ldm.*
|
|||
|
||||
LogFS
|
||||
M: Joern Engel <joern@logfs.org>
|
||||
M: Prasad Joshi <prasadjoshi.linux@gmail.com>
|
||||
L: logfs@logfs.org
|
||||
W: logfs.org
|
||||
S: Maintained
|
||||
|
@ -4278,13 +4282,6 @@ S: Orphan
|
|||
F: drivers/video/matrox/matroxfb_*
|
||||
F: include/linux/matroxfb.h
|
||||
|
||||
MAX1668 TEMPERATURE SENSOR DRIVER
|
||||
M: "David George" <david.george@ska.ac.za>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
S: Maintained
|
||||
F: Documentation/hwmon/max1668
|
||||
F: drivers/hwmon/max1668.c
|
||||
|
||||
MAX6650 HARDWARE MONITOR AND FAN CONTROLLER DRIVER
|
||||
M: "Hans J. Koch" <hjk@hansjkoch.de>
|
||||
L: lm-sensors@lm-sensors.org
|
||||
|
@ -6675,7 +6672,7 @@ TTY LAYER
|
|||
M: Greg Kroah-Hartman <gregkh@suse.de>
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
|
||||
F: drivers/tty/*
|
||||
F: drivers/tty/
|
||||
F: drivers/tty/serial/serial_core.c
|
||||
F: include/linux/serial_core.h
|
||||
F: include/linux/serial.h
|
||||
|
@ -7368,6 +7365,7 @@ S: Supported
|
|||
F: Documentation/hwmon/wm83??
|
||||
F: arch/arm/mach-s3c64xx/mach-crag6410*
|
||||
F: drivers/leds/leds-wm83*.c
|
||||
F: drivers/hwmon/wm83??-hwmon.c
|
||||
F: drivers/input/misc/wm831x-on.c
|
||||
F: drivers/input/touchscreen/wm831x-ts.c
|
||||
F: drivers/input/touchscreen/wm97*.c
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 3
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc2
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -754,7 +754,7 @@ config ARCH_SA1100
|
|||
select ARCH_HAS_CPUFREQ
|
||||
select CPU_FREQ
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select CLKDEV_LOOKUP
|
||||
select HAVE_CLK
|
||||
select HAVE_SCHED_CLOCK
|
||||
select TICK_ONESHOT
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
@ -825,7 +825,6 @@ config ARCH_S5PC100
|
|||
select HAVE_CLK
|
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select CLKDEV_LOOKUP
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select CPU_V7
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select ARM_L1_CACHE_SHIFT_6
|
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select ARCH_USES_GETTIMEOFFSET
|
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select HAVE_S3C2410_I2C if I2C
|
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select HAVE_S3C_RTC if RTC_CLASS
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|
@ -842,7 +841,6 @@ config ARCH_S5PV210
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|||
select HAVE_CLK
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||||
select CLKDEV_LOOKUP
|
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select CLKSRC_MMIO
|
||||
select ARM_L1_CACHE_SHIFT_6
|
||||
select ARCH_HAS_CPUFREQ
|
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select GENERIC_CLOCKEVENTS
|
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select HAVE_SCHED_CLOCK
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|
|
|
@ -41,6 +41,7 @@
|
|||
|
||||
#include <asm/irq.h>
|
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#include <asm/exception.h>
|
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#include <asm/smp_plat.h>
|
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#include <asm/mach/irq.h>
|
||||
#include <asm/hardware/gic.h>
|
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|
||||
|
@ -352,11 +353,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
|
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unsigned int gic_irqs = gic->gic_irqs;
|
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struct irq_domain *domain = &gic->domain;
|
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void __iomem *base = gic_data_dist_base(gic);
|
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u32 cpu = 0;
|
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|
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(smp_processor_id());
|
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#endif
|
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u32 cpu = cpu_logical_map(smp_processor_id());
|
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|
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cpumask = 1 << cpu;
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cpumask |= cpumask << 8;
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|
|
|
@ -237,7 +237,7 @@
|
|||
*/
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
|
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9999:
|
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.if \inc == 1
|
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\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
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|
@ -277,7 +277,7 @@
|
|||
|
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#else /* !CONFIG_THUMB2_KERNEL */
|
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|
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
|
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
|
||||
.rept \rept
|
||||
9999:
|
||||
.if \inc == 1
|
||||
|
|
|
@ -83,9 +83,9 @@
|
|||
* instructions (inline assembly)
|
||||
*/
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
#define T(instr) #instr "t"
|
||||
#define TUSER(instr) #instr "t"
|
||||
#else
|
||||
#define T(instr) #instr
|
||||
#define TUSER(instr) #instr
|
||||
#endif
|
||||
|
||||
#else /* __ASSEMBLY__ */
|
||||
|
@ -95,9 +95,9 @@
|
|||
* instructions
|
||||
*/
|
||||
#ifdef CONFIG_CPU_USE_DOMAINS
|
||||
#define T(instr) instr ## t
|
||||
#define TUSER(instr) instr ## t
|
||||
#else
|
||||
#define T(instr) instr
|
||||
#define TUSER(instr) instr
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
|
@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
|
||||
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(ldr) " %1, [%3]\n" \
|
||||
"1: " TUSER(ldr) " %1, [%3]\n" \
|
||||
" " insn "\n" \
|
||||
"2: " T(str) " %0, [%3]\n" \
|
||||
"2: " TUSER(str) " %0, [%3]\n" \
|
||||
" mov %0, #0\n" \
|
||||
__futex_atomic_ex_table("%5") \
|
||||
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
|
||||
|
@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
|
|||
return -EFAULT;
|
||||
|
||||
__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
|
||||
"1: " T(ldr) " %1, [%4]\n"
|
||||
"1: " TUSER(ldr) " %1, [%4]\n"
|
||||
" teq %1, %2\n"
|
||||
" it eq @ explicit IT needed for the 2b label\n"
|
||||
"2: " T(streq) " %3, [%4]\n"
|
||||
"2: " TUSER(streq) " %3, [%4]\n"
|
||||
__futex_atomic_ex_table("%5")
|
||||
: "+r" (ret), "=&r" (val)
|
||||
: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
|
||||
|
|
|
@ -70,12 +70,6 @@ extern void platform_secondary_init(unsigned int cpu);
|
|||
*/
|
||||
extern void platform_smp_prepare_cpus(unsigned int);
|
||||
|
||||
/*
|
||||
* Logical CPU mapping.
|
||||
*/
|
||||
extern int __cpu_logical_map[NR_CPUS];
|
||||
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
|
||||
|
||||
/*
|
||||
* Initial data for bringing up a secondary CPU.
|
||||
*/
|
||||
|
|
|
@ -43,4 +43,10 @@ static inline int cache_ops_need_broadcast(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Logical CPU mapping.
|
||||
*/
|
||||
extern int __cpu_logical_map[];
|
||||
#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
|
||||
|
||||
#endif
|
||||
|
|
|
@ -227,7 +227,7 @@ do { \
|
|||
|
||||
#define __get_user_asm_byte(x,addr,err) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(ldrb) " %1,[%2],#0\n" \
|
||||
"1: " TUSER(ldrb) " %1,[%2],#0\n" \
|
||||
"2:\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
|
@ -263,7 +263,7 @@ do { \
|
|||
|
||||
#define __get_user_asm_word(x,addr,err) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(ldr) " %1,[%2],#0\n" \
|
||||
"1: " TUSER(ldr) " %1,[%2],#0\n" \
|
||||
"2:\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
|
@ -308,7 +308,7 @@ do { \
|
|||
|
||||
#define __put_user_asm_byte(x,__pu_addr,err) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(strb) " %1,[%2],#0\n" \
|
||||
"1: " TUSER(strb) " %1,[%2],#0\n" \
|
||||
"2:\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
|
@ -341,7 +341,7 @@ do { \
|
|||
|
||||
#define __put_user_asm_word(x,__pu_addr,err) \
|
||||
__asm__ __volatile__( \
|
||||
"1: " T(str) " %1,[%2],#0\n" \
|
||||
"1: " TUSER(str) " %1,[%2],#0\n" \
|
||||
"2:\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
|
@ -366,10 +366,10 @@ do { \
|
|||
|
||||
#define __put_user_asm_dword(x,__pu_addr,err) \
|
||||
__asm__ __volatile__( \
|
||||
ARM( "1: " T(str) " " __reg_oper1 ", [%1], #4\n" ) \
|
||||
ARM( "2: " T(str) " " __reg_oper0 ", [%1]\n" ) \
|
||||
THUMB( "1: " T(str) " " __reg_oper1 ", [%1]\n" ) \
|
||||
THUMB( "2: " T(str) " " __reg_oper0 ", [%1, #4]\n" ) \
|
||||
ARM( "1: " TUSER(str) " " __reg_oper1 ", [%1], #4\n" ) \
|
||||
ARM( "2: " TUSER(str) " " __reg_oper0 ", [%1]\n" ) \
|
||||
THUMB( "1: " TUSER(str) " " __reg_oper1 ", [%1]\n" ) \
|
||||
THUMB( "2: " TUSER(str) " " __reg_oper0 ", [%1, #4]\n" ) \
|
||||
"3:\n" \
|
||||
" .pushsection .fixup,\"ax\"\n" \
|
||||
" .align 2\n" \
|
||||
|
|
|
@ -149,6 +149,11 @@ ENDPROC(ret_from_fork)
|
|||
#endif
|
||||
#endif
|
||||
|
||||
.macro mcount_adjust_addr rd, rn
|
||||
bic \rd, \rn, #1 @ clear the Thumb bit if present
|
||||
sub \rd, \rd, #MCOUNT_INSN_SIZE
|
||||
.endm
|
||||
|
||||
.macro __mcount suffix
|
||||
mcount_enter
|
||||
ldr r0, =ftrace_trace_function
|
||||
|
@ -173,8 +178,7 @@ ENDPROC(ret_from_fork)
|
|||
mcount_exit
|
||||
|
||||
1: mcount_get_lr r1 @ lr of instrumented func
|
||||
mov r0, lr @ instrumented function
|
||||
sub r0, r0, #MCOUNT_INSN_SIZE
|
||||
mcount_adjust_addr r0, lr @ instrumented function
|
||||
adr lr, BSYM(2f)
|
||||
mov pc, r2
|
||||
2: mcount_exit
|
||||
|
@ -184,8 +188,7 @@ ENDPROC(ret_from_fork)
|
|||
mcount_enter
|
||||
|
||||
mcount_get_lr r1 @ lr of instrumented func
|
||||
mov r0, lr @ instrumented function
|
||||
sub r0, r0, #MCOUNT_INSN_SIZE
|
||||
mcount_adjust_addr r0, lr @ instrumented function
|
||||
|
||||
.globl ftrace_call\suffix
|
||||
ftrace_call\suffix:
|
||||
|
@ -205,11 +208,11 @@ ftrace_graph_call\suffix:
|
|||
#ifdef CONFIG_DYNAMIC_FTRACE
|
||||
@ called from __ftrace_caller, saved in mcount_enter
|
||||
ldr r1, [sp, #16] @ instrumented routine (func)
|
||||
mcount_adjust_addr r1, r1
|
||||
#else
|
||||
@ called from __mcount, untouched in lr
|
||||
mov r1, lr @ instrumented routine (func)
|
||||
mcount_adjust_addr r1, lr @ instrumented routine (func)
|
||||
#endif
|
||||
sub r1, r1, #MCOUNT_INSN_SIZE
|
||||
mov r2, fp @ frame pointer
|
||||
bl prepare_ftrace_return
|
||||
mcount_exit
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/kexec.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/crash_dump.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
@ -160,7 +159,7 @@ static struct resource mem_res[] = {
|
|||
.flags = IORESOURCE_MEM
|
||||
},
|
||||
{
|
||||
.name = "Kernel text",
|
||||
.name = "Kernel code",
|
||||
.start = 0,
|
||||
.end = 0,
|
||||
.flags = IORESOURCE_MEM
|
||||
|
@ -427,6 +426,20 @@ void cpu_init(void)
|
|||
: "r14");
|
||||
}
|
||||
|
||||
int __cpu_logical_map[NR_CPUS];
|
||||
|
||||
void __init smp_setup_processor_id(void)
|
||||
{
|
||||
int i;
|
||||
u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
|
||||
|
||||
cpu_logical_map(0) = cpu;
|
||||
for (i = 1; i < NR_CPUS; ++i)
|
||||
cpu_logical_map(i) = i == cpu ? 0 : i;
|
||||
|
||||
printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
|
||||
}
|
||||
|
||||
static void __init setup_processor(void)
|
||||
{
|
||||
struct proc_info_list *list;
|
||||
|
|
|
@ -233,20 +233,6 @@ void __ref cpu_die(void)
|
|||
}
|
||||
#endif /* CONFIG_HOTPLUG_CPU */
|
||||
|
||||
int __cpu_logical_map[NR_CPUS];
|
||||
|
||||
void __init smp_setup_processor_id(void)
|
||||
{
|
||||
int i;
|
||||
u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
|
||||
|
||||
cpu_logical_map(0) = cpu;
|
||||
for (i = 1; i < NR_CPUS; ++i)
|
||||
cpu_logical_map(i) = i == cpu ? 0 : i;
|
||||
|
||||
printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
|
||||
}
|
||||
|
||||
/*
|
||||
* Called by both boot and secondaries to move global data into
|
||||
* per-processor storage.
|
||||
|
@ -443,9 +429,7 @@ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
|
|||
static void ipi_timer(void)
|
||||
{
|
||||
struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
|
||||
irq_enter();
|
||||
evt->event_handler(evt);
|
||||
irq_exit();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
|
||||
|
@ -548,7 +532,9 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
|
|||
|
||||
switch (ipinr) {
|
||||
case IPI_TIMER:
|
||||
irq_enter();
|
||||
ipi_timer();
|
||||
irq_exit();
|
||||
break;
|
||||
|
||||
case IPI_RESCHEDULE:
|
||||
|
@ -556,15 +542,21 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
|
|||
break;
|
||||
|
||||
case IPI_CALL_FUNC:
|
||||
irq_enter();
|
||||
generic_smp_call_function_interrupt();
|
||||
irq_exit();
|
||||
break;
|
||||
|
||||
case IPI_CALL_FUNC_SINGLE:
|
||||
irq_enter();
|
||||
generic_smp_call_function_single_interrupt();
|
||||
irq_exit();
|
||||
break;
|
||||
|
||||
case IPI_CPU_STOP:
|
||||
irq_enter();
|
||||
ipi_cpu_stop(cpu);
|
||||
irq_exit();
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
|
|||
else
|
||||
twd_calibrate_rate();
|
||||
|
||||
__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
|
||||
|
||||
clk->name = "local_timer";
|
||||
clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
|
||||
CLOCK_EVT_FEAT_C3STOP;
|
||||
|
|
|
@ -4,6 +4,7 @@
|
|||
*/
|
||||
|
||||
#include <asm-generic/vmlinux.lds.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/memory.h>
|
||||
#include <asm/page.h>
|
||||
|
@ -181,7 +182,7 @@ SECTIONS
|
|||
}
|
||||
#endif
|
||||
|
||||
PERCPU_SECTION(32)
|
||||
PERCPU_SECTION(L1_CACHE_BYTES)
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
__data_loc = ALIGN(4); /* location in binary */
|
||||
|
@ -212,13 +213,13 @@ SECTIONS
|
|||
#endif
|
||||
|
||||
NOSAVE_DATA
|
||||
CACHELINE_ALIGNED_DATA(32)
|
||||
READ_MOSTLY_DATA(32)
|
||||
CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
|
||||
READ_MOSTLY_DATA(L1_CACHE_BYTES)
|
||||
|
||||
/*
|
||||
* The exception fixup table (might need resorting at runtime)
|
||||
*/
|
||||
. = ALIGN(32);
|
||||
. = ALIGN(4);
|
||||
__start___ex_table = .;
|
||||
#ifdef CONFIG_MMU
|
||||
*(__ex_table)
|
||||
|
|
|
@ -31,18 +31,18 @@
|
|||
#include <asm/domain.h>
|
||||
|
||||
ENTRY(__get_user_1)
|
||||
1: T(ldrb) r2, [r0]
|
||||
1: TUSER(ldrb) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__get_user_1)
|
||||
|
||||
ENTRY(__get_user_2)
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
2: T(ldrb) r2, [r0]
|
||||
3: T(ldrb) r3, [r0, #1]
|
||||
2: TUSER(ldrb) r2, [r0]
|
||||
3: TUSER(ldrb) r3, [r0, #1]
|
||||
#else
|
||||
2: T(ldrb) r2, [r0], #1
|
||||
3: T(ldrb) r3, [r0]
|
||||
2: TUSER(ldrb) r2, [r0], #1
|
||||
3: TUSER(ldrb) r3, [r0]
|
||||
#endif
|
||||
#ifndef __ARMEB__
|
||||
orr r2, r2, r3, lsl #8
|
||||
|
@ -54,7 +54,7 @@ ENTRY(__get_user_2)
|
|||
ENDPROC(__get_user_2)
|
||||
|
||||
ENTRY(__get_user_4)
|
||||
4: T(ldr) r2, [r0]
|
||||
4: TUSER(ldr) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__get_user_4)
|
||||
|
|
|
@ -31,7 +31,7 @@
|
|||
#include <asm/domain.h>
|
||||
|
||||
ENTRY(__put_user_1)
|
||||
1: T(strb) r2, [r0]
|
||||
1: TUSER(strb) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__put_user_1)
|
||||
|
@ -40,19 +40,19 @@ ENTRY(__put_user_2)
|
|||
mov ip, r2, lsr #8
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
#ifndef __ARMEB__
|
||||
2: T(strb) r2, [r0]
|
||||
3: T(strb) ip, [r0, #1]
|
||||
2: TUSER(strb) r2, [r0]
|
||||
3: TUSER(strb) ip, [r0, #1]
|
||||
#else
|
||||
2: T(strb) ip, [r0]
|
||||
3: T(strb) r2, [r0, #1]
|
||||
2: TUSER(strb) ip, [r0]
|
||||
3: TUSER(strb) r2, [r0, #1]
|
||||
#endif
|
||||
#else /* !CONFIG_THUMB2_KERNEL */
|
||||
#ifndef __ARMEB__
|
||||
2: T(strb) r2, [r0], #1
|
||||
3: T(strb) ip, [r0]
|
||||
2: TUSER(strb) r2, [r0], #1
|
||||
3: TUSER(strb) ip, [r0]
|
||||
#else
|
||||
2: T(strb) ip, [r0], #1
|
||||
3: T(strb) r2, [r0]
|
||||
2: TUSER(strb) ip, [r0], #1
|
||||
3: TUSER(strb) r2, [r0]
|
||||
#endif
|
||||
#endif /* CONFIG_THUMB2_KERNEL */
|
||||
mov r0, #0
|
||||
|
@ -60,18 +60,18 @@ ENTRY(__put_user_2)
|
|||
ENDPROC(__put_user_2)
|
||||
|
||||
ENTRY(__put_user_4)
|
||||
4: T(str) r2, [r0]
|
||||
4: TUSER(str) r2, [r0]
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
ENDPROC(__put_user_4)
|
||||
|
||||
ENTRY(__put_user_8)
|
||||
#ifdef CONFIG_THUMB2_KERNEL
|
||||
5: T(str) r2, [r0]
|
||||
6: T(str) r3, [r0, #4]
|
||||
5: TUSER(str) r2, [r0]
|
||||
6: TUSER(str) r3, [r0, #4]
|
||||
#else
|
||||
5: T(str) r2, [r0], #4
|
||||
6: T(str) r3, [r0]
|
||||
5: TUSER(str) r2, [r0], #4
|
||||
6: TUSER(str) r3, [r0]
|
||||
#endif
|
||||
mov r0, #0
|
||||
mov pc, lr
|
||||
|
|
|
@ -32,11 +32,11 @@
|
|||
rsb ip, ip, #4
|
||||
cmp ip, #2
|
||||
ldrb r3, [r1], #1
|
||||
USER( T(strb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strb) r3, [r0], #1) @ May fault
|
||||
ldrgeb r3, [r1], #1
|
||||
USER( T(strgeb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgeb) r3, [r0], #1) @ May fault
|
||||
ldrgtb r3, [r1], #1
|
||||
USER( T(strgtb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgtb) r3, [r0], #1) @ May fault
|
||||
sub r2, r2, ip
|
||||
b .Lc2u_dest_aligned
|
||||
|
||||
|
@ -59,7 +59,7 @@ ENTRY(__copy_to_user)
|
|||
addmi ip, r2, #4
|
||||
bmi .Lc2u_0nowords
|
||||
ldr r3, [r1], #4
|
||||
USER( T(str) r3, [r0], #4) @ May fault
|
||||
USER( TUSER( str) r3, [r0], #4) @ May fault
|
||||
mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
|
||||
rsb ip, ip, #0
|
||||
movs ip, ip, lsr #32 - PAGE_SHIFT
|
||||
|
@ -88,18 +88,18 @@ USER( T(str) r3, [r0], #4) @ May fault
|
|||
stmneia r0!, {r3 - r4} @ Shouldnt fault
|
||||
tst ip, #4
|
||||
ldrne r3, [r1], #4
|
||||
T(strne) r3, [r0], #4 @ Shouldnt fault
|
||||
TUSER( strne) r3, [r0], #4 @ Shouldnt fault
|
||||
ands ip, ip, #3
|
||||
beq .Lc2u_0fupi
|
||||
.Lc2u_0nowords: teq ip, #0
|
||||
beq .Lc2u_finished
|
||||
.Lc2u_nowords: cmp ip, #2
|
||||
ldrb r3, [r1], #1
|
||||
USER( T(strb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strb) r3, [r0], #1) @ May fault
|
||||
ldrgeb r3, [r1], #1
|
||||
USER( T(strgeb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgeb) r3, [r0], #1) @ May fault
|
||||
ldrgtb r3, [r1], #1
|
||||
USER( T(strgtb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgtb) r3, [r0], #1) @ May fault
|
||||
b .Lc2u_finished
|
||||
|
||||
.Lc2u_not_enough:
|
||||
|
@ -120,7 +120,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
|
|||
mov r3, r7, pull #8
|
||||
ldr r7, [r1], #4
|
||||
orr r3, r3, r7, push #24
|
||||
USER( T(str) r3, [r0], #4) @ May fault
|
||||
USER( TUSER( str) r3, [r0], #4) @ May fault
|
||||
mov ip, r0, lsl #32 - PAGE_SHIFT
|
||||
rsb ip, ip, #0
|
||||
movs ip, ip, lsr #32 - PAGE_SHIFT
|
||||
|
@ -155,18 +155,18 @@ USER( T(str) r3, [r0], #4) @ May fault
|
|||
movne r3, r7, pull #8
|
||||
ldrne r7, [r1], #4
|
||||
orrne r3, r3, r7, push #24
|
||||
T(strne) r3, [r0], #4 @ Shouldnt fault
|
||||
TUSER( strne) r3, [r0], #4 @ Shouldnt fault
|
||||
ands ip, ip, #3
|
||||
beq .Lc2u_1fupi
|
||||
.Lc2u_1nowords: mov r3, r7, get_byte_1
|
||||
teq ip, #0
|
||||
beq .Lc2u_finished
|
||||
cmp ip, #2
|
||||
USER( T(strb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strb) r3, [r0], #1) @ May fault
|
||||
movge r3, r7, get_byte_2
|
||||
USER( T(strgeb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgeb) r3, [r0], #1) @ May fault
|
||||
movgt r3, r7, get_byte_3
|
||||
USER( T(strgtb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgtb) r3, [r0], #1) @ May fault
|
||||
b .Lc2u_finished
|
||||
|
||||
.Lc2u_2fupi: subs r2, r2, #4
|
||||
|
@ -175,7 +175,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
|
|||
mov r3, r7, pull #16
|
||||
ldr r7, [r1], #4
|
||||
orr r3, r3, r7, push #16
|
||||
USER( T(str) r3, [r0], #4) @ May fault
|
||||
USER( TUSER( str) r3, [r0], #4) @ May fault
|
||||
mov ip, r0, lsl #32 - PAGE_SHIFT
|
||||
rsb ip, ip, #0
|
||||
movs ip, ip, lsr #32 - PAGE_SHIFT
|
||||
|
@ -210,18 +210,18 @@ USER( T(str) r3, [r0], #4) @ May fault
|
|||
movne r3, r7, pull #16
|
||||
ldrne r7, [r1], #4
|
||||
orrne r3, r3, r7, push #16
|
||||
T(strne) r3, [r0], #4 @ Shouldnt fault
|
||||
TUSER( strne) r3, [r0], #4 @ Shouldnt fault
|
||||
ands ip, ip, #3
|
||||
beq .Lc2u_2fupi
|
||||
.Lc2u_2nowords: mov r3, r7, get_byte_2
|
||||
teq ip, #0
|
||||
beq .Lc2u_finished
|
||||
cmp ip, #2
|
||||
USER( T(strb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strb) r3, [r0], #1) @ May fault
|
||||
movge r3, r7, get_byte_3
|
||||
USER( T(strgeb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgeb) r3, [r0], #1) @ May fault
|
||||
ldrgtb r3, [r1], #0
|
||||
USER( T(strgtb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgtb) r3, [r0], #1) @ May fault
|
||||
b .Lc2u_finished
|
||||
|
||||
.Lc2u_3fupi: subs r2, r2, #4
|
||||
|
@ -230,7 +230,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
|
|||
mov r3, r7, pull #24
|
||||
ldr r7, [r1], #4
|
||||
orr r3, r3, r7, push #8
|
||||
USER( T(str) r3, [r0], #4) @ May fault
|
||||
USER( TUSER( str) r3, [r0], #4) @ May fault
|
||||
mov ip, r0, lsl #32 - PAGE_SHIFT
|
||||
rsb ip, ip, #0
|
||||
movs ip, ip, lsr #32 - PAGE_SHIFT
|
||||
|
@ -265,18 +265,18 @@ USER( T(str) r3, [r0], #4) @ May fault
|
|||
movne r3, r7, pull #24
|
||||
ldrne r7, [r1], #4
|
||||
orrne r3, r3, r7, push #8
|
||||
T(strne) r3, [r0], #4 @ Shouldnt fault
|
||||
TUSER( strne) r3, [r0], #4 @ Shouldnt fault
|
||||
ands ip, ip, #3
|
||||
beq .Lc2u_3fupi
|
||||
.Lc2u_3nowords: mov r3, r7, get_byte_3
|
||||
teq ip, #0
|
||||
beq .Lc2u_finished
|
||||
cmp ip, #2
|
||||
USER( T(strb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strb) r3, [r0], #1) @ May fault
|
||||
ldrgeb r3, [r1], #1
|
||||
USER( T(strgeb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgeb) r3, [r0], #1) @ May fault
|
||||
ldrgtb r3, [r1], #0
|
||||
USER( T(strgtb) r3, [r0], #1) @ May fault
|
||||
USER( TUSER( strgtb) r3, [r0], #1) @ May fault
|
||||
b .Lc2u_finished
|
||||
ENDPROC(__copy_to_user)
|
||||
|
||||
|
@ -295,11 +295,11 @@ ENDPROC(__copy_to_user)
|
|||
.Lcfu_dest_not_aligned:
|
||||
rsb ip, ip, #4
|
||||
cmp ip, #2
|
||||
USER( T(ldrb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrb) r3, [r1], #1) @ May fault
|
||||
strb r3, [r0], #1
|
||||
USER( T(ldrgeb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
|
||||
strgeb r3, [r0], #1
|
||||
USER( T(ldrgtb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
|
||||
strgtb r3, [r0], #1
|
||||
sub r2, r2, ip
|
||||
b .Lcfu_dest_aligned
|
||||
|
@ -322,7 +322,7 @@ ENTRY(__copy_from_user)
|
|||
.Lcfu_0fupi: subs r2, r2, #4
|
||||
addmi ip, r2, #4
|
||||
bmi .Lcfu_0nowords
|
||||
USER( T(ldr) r3, [r1], #4)
|
||||
USER( TUSER( ldr) r3, [r1], #4)
|
||||
str r3, [r0], #4
|
||||
mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
|
||||
rsb ip, ip, #0
|
||||
|
@ -351,18 +351,18 @@ USER( T(ldr) r3, [r1], #4)
|
|||
ldmneia r1!, {r3 - r4} @ Shouldnt fault
|
||||
stmneia r0!, {r3 - r4}
|
||||
tst ip, #4
|
||||
T(ldrne) r3, [r1], #4 @ Shouldnt fault
|
||||
TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault
|
||||
strne r3, [r0], #4
|
||||
ands ip, ip, #3
|
||||
beq .Lcfu_0fupi
|
||||
.Lcfu_0nowords: teq ip, #0
|
||||
beq .Lcfu_finished
|
||||
.Lcfu_nowords: cmp ip, #2
|
||||
USER( T(ldrb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrb) r3, [r1], #1) @ May fault
|
||||
strb r3, [r0], #1
|
||||
USER( T(ldrgeb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
|
||||
strgeb r3, [r0], #1
|
||||
USER( T(ldrgtb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
|
||||
strgtb r3, [r0], #1
|
||||
b .Lcfu_finished
|
||||
|
||||
|
@ -375,7 +375,7 @@ USER( T(ldrgtb) r3, [r1], #1) @ May fault
|
|||
|
||||
.Lcfu_src_not_aligned:
|
||||
bic r1, r1, #3
|
||||
USER( T(ldr) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldr) r7, [r1], #4) @ May fault
|
||||
cmp ip, #2
|
||||
bgt .Lcfu_3fupi
|
||||
beq .Lcfu_2fupi
|
||||
|
@ -383,7 +383,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
|
|||
addmi ip, r2, #4
|
||||
bmi .Lcfu_1nowords
|
||||
mov r3, r7, pull #8
|
||||
USER( T(ldr) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldr) r7, [r1], #4) @ May fault
|
||||
orr r3, r3, r7, push #24
|
||||
str r3, [r0], #4
|
||||
mov ip, r1, lsl #32 - PAGE_SHIFT
|
||||
|
@ -418,7 +418,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
|
|||
stmneia r0!, {r3 - r4}
|
||||
tst ip, #4
|
||||
movne r3, r7, pull #8
|
||||
USER( T(ldrne) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldrne) r7, [r1], #4) @ May fault
|
||||
orrne r3, r3, r7, push #24
|
||||
strne r3, [r0], #4
|
||||
ands ip, ip, #3
|
||||
|
@ -438,7 +438,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
|
|||
addmi ip, r2, #4
|
||||
bmi .Lcfu_2nowords
|
||||
mov r3, r7, pull #16
|
||||
USER( T(ldr) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldr) r7, [r1], #4) @ May fault
|
||||
orr r3, r3, r7, push #16
|
||||
str r3, [r0], #4
|
||||
mov ip, r1, lsl #32 - PAGE_SHIFT
|
||||
|
@ -474,7 +474,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
|
|||
stmneia r0!, {r3 - r4}
|
||||
tst ip, #4
|
||||
movne r3, r7, pull #16
|
||||
USER( T(ldrne) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldrne) r7, [r1], #4) @ May fault
|
||||
orrne r3, r3, r7, push #16
|
||||
strne r3, [r0], #4
|
||||
ands ip, ip, #3
|
||||
|
@ -486,7 +486,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
|
|||
strb r3, [r0], #1
|
||||
movge r3, r7, get_byte_3
|
||||
strgeb r3, [r0], #1
|
||||
USER( T(ldrgtb) r3, [r1], #0) @ May fault
|
||||
USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault
|
||||
strgtb r3, [r0], #1
|
||||
b .Lcfu_finished
|
||||
|
||||
|
@ -494,7 +494,7 @@ USER( T(ldrgtb) r3, [r1], #0) @ May fault
|
|||
addmi ip, r2, #4
|
||||
bmi .Lcfu_3nowords
|
||||
mov r3, r7, pull #24
|
||||
USER( T(ldr) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldr) r7, [r1], #4) @ May fault
|
||||
orr r3, r3, r7, push #8
|
||||
str r3, [r0], #4
|
||||
mov ip, r1, lsl #32 - PAGE_SHIFT
|
||||
|
@ -529,7 +529,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
|
|||
stmneia r0!, {r3 - r4}
|
||||
tst ip, #4
|
||||
movne r3, r7, pull #24
|
||||
USER( T(ldrne) r7, [r1], #4) @ May fault
|
||||
USER( TUSER( ldrne) r7, [r1], #4) @ May fault
|
||||
orrne r3, r3, r7, push #8
|
||||
strne r3, [r0], #4
|
||||
ands ip, ip, #3
|
||||
|
@ -539,9 +539,9 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
|
|||
beq .Lcfu_finished
|
||||
cmp ip, #2
|
||||
strb r3, [r0], #1
|
||||
USER( T(ldrgeb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
|
||||
strgeb r3, [r0], #1
|
||||
USER( T(ldrgtb) r3, [r1], #1) @ May fault
|
||||
USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
|
||||
strgtb r3, [r0], #1
|
||||
b .Lcfu_finished
|
||||
ENDPROC(__copy_from_user)
|
||||
|
|
|
@ -18,6 +18,12 @@ config HAVE_AT91_USART4
|
|||
config HAVE_AT91_USART5
|
||||
bool
|
||||
|
||||
config AT91_SAM9_ALT_RESET
|
||||
bool
|
||||
|
||||
config AT91_SAM9G45_RESET
|
||||
bool
|
||||
|
||||
menu "Atmel AT91 System-on-Chip"
|
||||
|
||||
choice
|
||||
|
@ -39,6 +45,7 @@ config ARCH_AT91SAM9260
|
|||
select HAVE_AT91_USART4
|
||||
select HAVE_AT91_USART5
|
||||
select HAVE_NET_MACB
|
||||
select AT91_SAM9_ALT_RESET
|
||||
|
||||
config ARCH_AT91SAM9261
|
||||
bool "AT91SAM9261"
|
||||
|
@ -46,6 +53,7 @@ config ARCH_AT91SAM9261
|
|||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_DBGU0
|
||||
select AT91_SAM9_ALT_RESET
|
||||
|
||||
config ARCH_AT91SAM9G10
|
||||
bool "AT91SAM9G10"
|
||||
|
@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10
|
|||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select AT91_SAM9_ALT_RESET
|
||||
|
||||
config ARCH_AT91SAM9263
|
||||
bool "AT91SAM9263"
|
||||
|
@ -61,6 +70,7 @@ config ARCH_AT91SAM9263
|
|||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU1
|
||||
select AT91_SAM9_ALT_RESET
|
||||
|
||||
config ARCH_AT91SAM9RL
|
||||
bool "AT91SAM9RL"
|
||||
|
@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL
|
|||
select HAVE_AT91_USART3
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_DBGU0
|
||||
select AT91_SAM9_ALT_RESET
|
||||
|
||||
config ARCH_AT91SAM9G20
|
||||
bool "AT91SAM9G20"
|
||||
|
@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20
|
|||
select HAVE_AT91_USART4
|
||||
select HAVE_AT91_USART5
|
||||
select HAVE_NET_MACB
|
||||
select AT91_SAM9_ALT_RESET
|
||||
|
||||
config ARCH_AT91SAM9G45
|
||||
bool "AT91SAM9G45"
|
||||
|
@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45
|
|||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU1
|
||||
select AT91_SAM9G45_RESET
|
||||
|
||||
config ARCH_AT91CAP9
|
||||
bool "AT91CAP9"
|
||||
|
@ -96,6 +109,7 @@ config ARCH_AT91CAP9
|
|||
select HAVE_FB_ATMEL
|
||||
select HAVE_NET_MACB
|
||||
select HAVE_AT91_DBGU1
|
||||
select AT91_SAM9G45_RESET
|
||||
|
||||
config ARCH_AT91X40
|
||||
bool "AT91x40"
|
||||
|
|
|
@ -8,15 +8,17 @@ obj-n :=
|
|||
obj- :=
|
||||
|
||||
obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
|
||||
obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
|
||||
|
||||
# CPU-specific support
|
||||
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
|
||||
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <mach/cpu.h>
|
||||
#include <mach/at91cap9.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/at91_rstc.h>
|
||||
|
||||
#include "soc.h"
|
||||
#include "generic.h"
|
||||
|
@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static void at91cap9_restart(char mode, const char *cmd)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91CAP9 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void)
|
|||
static void __init at91cap9_ioremap_registers(void)
|
||||
{
|
||||
at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
|
||||
at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
|
||||
at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
|
||||
at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
|
||||
}
|
||||
|
||||
static void __init at91cap9_initialize(void)
|
||||
{
|
||||
arm_pm_restart = at91cap9_restart;
|
||||
arm_pm_restart = at91sam9g45_restart;
|
||||
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
|
||||
|
||||
/* Register GPIO subsystem */
|
||||
|
|
|
@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
|
|||
static void __init at91sam9260_ioremap_registers(void)
|
||||
{
|
||||
at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
|
||||
at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
|
||||
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
|
||||
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
|
||||
}
|
||||
|
|
|
@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
|
|||
static void __init at91sam9261_ioremap_registers(void)
|
||||
{
|
||||
at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
|
||||
at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
|
||||
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
|
||||
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
|
||||
}
|
||||
|
|
|
@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
|
|||
static void __init at91sam9263_ioremap_registers(void)
|
||||
{
|
||||
at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
|
||||
at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
|
||||
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
|
||||
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
|
||||
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
|
||||
|
|
|
@ -23,7 +23,8 @@
|
|||
.globl at91sam9_alt_restart
|
||||
|
||||
at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
|
||||
ldr r1, .at91_va_base_rstc_cr
|
||||
ldr r1, =at91_rstc_base
|
||||
ldr r1, [r1]
|
||||
|
||||
mov r2, #1
|
||||
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
|
||||
|
@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
|
|||
|
||||
str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
|
||||
str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
|
||||
str r4, [r1] @ reset processor
|
||||
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
||||
|
||||
b .
|
||||
|
||||
.at91_va_base_sdramc:
|
||||
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
|
||||
.at91_va_base_rstc_cr:
|
||||
.word AT91_VA_BASE_SYS + AT91_RSTC_CR
|
||||
|
|
|
@ -18,7 +18,6 @@
|
|||
#include <asm/mach/map.h>
|
||||
#include <mach/at91sam9g45.h>
|
||||
#include <mach/at91_pmc.h>
|
||||
#include <mach/at91_rstc.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
|
|||
}
|
||||
};
|
||||
|
||||
static void at91sam9g45_restart(char mode, const char *cmd)
|
||||
{
|
||||
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9G45 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void)
|
|||
static void __init at91sam9g45_ioremap_registers(void)
|
||||
{
|
||||
at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
|
||||
at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
|
||||
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
|
||||
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
|
||||
}
|
||||
|
|
40
arch/arm/mach-at91/at91sam9g45_reset.S
Normal file
40
arch/arm/mach-at91/at91sam9g45_reset.S
Normal file
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* reset AT91SAM9G45 as per errata
|
||||
*
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
|
||||
*
|
||||
* unless the SDRAM is cleanly shutdown before we hit the
|
||||
* reset register it can be left driving the data bus and
|
||||
* killing the chance of a subsequent boot from NAND
|
||||
*
|
||||
* GPLv2 Only
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
#include <mach/at91_rstc.h>
|
||||
|
||||
.arm
|
||||
|
||||
.globl at91sam9g45_restart
|
||||
|
||||
at91sam9g45_restart:
|
||||
ldr r0, .at91_va_base_sdramc0 @ preload constants
|
||||
ldr r1, =at91_rstc_base
|
||||
ldr r1, [r1]
|
||||
|
||||
mov r2, #1
|
||||
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
|
||||
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
|
||||
|
||||
.balign 32 @ align to cache line
|
||||
|
||||
str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
|
||||
str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
|
||||
str r4, [r1, #AT91_RSTC_CR] @ reset processor
|
||||
|
||||
b .
|
||||
|
||||
.at91_va_base_sdramc0:
|
||||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0
|
|
@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void)
|
|||
static void __init at91sam9rl_ioremap_registers(void)
|
||||
{
|
||||
at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
|
||||
at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
|
||||
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
|
||||
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
|
||||
}
|
||||
|
|
|
@ -58,7 +58,9 @@ extern void at91_irq_suspend(void);
|
|||
extern void at91_irq_resume(void);
|
||||
|
||||
/* reset */
|
||||
extern void at91_ioremap_rstc(u32 base_addr);
|
||||
extern void at91sam9_alt_restart(char, const char *);
|
||||
extern void at91sam9g45_restart(char, const char *);
|
||||
|
||||
/* shutdown */
|
||||
extern void at91_ioremap_shdwc(u32 base_addr);
|
||||
|
|
|
@ -16,13 +16,25 @@
|
|||
#ifndef AT91_RSTC_H
|
||||
#define AT91_RSTC_H
|
||||
|
||||
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void __iomem *at91_rstc_base;
|
||||
|
||||
#define at91_rstc_read(field) \
|
||||
__raw_readl(at91_rstc_base + field)
|
||||
|
||||
#define at91_rstc_write(field, value) \
|
||||
__raw_writel(value, at91_rstc_base + field);
|
||||
#else
|
||||
.extern at91_rstc_base
|
||||
#endif
|
||||
|
||||
#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
|
||||
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
|
||||
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
|
||||
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
|
||||
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
|
||||
|
||||
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
|
||||
#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
|
||||
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
|
||||
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
|
||||
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
|
||||
|
@ -33,7 +45,7 @@
|
|||
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
|
||||
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
|
||||
|
||||
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
|
||||
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
|
||||
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
|
||||
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
|
||||
|
|
|
@ -83,7 +83,6 @@
|
|||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
|
||||
(0xfffffd50 - AT91_BASE_SYS) : \
|
||||
(0xfffffd60 - AT91_BASE_SYS))
|
||||
|
@ -96,6 +95,7 @@
|
|||
#define AT91CAP9_BASE_PIOB 0xfffff400
|
||||
#define AT91CAP9_BASE_PIOC 0xfffff600
|
||||
#define AT91CAP9_BASE_PIOD 0xfffff800
|
||||
#define AT91CAP9_BASE_RSTC 0xfffffd00
|
||||
#define AT91CAP9_BASE_SHDWC 0xfffffd10
|
||||
#define AT91CAP9_BASE_RTT 0xfffffd20
|
||||
#define AT91CAP9_BASE_PIT 0xfffffd30
|
||||
|
|
|
@ -1,108 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
|
||||
*
|
||||
* (C) 2008 Andrew Victor
|
||||
*
|
||||
* DDR/SDR Controller (DDRSDRC) - System peripherals registers.
|
||||
* Based on AT91CAP9 datasheet revision B.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91CAP9_DDRSDR_H
|
||||
#define AT91CAP9_DDRSDR_H
|
||||
|
||||
#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
|
||||
#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
|
||||
#define AT91_DDRSDRC_MODE_NORMAL 0
|
||||
#define AT91_DDRSDRC_MODE_NOP 1
|
||||
#define AT91_DDRSDRC_MODE_PRECHARGE 2
|
||||
#define AT91_DDRSDRC_MODE_LMR 3
|
||||
#define AT91_DDRSDRC_MODE_REFRESH 4
|
||||
#define AT91_DDRSDRC_MODE_EXT_LMR 5
|
||||
#define AT91_DDRSDRC_MODE_DEEP 6
|
||||
|
||||
#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
|
||||
#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
|
||||
|
||||
#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
|
||||
#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
|
||||
#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
|
||||
#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
|
||||
#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
|
||||
#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
|
||||
#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
|
||||
#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
|
||||
#define AT91_DDRSDRC_NR_11 (0 << 2)
|
||||
#define AT91_DDRSDRC_NR_12 (1 << 2)
|
||||
#define AT91_DDRSDRC_NR_13 (2 << 2)
|
||||
#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
|
||||
#define AT91_DDRSDRC_CAS_2 (2 << 4)
|
||||
#define AT91_DDRSDRC_CAS_3 (3 << 4)
|
||||
#define AT91_DDRSDRC_CAS_25 (6 << 4)
|
||||
#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
|
||||
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
|
||||
|
||||
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
|
||||
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
|
||||
#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
|
||||
#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
|
||||
#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
|
||||
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
||||
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
||||
#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
|
||||
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
||||
|
||||
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
|
||||
#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
|
||||
#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
|
||||
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
|
||||
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
|
||||
|
||||
#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
|
||||
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
||||
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
||||
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
||||
#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
|
||||
#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
|
||||
#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
|
||||
#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
|
||||
#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
|
||||
#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
|
||||
#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
|
||||
#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
|
||||
#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
|
||||
#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
|
||||
|
||||
#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
|
||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||
#define AT91_DDRSDRC_MD_SDR 0
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||
#define AT91_DDRSDRC_MD_DDR 2
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||
|
||||
#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
|
||||
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
||||
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
||||
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
||||
#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
|
||||
#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
|
||||
#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
|
||||
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
||||
#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
|
||||
#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
|
||||
|
||||
/* Register access macros */
|
||||
#define at91_ramc_read(num, reg) \
|
||||
at91_sys_read(AT91_DDRSDRC##num + reg)
|
||||
#define at91_ramc_write(num, reg, value) \
|
||||
at91_sys_write(AT91_DDRSDRC##num + reg, value)
|
||||
|
||||
|
||||
#endif
|
|
@ -83,7 +83,6 @@
|
|||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9260_BASE_ECC 0xffffe800
|
||||
|
@ -92,6 +91,7 @@
|
|||
#define AT91SAM9260_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9260_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9260_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9260_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9260_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9260_BASE_PIT 0xfffffd30
|
||||
|
|
|
@ -68,7 +68,6 @@
|
|||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9261_BASE_SMC 0xffffec00
|
||||
|
@ -76,6 +75,7 @@
|
|||
#define AT91SAM9261_BASE_PIOA 0xfffff400
|
||||
#define AT91SAM9261_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9261_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9261_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9261_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9261_BASE_PIT 0xfffffd30
|
||||
|
|
|
@ -78,7 +78,6 @@
|
|||
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9263_BASE_ECC0 0xffffe000
|
||||
|
@ -91,6 +90,7 @@
|
|||
#define AT91SAM9263_BASE_PIOC 0xfffff600
|
||||
#define AT91SAM9263_BASE_PIOD 0xfffff800
|
||||
#define AT91SAM9263_BASE_PIOE 0xfffffa00
|
||||
#define AT91SAM9263_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9263_BASE_RTT0 0xfffffd20
|
||||
#define AT91SAM9263_BASE_PIT 0xfffffd30
|
||||
|
|
|
@ -46,10 +46,10 @@
|
|||
#define AT91_DDRSDRC_CAS_25 (6 << 4)
|
||||
#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
|
||||
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
|
||||
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
|
||||
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
|
||||
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
|
||||
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
|
||||
#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
|
||||
|
||||
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
|
||||
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
|
||||
|
@ -59,7 +59,8 @@
|
|||
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
|
||||
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
|
||||
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
|
||||
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
|
||||
#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
|
||||
#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
|
||||
|
||||
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
|
||||
|
@ -68,13 +69,14 @@
|
|||
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
|
||||
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
|
||||
|
||||
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
|
||||
#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
|
||||
#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
|
||||
#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
|
||||
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
|
||||
|
||||
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
|
||||
#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
|
||||
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
|
||||
#define AT91_DDRSDRC_LPCB_DISABLE 0
|
||||
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
|
||||
|
@ -92,32 +94,40 @@
|
|||
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
|
||||
|
||||
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
|
||||
#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
|
||||
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
|
||||
#define AT91_DDRSDRC_MD_SDR 0
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
|
||||
#define AT91CAP9_DDRSDRC_MD_DDR 2
|
||||
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
|
||||
#define AT91_DDRSDRC_MD_DDR2 6
|
||||
#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
|
||||
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
|
||||
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
|
||||
|
||||
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
|
||||
#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
|
||||
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
|
||||
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
|
||||
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
|
||||
#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
|
||||
#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
|
||||
#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
|
||||
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
|
||||
#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
|
||||
#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
|
||||
|
||||
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
|
||||
#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
|
||||
|
||||
#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
|
||||
|
||||
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
|
||||
#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
|
||||
#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
|
||||
#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
|
||||
|
||||
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
|
||||
#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
|
||||
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
|
||||
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
|
||||
|
||||
|
|
|
@ -90,7 +90,6 @@
|
|||
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
#define AT91SAM9G45_BASE_ECC 0xffffe200
|
||||
|
@ -102,6 +101,7 @@
|
|||
#define AT91SAM9G45_BASE_PIOC 0xfffff600
|
||||
#define AT91SAM9G45_BASE_PIOD 0xfffff800
|
||||
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
|
||||
#define AT91SAM9G45_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9G45_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9G45_BASE_PIT 0xfffffd30
|
||||
|
|
|
@ -72,7 +72,6 @@
|
|||
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
|
||||
|
@ -84,6 +83,7 @@
|
|||
#define AT91SAM9RL_BASE_PIOB 0xfffff600
|
||||
#define AT91SAM9RL_BASE_PIOC 0xfffff800
|
||||
#define AT91SAM9RL_BASE_PIOD 0xfffffa00
|
||||
#define AT91SAM9RL_BASE_RSTC 0xfffffd00
|
||||
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
|
||||
#define AT91SAM9RL_BASE_RTT 0xfffffd20
|
||||
#define AT91SAM9RL_BASE_PIT 0xfffffd30
|
||||
|
|
|
@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
|
|||
struct at91_usbh_data {
|
||||
u8 ports; /* number of ports on root hub */
|
||||
int vbus_pin[2]; /* port power-control pin */
|
||||
u8 vbus_pin_inverted;
|
||||
u8 vbus_pin_active_low[2];
|
||||
u8 overcurrent_supported;
|
||||
int overcurrent_pin[2];
|
||||
u8 overcurrent_status[2];
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
/*
|
||||
* Show the reason for the previous system reset.
|
||||
*/
|
||||
#if defined(AT91_RSTC)
|
||||
|
||||
#include <mach/at91_rstc.h>
|
||||
#include <mach/at91_shdwc.h>
|
||||
|
@ -58,10 +57,10 @@ static void __init show_reset_status(void)
|
|||
char *reason, *r2 = reset;
|
||||
u32 reset_type, wake_type;
|
||||
|
||||
if (!at91_shdwc_base)
|
||||
if (!at91_shdwc_base || !at91_rstc_base)
|
||||
return;
|
||||
|
||||
reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
|
||||
reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
|
||||
wake_type = at91_shdwc_read(AT91_SHDW_SR);
|
||||
|
||||
switch (reset_type) {
|
||||
|
@ -102,10 +101,6 @@ static void __init show_reset_status(void)
|
|||
}
|
||||
pr_info("AT91: Starting after %s %s\n", reason, r2);
|
||||
}
|
||||
#else
|
||||
static void __init show_reset_status(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
static int at91_pm_valid_state(suspend_state_t state)
|
||||
{
|
||||
|
|
|
@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
|
|||
: : "r" (0))
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#include <mach/at91cap9_ddrsdr.h>
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
|
||||
|
||||
static inline u32 sdram_selfrefresh_enable(void)
|
||||
{
|
||||
u32 saved_lpr, lpr;
|
||||
|
||||
saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
|
||||
saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
|
||||
|
||||
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
|
||||
at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
||||
at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
|
||||
return saved_lpr;
|
||||
}
|
||||
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
|
||||
#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
|
||||
#define wait_for_interrupt_enable() cpu_do_idle()
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
|
|
|
@ -18,9 +18,8 @@
|
|||
|
||||
#if defined(CONFIG_ARCH_AT91RM9200)
|
||||
#include <mach/at91rm9200_mc.h>
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#include <mach/at91cap9_ddrsdr.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9) \
|
||||
|| defined(CONFIG_ARCH_AT91SAM9G45)
|
||||
#include <mach/at91sam9_ddrsdr.h>
|
||||
#else
|
||||
#include <mach/at91sam9_sdramc.h>
|
||||
|
|
|
@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata);
|
|||
void __init at91rm9200_set_type(int type)
|
||||
{
|
||||
if (type == ARCH_REVISON_9200_PQFP)
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
else
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
|
||||
else
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
|
||||
pr_info("AT91: filled in soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __init at91_init_irq_default(void)
|
||||
|
@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr)
|
|||
pm_power_off = at91sam9_poweroff;
|
||||
}
|
||||
|
||||
void __iomem *at91_rstc_base;
|
||||
|
||||
void __init at91_ioremap_rstc(u32 base_addr)
|
||||
{
|
||||
at91_rstc_base = ioremap(base_addr, 16);
|
||||
if (!at91_rstc_base)
|
||||
panic("Impossible to ioremap at91_rstc_base\n");
|
||||
}
|
||||
|
||||
void __init at91_initialize(unsigned long main_clock)
|
||||
{
|
||||
at91_boot_soc.ioremap_registers();
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/io.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/hardware/arm_timer.h>
|
||||
#include <asm/hardware/timer-sp.h>
|
||||
|
@ -72,9 +73,7 @@ static void __init highbank_map_io(void)
|
|||
|
||||
void highbank_set_cpu_jump(int cpu, void *jump_addr)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
cpu = cpu_logical_map(cpu);
|
||||
#endif
|
||||
writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
|
||||
__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
|
||||
outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
|
||||
|
|
|
@ -87,7 +87,6 @@ config SOC_IMX35
|
|||
|
||||
config SOC_IMX5
|
||||
select CPU_V7
|
||||
select ARM_L1_CACHE_SHIFT_6
|
||||
select MXC_TZIC
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select ARCH_MXC_AUDMUX_V2
|
||||
|
|
|
@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
|
|||
DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
|
||||
DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
|
||||
|
||||
static unsigned long twd_clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk_get_rate(clk->parent) / 2;
|
||||
}
|
||||
|
||||
static struct clk twd_clk = {
|
||||
.parent = &arm_clk,
|
||||
.get_rate = twd_clk_get_rate,
|
||||
};
|
||||
|
||||
static unsigned long pll2_200m_get_rate(struct clk *clk)
|
||||
{
|
||||
return clk_get_rate(clk->parent) / 2;
|
||||
|
@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = {
|
|||
_REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
|
||||
_REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
|
||||
_REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
|
||||
_REGISTER_CLOCK("smp_twd", NULL, twd_clk),
|
||||
_REGISTER_CLOCK(NULL, "ckih", ckih_clk),
|
||||
_REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
|
||||
_REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
|
||||
|
|
|
@ -188,8 +188,10 @@ static int weim_cs_config(void)
|
|||
return -ENOMEM;
|
||||
|
||||
iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
|
||||
if (!iomuxc_base)
|
||||
if (!iomuxc_base) {
|
||||
iounmap(weim_base);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* CS1 timings for LAN9220 */
|
||||
writel(0x20001, (weim_base + 0x18));
|
||||
|
|
|
@ -15,6 +15,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#define SRC_SCR 0x000
|
||||
#define SRC_GPR1 0x020
|
||||
|
@ -24,10 +25,6 @@
|
|||
|
||||
static void __iomem *src_base;
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
#define cpu_logical_map(cpu) 0
|
||||
#endif
|
||||
|
||||
void imx_enable_cpu(int cpu, bool enable)
|
||||
{
|
||||
u32 mask, val;
|
||||
|
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
extern volatile int pen_release;
|
||||
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/cputype.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#include <mach/msm_iomap.h>
|
||||
|
||||
|
|
|
@ -33,7 +33,6 @@ config ARCH_OMAP3
|
|||
default y
|
||||
select CPU_V7
|
||||
select USB_ARCH_HAS_EHCI
|
||||
select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
|
||||
select ARCH_HAS_OPP
|
||||
select PM_OPP if PM
|
||||
select ARM_CPU_SUSPEND if PM
|
||||
|
|
|
@ -415,29 +415,9 @@ static struct resource pxa_rtc_resources[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct resource sa1100_rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x40900000,
|
||||
.end = 0x409000ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_RTC1Hz,
|
||||
.end = IRQ_RTC1Hz,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_RTCAlrm,
|
||||
.end = IRQ_RTCAlrm,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device sa1100_device_rtc = {
|
||||
.name = "sa1100-rtc",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(sa1100_rtc_resources),
|
||||
.resource = sa1100_rtc_resources,
|
||||
};
|
||||
|
||||
struct platform_device pxa_device_rtc = {
|
||||
|
|
|
@ -209,8 +209,6 @@ static struct clk_lookup pxa25x_clkregs[] = {
|
|||
INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
|
||||
INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
|
||||
INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
};
|
||||
|
||||
static struct clk_lookup pxa25x_hwuart_clkreg =
|
||||
|
|
|
@ -230,8 +230,6 @@ static struct clk_lookup pxa27x_clkregs[] = {
|
|||
INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
|
||||
INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
|
||||
INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
|
|
@ -89,7 +89,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
|
|||
static struct clk_lookup common_clkregs[] = {
|
||||
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
|
||||
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
};
|
||||
|
||||
static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
|
||||
|
|
|
@ -83,7 +83,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
|
|||
static struct clk_lookup pxa320_clkregs[] = {
|
||||
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
|
||||
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
};
|
||||
|
||||
static int __init pxa320_init(void)
|
||||
|
|
|
@ -67,7 +67,6 @@ static struct clk_lookup pxa3xx_clkregs[] = {
|
|||
INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
|
||||
/* Power I2C clock is always on */
|
||||
INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
|
||||
INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
|
||||
INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
|
||||
|
|
|
@ -217,7 +217,6 @@ static struct clk_lookup pxa95x_clkregs[] = {
|
|||
INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
|
||||
/* Power I2C clock is always on */
|
||||
INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
|
||||
INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
|
||||
INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
extern volatile int pen_release;
|
||||
|
||||
|
|
|
@ -47,21 +47,23 @@
|
|||
#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
|
||||
|
||||
#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
|
||||
#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
|
||||
#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
|
||||
#define REALVIEW_EB11MP_TWD_BASE 0x10100600
|
||||
#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
|
||||
#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
|
||||
#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
|
||||
#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
|
||||
#else
|
||||
#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
|
||||
#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
|
||||
#define REALVIEW_EB11MP_TWD_BASE 0x1F000600
|
||||
#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
|
||||
#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
|
||||
#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
|
||||
#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
|
||||
#endif
|
||||
|
||||
#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
|
||||
#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
|
||||
|
||||
#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
|
||||
#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
|
||||
#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
|
||||
#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
|
||||
|
||||
/*
|
||||
* Core tile identification (REALVIEW_SYS_PROCID)
|
||||
*/
|
||||
|
|
|
@ -75,6 +75,8 @@
|
|||
/*
|
||||
* Testchip peripheral and fpga gic regions
|
||||
*/
|
||||
#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000
|
||||
#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K
|
||||
#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
|
||||
#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
|
||||
#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
|
||||
|
|
|
@ -91,14 +91,9 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
|
|||
|
||||
static struct map_desc realview_eb11mp_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE),
|
||||
.pfn = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
|
||||
.pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
|
||||
.length = SZ_4K,
|
||||
.virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
|
||||
.pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
|
||||
.length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
|
||||
|
|
|
@ -64,15 +64,10 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
|
||||
.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
|
||||
.pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
|
||||
.length = SZ_4K,
|
||||
}, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
|
||||
.virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
|
||||
.pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
|
||||
.length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
|
||||
|
|
|
@ -202,7 +202,6 @@ static struct irda_platform_data assabet_irda_data = {
|
|||
static struct mcp_plat_data assabet_mcp_data = {
|
||||
.mccr0 = MCCR0_ADM,
|
||||
.sclk_rate = 11981000,
|
||||
.codec = "ucb1x00",
|
||||
};
|
||||
|
||||
static void __init assabet_init(void)
|
||||
|
@ -253,17 +252,6 @@ static void __init assabet_init(void)
|
|||
sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
|
||||
ARRAY_SIZE(assabet_flash_resources));
|
||||
sa11x0_register_irda(&assabet_irda_data);
|
||||
|
||||
/*
|
||||
* Setup the PPC unit correctly.
|
||||
*/
|
||||
PPDR &= ~PPC_RXD4;
|
||||
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
|
||||
PSDR |= PPC_RXD4;
|
||||
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
|
||||
ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
|
||||
sa11x0_register_mcp(&assabet_mcp_data);
|
||||
}
|
||||
|
||||
|
|
|
@ -124,23 +124,12 @@ static void __init cerf_map_io(void)
|
|||
static struct mcp_plat_data cerf_mcp_data = {
|
||||
.mccr0 = MCCR0_ADM,
|
||||
.sclk_rate = 11981000,
|
||||
.codec = "ucb1x00",
|
||||
};
|
||||
|
||||
static void __init cerf_init(void)
|
||||
{
|
||||
platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
|
||||
sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
|
||||
|
||||
/*
|
||||
* Setup the PPC unit correctly.
|
||||
*/
|
||||
PPDR &= ~PPC_RXD4;
|
||||
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
|
||||
PSDR |= PPC_RXD4;
|
||||
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
|
||||
sa11x0_register_mcp(&cerf_mcp_data);
|
||||
}
|
||||
|
||||
|
|
|
@ -11,39 +11,17 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
struct clkops {
|
||||
void (*enable)(struct clk *);
|
||||
void (*disable)(struct clk *);
|
||||
unsigned long (*getrate)(struct clk *);
|
||||
};
|
||||
|
||||
/*
|
||||
* Very simple clock implementation - we only have one clock to deal with.
|
||||
*/
|
||||
struct clk {
|
||||
const struct clkops *ops;
|
||||
unsigned long rate;
|
||||
unsigned int enabled;
|
||||
};
|
||||
|
||||
#define INIT_CLKREG(_clk, _devname, _conname) \
|
||||
{ \
|
||||
.clk = _clk, \
|
||||
.dev_id = _devname, \
|
||||
.con_id = _conname, \
|
||||
}
|
||||
|
||||
#define DEFINE_CLK(_name, _ops, _rate) \
|
||||
struct clk clk_##_name = { \
|
||||
.ops = _ops, \
|
||||
.rate = _rate, \
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(clocks_lock);
|
||||
|
||||
static void clk_gpio27_enable(struct clk *clk)
|
||||
static void clk_gpio27_enable(void)
|
||||
{
|
||||
/*
|
||||
* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
|
||||
|
@ -54,22 +32,38 @@ static void clk_gpio27_enable(struct clk *clk)
|
|||
TUCR = TUCR_3_6864MHz;
|
||||
}
|
||||
|
||||
static void clk_gpio27_disable(struct clk *clk)
|
||||
static void clk_gpio27_disable(void)
|
||||
{
|
||||
TUCR = 0;
|
||||
GPDR &= ~GPIO_32_768kHz;
|
||||
GAFR &= ~GPIO_32_768kHz;
|
||||
}
|
||||
|
||||
static struct clk clk_gpio27;
|
||||
|
||||
static DEFINE_SPINLOCK(clocks_lock);
|
||||
|
||||
struct clk *clk_get(struct device *dev, const char *id)
|
||||
{
|
||||
const char *devname = dev_name(dev);
|
||||
|
||||
return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get);
|
||||
|
||||
void clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_put);
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (clk->enabled++ == 0)
|
||||
clk->ops->enable(clk);
|
||||
clk_gpio27_enable();
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_enable);
|
||||
|
@ -82,48 +76,13 @@ void clk_disable(struct clk *clk)
|
|||
|
||||
spin_lock_irqsave(&clocks_lock, flags);
|
||||
if (--clk->enabled == 0)
|
||||
clk->ops->disable(clk);
|
||||
clk_gpio27_disable();
|
||||
spin_unlock_irqrestore(&clocks_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_disable);
|
||||
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
rate = clk->rate;
|
||||
if (clk->ops->getrate)
|
||||
rate = clk->ops->getrate(clk);
|
||||
|
||||
return rate;
|
||||
return 3686400;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
const struct clkops clk_gpio27_ops = {
|
||||
.enable = clk_gpio27_enable,
|
||||
.disable = clk_gpio27_disable,
|
||||
};
|
||||
|
||||
static void clk_dummy_enable(struct clk *clk) { }
|
||||
static void clk_dummy_disable(struct clk *clk) { }
|
||||
|
||||
const struct clkops clk_dummy_ops = {
|
||||
.enable = clk_dummy_enable,
|
||||
.disable = clk_dummy_disable,
|
||||
};
|
||||
|
||||
static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400);
|
||||
static DEFINE_CLK(dummy, &clk_dummy_ops, 0);
|
||||
|
||||
static struct clk_lookup sa11xx_clkregs[] = {
|
||||
INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL),
|
||||
INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
|
||||
};
|
||||
|
||||
static int __init sa11xx_clk_init(void)
|
||||
{
|
||||
clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
|
||||
return 0;
|
||||
}
|
||||
|
||||
postcore_initcall(sa11xx_clk_init);
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <linux/timer.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pda_power.h>
|
||||
#include <linux/mfd/ucb1x00.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -86,15 +85,10 @@ static struct scoop_pcmcia_config collie_pcmcia_config = {
|
|||
.num_devs = 1,
|
||||
};
|
||||
|
||||
static struct ucb1x00_plat_data collie_ucb1x00_data = {
|
||||
.gpio_base = COLLIE_TC35143_GPIO_BASE,
|
||||
};
|
||||
|
||||
static struct mcp_plat_data collie_mcp_data = {
|
||||
.mccr0 = MCCR0_ADM | MCCR0_ExtClk,
|
||||
.sclk_rate = 9216000,
|
||||
.codec = "ucb1x00",
|
||||
.codec_pdata = &collie_ucb1x00_data,
|
||||
.gpio_base = COLLIE_TC35143_GPIO_BASE,
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -144,8 +138,6 @@ static struct pda_power_pdata collie_power_data = {
|
|||
static struct resource collie_power_resource[] = {
|
||||
{
|
||||
.name = "ac",
|
||||
.start = gpio_to_irq(COLLIE_GPIO_AC_IN),
|
||||
.end = gpio_to_irq(COLLIE_GPIO_AC_IN),
|
||||
.flags = IORESOURCE_IRQ |
|
||||
IORESOURCE_IRQ_HIGHEDGE |
|
||||
IORESOURCE_IRQ_LOWEDGE,
|
||||
|
@ -347,7 +339,8 @@ static void __init collie_init(void)
|
|||
|
||||
GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
|
||||
|
||||
|
||||
collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
|
||||
collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
|
||||
platform_scoop_config = &collie_pcmcia_config;
|
||||
|
||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
@ -357,16 +350,6 @@ static void __init collie_init(void)
|
|||
|
||||
sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
|
||||
ARRAY_SIZE(collie_flash_resources));
|
||||
|
||||
/*
|
||||
* Setup the PPC unit correctly.
|
||||
*/
|
||||
PPDR &= ~PPC_RXD4;
|
||||
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
|
||||
PSDR |= PPC_RXD4;
|
||||
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
|
||||
sa11x0_register_mcp(&collie_mcp_data);
|
||||
|
||||
sharpsl_save_param();
|
||||
|
|
|
@ -228,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct cpufreq_driver sa1100_driver = {
|
||||
static struct cpufreq_driver sa1100_driver __refdata = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = sa11x0_verify_speed,
|
||||
.target = sa1100_target,
|
||||
|
|
|
@ -217,15 +217,10 @@ static struct platform_device sa11x0uart3_device = {
|
|||
static struct resource sa11x0mcp_resources[] = {
|
||||
[0] = {
|
||||
.start = __PREG(Ser4MCCR0),
|
||||
.end = __PREG(Ser4MCCR0) + 0x1C - 1,
|
||||
.end = __PREG(Ser4MCCR0) + 0xffff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = __PREG(Ser4MCCR1),
|
||||
.end = __PREG(Ser4MCCR1) + 0x4 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_Ser4MCP,
|
||||
.end = IRQ_Ser4MCP,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
@ -350,29 +345,9 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
|
|||
sa11x0_register_device(&sa11x0ir_device, irda);
|
||||
}
|
||||
|
||||
static struct resource sa11x0rtc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x90010000,
|
||||
.end = 0x900100ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_RTC1Hz,
|
||||
.end = IRQ_RTC1Hz,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_RTCAlrm,
|
||||
.end = IRQ_RTCAlrm,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device sa11x0rtc_device = {
|
||||
.name = "sa1100-rtc",
|
||||
.id = -1,
|
||||
.resource = sa11x0rtc_resources,
|
||||
.num_resources = ARRAY_SIZE(sa11x0rtc_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *sa11x0_devices[] __initdata = {
|
||||
|
|
|
@ -17,8 +17,6 @@ struct mcp_plat_data {
|
|||
u32 mccr1;
|
||||
unsigned int sclk_rate;
|
||||
int gpio_base;
|
||||
const char *codec;
|
||||
void *codec_pdata;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
@ -198,3 +198,5 @@ static int __init jornada_ssp_init(void)
|
|||
{
|
||||
return platform_driver_register(&jornadassp_driver);
|
||||
}
|
||||
|
||||
module_init(jornada_ssp_init);
|
||||
|
|
|
@ -24,20 +24,10 @@
|
|||
static struct mcp_plat_data lart_mcp_data = {
|
||||
.mccr0 = MCCR0_ADM,
|
||||
.sclk_rate = 11981000,
|
||||
.codec = "ucb1x00",
|
||||
};
|
||||
|
||||
static void __init lart_init(void)
|
||||
{
|
||||
/*
|
||||
* Setup the PPC unit correctly.
|
||||
*/
|
||||
PPDR &= ~PPC_RXD4;
|
||||
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
|
||||
PSDR |= PPC_RXD4;
|
||||
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
|
||||
sa11x0_register_mcp(&lart_mcp_data);
|
||||
}
|
||||
|
||||
|
|
|
@ -55,22 +55,11 @@ static struct resource shannon_flash_resource = {
|
|||
static struct mcp_plat_data shannon_mcp_data = {
|
||||
.mccr0 = MCCR0_ADM,
|
||||
.sclk_rate = 11981000,
|
||||
.codec = "ucb1x00",
|
||||
};
|
||||
|
||||
static void __init shannon_init(void)
|
||||
{
|
||||
sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
|
||||
|
||||
/*
|
||||
* Setup the PPC unit correctly.
|
||||
*/
|
||||
PPDR &= ~PPC_RXD4;
|
||||
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
|
||||
PSDR |= PPC_RXD4;
|
||||
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
|
||||
sa11x0_register_mcp(&shannon_mcp_data);
|
||||
}
|
||||
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mfd/ucb1x00.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
|
@ -188,15 +187,10 @@ static struct resource simpad_flash_resources [] = {
|
|||
}
|
||||
};
|
||||
|
||||
static struct ucb1x00_plat_data simpad_ucb1x00_data = {
|
||||
.gpio_base = SIMPAD_UCB1X00_GPIO_BASE,
|
||||
};
|
||||
|
||||
static struct mcp_plat_data simpad_mcp_data = {
|
||||
.mccr0 = MCCR0_ADM,
|
||||
.sclk_rate = 11981000,
|
||||
.codec = "ucb1300",
|
||||
.codec_pdata = &simpad_ucb1x00_data,
|
||||
.gpio_base = SIMPAD_UCB1X00_GPIO_BASE,
|
||||
};
|
||||
|
||||
|
||||
|
@ -384,16 +378,6 @@ static int __init simpad_init(void)
|
|||
|
||||
sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
|
||||
ARRAY_SIZE(simpad_flash_resources));
|
||||
|
||||
/*
|
||||
* Setup the PPC unit correctly.
|
||||
*/
|
||||
PPDR &= ~PPC_RXD4;
|
||||
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
|
||||
PSDR |= PPC_RXD4;
|
||||
PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
|
||||
|
||||
sa11x0_register_mcp(&simpad_mcp_data);
|
||||
|
||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/delay.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
|
|
@ -7,6 +7,7 @@ config UX500_SOC_COMMON
|
|||
select HAS_MTU
|
||||
select ARM_ERRATA_753970
|
||||
select ARM_ERRATA_754322
|
||||
select ARM_ERRATA_764369
|
||||
|
||||
menu "Ux500 SoC"
|
||||
|
||||
|
|
|
@ -261,6 +261,8 @@ void __init mop500_sdi_init(void)
|
|||
|
||||
void __init snowball_sdi_init(void)
|
||||
{
|
||||
/* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
|
||||
mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
|
||||
/* On-board eMMC */
|
||||
db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
|
||||
/* External Micro SD slot */
|
||||
|
|
|
@ -12,44 +12,6 @@
|
|||
|
||||
static void __iomem *l2x0_base;
|
||||
|
||||
static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
|
||||
{
|
||||
/* wait for the operation to complete */
|
||||
while (readl_relaxed(reg) & mask)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static inline void ux500_cache_sync(void)
|
||||
{
|
||||
writel_relaxed(0, l2x0_base + L2X0_CACHE_SYNC);
|
||||
ux500_cache_wait(l2x0_base + L2X0_CACHE_SYNC, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* The L2 cache cannot be turned off in the non-secure world.
|
||||
* Dummy until a secure service is in place.
|
||||
*/
|
||||
static void ux500_l2x0_disable(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* This is only called when doing a kexec, just after turning off the L2
|
||||
* and L1 cache, and it is surrounded by a spinlock in the generic version.
|
||||
* However, we're not really turning off the L2 cache right now and the
|
||||
* PL310 does not support exclusive accesses (used to implement the spinlock).
|
||||
* So, the invalidation needs to be done without the spinlock.
|
||||
*/
|
||||
static void ux500_l2x0_inv_all(void)
|
||||
{
|
||||
uint32_t l2x0_way_mask = (1<<16) - 1; /* Bitmask of active ways */
|
||||
|
||||
/* invalidate all ways */
|
||||
writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
|
||||
ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
|
||||
ux500_cache_sync();
|
||||
}
|
||||
|
||||
static int __init ux500_l2x0_unlock(void)
|
||||
{
|
||||
int i;
|
||||
|
@ -85,9 +47,13 @@ static int __init ux500_l2x0_init(void)
|
|||
/* 64KB way size, 8 way associativity, force WA */
|
||||
l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
|
||||
|
||||
/* Override invalidate function */
|
||||
outer_cache.disable = ux500_l2x0_disable;
|
||||
outer_cache.inv_all = ux500_l2x0_inv_all;
|
||||
/*
|
||||
* We can't disable l2 as we are in non secure mode, currently
|
||||
* this seems be called only during kexec path. So let's
|
||||
* override outer.disable with nasty assignment until we have
|
||||
* some SMI service available.
|
||||
*/
|
||||
outer_cache.disable = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
extern volatile int pen_release;
|
||||
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/setup.h>
|
||||
|
|
|
@ -95,13 +95,7 @@ static struct musb_hdrc_config musb_hdrc_config = {
|
|||
};
|
||||
|
||||
static struct musb_hdrc_platform_data musb_platform_data = {
|
||||
#if defined(CONFIG_USB_MUSB_OTG)
|
||||
.mode = MUSB_OTG,
|
||||
#elif defined(CONFIG_USB_MUSB_PERIPHERAL)
|
||||
.mode = MUSB_PERIPHERAL,
|
||||
#else /* defined(CONFIG_USB_MUSB_HOST) */
|
||||
.mode = MUSB_HOST,
|
||||
#endif
|
||||
.config = &musb_hdrc_config,
|
||||
.board_data = &musb_board_data,
|
||||
};
|
||||
|
|
|
@ -217,7 +217,7 @@ static void __init ct_ca9x4_init(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void ct_ca9x4_init_cpu_map(void)
|
||||
static void __init ct_ca9x4_init_cpu_map(void)
|
||||
{
|
||||
int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
|
||||
|
||||
|
@ -233,7 +233,7 @@ static void ct_ca9x4_init_cpu_map(void)
|
|||
set_smp_cross_call(gic_raise_softirq);
|
||||
}
|
||||
|
||||
static void ct_ca9x4_smp_enable(unsigned int max_cpus)
|
||||
static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)
|
||||
{
|
||||
scu_enable(MMIO_P2V(A9_MPCORE_SCU));
|
||||
}
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
extern volatile int pen_release;
|
||||
|
|
|
@ -882,6 +882,7 @@ config CACHE_XSC3L2
|
|||
|
||||
config ARM_L1_CACHE_SHIFT_6
|
||||
bool
|
||||
default y if CPU_V7
|
||||
help
|
||||
Setting ARM L1 cache line size to 64 Bytes.
|
||||
|
||||
|
|
|
@ -310,7 +310,7 @@ static void arm_memory_present(void)
|
|||
|
||||
static bool arm_memblock_steal_permitted = true;
|
||||
|
||||
phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align)
|
||||
phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
|
||||
{
|
||||
phys_addr_t phys;
|
||||
|
||||
|
|
|
@ -225,7 +225,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
|
|||
if ((area->flags & VM_ARM_MTYPE_MASK) != VM_ARM_MTYPE(mtype))
|
||||
continue;
|
||||
if (__phys_to_pfn(area->phys_addr) > pfn ||
|
||||
__pfn_to_phys(pfn) + size-1 > area->phys_addr + area->size-1)
|
||||
__pfn_to_phys(pfn) + offset + size-1 >
|
||||
area->phys_addr + area->size-1)
|
||||
continue;
|
||||
/* we can drop the lock here as we know *area is static */
|
||||
read_unlock(&vmlist_lock);
|
||||
|
|
|
@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume)
|
|||
* Initialise TLB, Caches, and MMU state ready to switch the MMU
|
||||
* on. Return in r0 the new CP15 C1 control register setting.
|
||||
*
|
||||
* We automatically detect if we have a Harvard cache, and use the
|
||||
* Harvard cache control instructions insead of the unified cache
|
||||
* control instructions.
|
||||
*
|
||||
* This should be able to cover all ARMv7 cores.
|
||||
*
|
||||
* It is assumed that:
|
||||
|
@ -251,9 +247,7 @@ __v7_setup:
|
|||
#endif
|
||||
|
||||
3: mov r10, #0
|
||||
#ifdef HARVARD_CACHE
|
||||
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
||||
#endif
|
||||
dsb
|
||||
#ifdef CONFIG_MMU
|
||||
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
|
||||
|
@ -329,16 +323,6 @@ __v7_ca5mp_proc_info:
|
|||
__v7_proc __v7_ca5mp_setup
|
||||
.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
|
||||
|
||||
/*
|
||||
* ARM Ltd. Cortex A7 processor.
|
||||
*/
|
||||
.type __v7_ca7mp_proc_info, #object
|
||||
__v7_ca7mp_proc_info:
|
||||
.long 0x410fc070
|
||||
.long 0xff0ffff0
|
||||
__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
|
||||
.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
|
||||
|
||||
/*
|
||||
* ARM Ltd. Cortex A9 processor.
|
||||
*/
|
||||
|
@ -350,6 +334,16 @@ __v7_ca9mp_proc_info:
|
|||
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
|
||||
#endif /* CONFIG_ARM_LPAE */
|
||||
|
||||
/*
|
||||
* ARM Ltd. Cortex A7 processor.
|
||||
*/
|
||||
.type __v7_ca7mp_proc_info, #object
|
||||
__v7_ca7mp_proc_info:
|
||||
.long 0x410fc070
|
||||
.long 0xff0ffff0
|
||||
__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
|
||||
.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
|
||||
|
||||
/*
|
||||
* ARM Ltd. Cortex A15 processor.
|
||||
*/
|
||||
|
|
|
@ -96,6 +96,6 @@ extern int mxc_gpio_mode(int gpio_mode);
|
|||
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
|
||||
const char *label);
|
||||
|
||||
extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
|
||||
extern int imx_iomuxv1_init(void __iomem *base, int numports);
|
||||
|
||||
#endif /* __MACH_IOMUX_V1_H__ */
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
/*
|
||||
|
|
|
@ -19,6 +19,7 @@ config MICROBLAZE
|
|||
select GENERIC_IRQ_SHOW
|
||||
select GENERIC_PCI_IOMAP
|
||||
select GENERIC_CPU_DEVICES
|
||||
select GENERIC_ATOMIC64
|
||||
|
||||
config SWAP
|
||||
def_bool n
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
#define _ASM_MICROBLAZE_ATOMIC_H
|
||||
|
||||
#include <asm-generic/atomic.h>
|
||||
#include <asm-generic/atomic64.h>
|
||||
|
||||
/*
|
||||
* Atomically test *v and decrement if it is greater than 0.
|
||||
|
|
|
@ -88,7 +88,6 @@ KBUILD_CFLAGS += -pipe -fno-strength-reduce -Wno-sign-compare
|
|||
KBUILD_AFLAGS += $(aflags-y)
|
||||
|
||||
OBJCOPYFLAGS := -O binary
|
||||
LDFLAGS_vmlinux := -e start
|
||||
|
||||
head-y := arch/s390/kernel/head.o
|
||||
head-y += arch/s390/kernel/$(if $(CONFIG_64BIT),head64.o,head31.o)
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue