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MLK-11387-3 ARM: imx: update ddr freq scale setting on imx7d

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To pass stress test in high temperature environment,
according to design team's suggestion, need to adjust
ddr phy setting for LPDDR3.

Signed-off-by: Anson Huang <b20788@freescale.com>
This commit is contained in:
Anson Huang 2015-08-20 20:25:28 +08:00 committed by Jason Liu
parent 7cec4347c7
commit 29503a35ad
1 changed files with 19 additions and 0 deletions
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19
arch/arm/mach-imx/lpddr3_freq_imx.S
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@ -15,6 +15,7 @@
#include <linux/linkage.h>
#include "hardware.h"
#define DDRC_MSTR 0x0
#define DDRC_STAT 0x4
#define DDRC_PWRCTL 0x30
#define DDRC_DBG1 0x304
@ -36,6 +37,7 @@
#define DDRPHY_OFFSETW_CON0 0x30
#define DDRPHY_OFFSETW_CON1 0x34
#define DDRPHY_OFFSETW_CON2 0x38
#define DDRPHY_RFSHTMG 0x64
#define DDRPHY_CA_DSKEW_CON0 0x7c
#define DDRPHY_CA_DSKEW_CON1 0x80
#define DDRPHY_CA_DSKEW_CON2 0x84
@ -118,8 +120,22 @@
.macro switch_to_below_100m
/* LPDDR2 and LPDDR3 has different setting */
ldr r8, [r4, #DDRC_MSTR]
ands r8, r8, #0x4
bne 9f
/* LPDDR3 */
ldr r7, =0x00000100
str r7, [r5, #DDRPHY_PHY_CON1]
b 10f
9:
/* LPDDR2 */
ldr r7, =0x10010100
str r7, [r5, #DDRPHY_PHY_CON1]
10:
ldr r7, =0x00020038
str r7, [r5, #DDRPHY_RFSHTMG]
ldr r6, =24000000
cmp r0, r6
@ -180,6 +196,9 @@
ldr r7, =0x10210100
str r7, [r5, #DDRPHY_PHY_CON1]
ldr r7, =0x00200038
str r7, [r5, #DDRPHY_RFSHTMG]
/* dram root set to from dram main, div by 2 */
ldr r7, =0x10000001
ldr r8, =0x9880