clk: mediatek: Add subsystem clocks of MT8173
Most multimedia subsystem clocks will be accessed by multiple drivers, so it's a better way to manage these clocks in CCF. This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT subsystems. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
This commit is contained in:
James Liao
parent
5661848956
commit
29859d9315
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@ -33,6 +33,10 @@ static DEFINE_SPINLOCK(mt8173_clk_lock);
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static const struct mtk_fixed_clk fixed_clks[] __initconst = {
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FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE),
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FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ),
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FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE),
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FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", DUMMY_RATE),
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FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", DUMMY_RATE),
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FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE),
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};
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static const struct mtk_fixed_factor top_divs[] __initconst = {
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@ -709,6 +713,183 @@ static const struct mtk_composite peri_clks[] __initconst = {
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MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
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};
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static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = {
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.set_ofs = 0x0004,
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.clr_ofs = 0x0008,
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.sta_ofs = 0x0000,
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};
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#define GATE_IMG(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &cg_regs_4_8_0, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate img_clks[] __initconst = {
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GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0),
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GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5),
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GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6),
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GATE_IMG(CLK_IMG_SEN_TG, "img_sen_tg", "camtg_sel", 7),
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GATE_IMG(CLK_IMG_SEN_CAM, "img_sen_cam", "mm_sel", 8),
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GATE_IMG(CLK_IMG_CAM_SV, "img_cam_sv", "mm_sel", 9),
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GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
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};
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static const struct mtk_gate_regs mm0_cg_regs __initconst = {
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.set_ofs = 0x0104,
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.clr_ofs = 0x0108,
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.sta_ofs = 0x0100,
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};
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static const struct mtk_gate_regs mm1_cg_regs __initconst = {
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.set_ofs = 0x0114,
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.clr_ofs = 0x0118,
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.sta_ofs = 0x0110,
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};
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#define GATE_MM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_MM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &mm1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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static const struct mtk_gate mm_clks[] __initconst = {
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/* MM0 */
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GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
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GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
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GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
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GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
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GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
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GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
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GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
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GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
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GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
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GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
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GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
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GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
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GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
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GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
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GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
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GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
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GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
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GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
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GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
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GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
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GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
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GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
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GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
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GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
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GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
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GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
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GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
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GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
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GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
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GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
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GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
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/* MM1 */
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GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
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GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
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GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
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GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
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GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
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GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
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GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
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GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
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GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
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GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
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GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
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GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
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GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
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GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
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GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
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GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
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GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
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GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
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GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
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GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
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GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
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};
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static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
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.set_ofs = 0x0000,
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.clr_ofs = 0x0004,
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.sta_ofs = 0x0000,
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};
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static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
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.set_ofs = 0x0008,
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.clr_ofs = 0x000c,
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.sta_ofs = 0x0008,
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};
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#define GATE_VDEC0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vdec0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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#define GATE_VDEC1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vdec1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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static const struct mtk_gate vdec_clks[] __initconst = {
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GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
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GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0),
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};
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#define GATE_VENC(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &cg_regs_4_8_0, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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static const struct mtk_gate venc_clks[] __initconst = {
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GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0),
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GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4),
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GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8),
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GATE_VENC(CLK_VENC_CKE3, "venc_cke3", "venc_sel", 12),
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};
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#define GATE_VENCLT(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &cg_regs_4_8_0, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_inv, \
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}
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static const struct mtk_gate venclt_clks[] __initconst = {
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GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0),
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GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
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};
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static struct clk_onecell_data *mt8173_top_clk_data __initdata;
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static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
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@ -872,3 +1053,89 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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}
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CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
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mtk_apmixedsys_init);
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static void __init mtk_imgsys_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
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mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
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static void __init mtk_mmsys_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
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mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
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static void __init mtk_vdecsys_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
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mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
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static void __init mtk_vencsys_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
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mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
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static void __init mtk_vencltsys_init(struct device_node *node)
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{
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struct clk_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
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mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
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clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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}
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CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);
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@ -153,12 +153,16 @@
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#define CLK_TOP_I2S2_M_SEL 135
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#define CLK_TOP_I2S3_M_SEL 136
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#define CLK_TOP_I2S3_B_SEL 137
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#define CLK_TOP_NR_CLK 138
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#define CLK_TOP_DSI0_DIG 138
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#define CLK_TOP_DSI1_DIG 139
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#define CLK_TOP_LVDS_PXL 140
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#define CLK_TOP_LVDS_CTS 141
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#define CLK_TOP_NR_CLK 142
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/* APMIXED_SYS */
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#define CLK_APMIXED_ARMCA15PLL 1
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#define CLK_APMIXED_ARMCA7PLL 2
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#define CLK_APMIXED_ARMCA15PLL 1
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#define CLK_APMIXED_ARMCA7PLL 2
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#define CLK_APMIXED_MAINPLL 3
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#define CLK_APMIXED_UNIVPLL 4
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#define CLK_APMIXED_MMPLL 5
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@ -232,4 +236,91 @@
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#define CLK_PERI_UART3_SEL 39
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#define CLK_PERI_NR_CLK 40
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/* IMG_SYS */
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#define CLK_IMG_LARB2_SMI 1
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#define CLK_IMG_CAM_SMI 2
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#define CLK_IMG_CAM_CAM 3
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#define CLK_IMG_SEN_TG 4
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#define CLK_IMG_SEN_CAM 5
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#define CLK_IMG_CAM_SV 6
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#define CLK_IMG_FD 7
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#define CLK_IMG_NR_CLK 8
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/* MM_SYS */
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#define CLK_MM_SMI_COMMON 1
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#define CLK_MM_SMI_LARB0 2
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#define CLK_MM_CAM_MDP 3
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#define CLK_MM_MDP_RDMA0 4
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#define CLK_MM_MDP_RDMA1 5
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#define CLK_MM_MDP_RSZ0 6
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#define CLK_MM_MDP_RSZ1 7
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#define CLK_MM_MDP_RSZ2 8
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#define CLK_MM_MDP_TDSHP0 9
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#define CLK_MM_MDP_TDSHP1 10
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#define CLK_MM_MDP_WDMA 11
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#define CLK_MM_MDP_WROT0 12
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#define CLK_MM_MDP_WROT1 13
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#define CLK_MM_FAKE_ENG 14
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#define CLK_MM_MUTEX_32K 15
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#define CLK_MM_DISP_OVL0 16
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#define CLK_MM_DISP_OVL1 17
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#define CLK_MM_DISP_RDMA0 18
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#define CLK_MM_DISP_RDMA1 19
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#define CLK_MM_DISP_RDMA2 20
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#define CLK_MM_DISP_WDMA0 21
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#define CLK_MM_DISP_WDMA1 22
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#define CLK_MM_DISP_COLOR0 23
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#define CLK_MM_DISP_COLOR1 24
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#define CLK_MM_DISP_AAL 25
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#define CLK_MM_DISP_GAMMA 26
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#define CLK_MM_DISP_UFOE 27
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#define CLK_MM_DISP_SPLIT0 28
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#define CLK_MM_DISP_SPLIT1 29
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#define CLK_MM_DISP_MERGE 30
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#define CLK_MM_DISP_OD 31
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#define CLK_MM_DISP_PWM0MM 32
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#define CLK_MM_DISP_PWM026M 33
|
||||
#define CLK_MM_DISP_PWM1MM 34
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||||
#define CLK_MM_DISP_PWM126M 35
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||||
#define CLK_MM_DSI0_ENGINE 36
|
||||
#define CLK_MM_DSI0_DIGITAL 37
|
||||
#define CLK_MM_DSI1_ENGINE 38
|
||||
#define CLK_MM_DSI1_DIGITAL 39
|
||||
#define CLK_MM_DPI_PIXEL 40
|
||||
#define CLK_MM_DPI_ENGINE 41
|
||||
#define CLK_MM_DPI1_PIXEL 42
|
||||
#define CLK_MM_DPI1_ENGINE 43
|
||||
#define CLK_MM_HDMI_PIXEL 44
|
||||
#define CLK_MM_HDMI_PLLCK 45
|
||||
#define CLK_MM_HDMI_AUDIO 46
|
||||
#define CLK_MM_HDMI_SPDIF 47
|
||||
#define CLK_MM_LVDS_PIXEL 48
|
||||
#define CLK_MM_LVDS_CTS 49
|
||||
#define CLK_MM_SMI_LARB4 50
|
||||
#define CLK_MM_HDMI_HDCP 51
|
||||
#define CLK_MM_HDMI_HDCP24M 52
|
||||
#define CLK_MM_NR_CLK 53
|
||||
|
||||
/* VDEC_SYS */
|
||||
|
||||
#define CLK_VDEC_CKEN 1
|
||||
#define CLK_VDEC_LARB_CKEN 2
|
||||
#define CLK_VDEC_NR_CLK 3
|
||||
|
||||
/* VENC_SYS */
|
||||
|
||||
#define CLK_VENC_CKE0 1
|
||||
#define CLK_VENC_CKE1 2
|
||||
#define CLK_VENC_CKE2 3
|
||||
#define CLK_VENC_CKE3 4
|
||||
#define CLK_VENC_NR_CLK 5
|
||||
|
||||
/* VENCLT_SYS */
|
||||
|
||||
#define CLK_VENCLT_CKE0 1
|
||||
#define CLK_VENCLT_CKE1 2
|
||||
#define CLK_VENCLT_NR_CLK 3
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT8173_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue