MLK-16136-1 clk: imx: imx8mq: define DCSS root clocks.
Define three root clocks for DCSS module: .IMX8MQ_CLK_DISP_AXI_ROOT .IMX8MQ_CLK_DISP_APB_ROOT .IMX8MQ_CLK_DISP_RTRM_ROOT These root clocks share one clock gate along with 'IMX8MQ_CLK_DISP_ROOT' clock. So change its type to be shared gate clock too. Signed-off-by: Fancy Fang <chen.fang@nxp.com>pull/10/head
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f6a5887e1c
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2a5a92e7ad
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@ -28,6 +28,7 @@ static u32 share_count_sai3;
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static u32 share_count_sai4;
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static u32 share_count_sai5;
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static u32 share_count_sai6;
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static u32 share_count_dcss;
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static struct clk *clks[IMX8MQ_CLK_END];
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@ -797,7 +798,10 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
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clks[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_gate4("vpu_g1_root_clk", "vpu_g1_div", base + 0x4560, 0);
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clks[IMX8MQ_CLK_GPU_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_core_div", base + 0x4570, 0);
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clks[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_gate4("vpu_g2_root_clk", "vpu_g2_div", base + 0x45a0, 0);
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clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate4("disp_root_clk", "disp_dc8000_div", base + 0x45d0, 0);
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clks[IMX8MQ_CLK_DISP_ROOT] = imx_clk_gate2_shared2("disp_root_clk", "disp_dc8000_div", base + 0x45d0, 0, &share_count_dcss);
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clks[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi_div", base + 0x45d0, 0, &share_count_dcss);
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clks[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb_div", base + 0x45d0, 0, &share_count_dcss);
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clks[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_gate2_shared2("disp_rtrm_root_clk", "disp_rtrm_div", base + 0x45d0, 0, &share_count_dcss);
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clks[IMX8MQ_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
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clks[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_gate4("vpu_dec_root_clk", "vpu_bus_div", base + 0x4630, 0);
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clks[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_gate4("csi1_root_clk", "csi1_core_div", base + 0x4650, 0);
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@ -608,5 +608,10 @@
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#define IMX8MQ_VIDEO2_PLL2_OUT 474
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#define IMX8MQ_CLK_TMU_ROOT 475
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#define IMX8MQ_CLK_END 476
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/* Display root clocks */
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#define IMX8MQ_CLK_DISP_AXI_ROOT 476
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#define IMX8MQ_CLK_DISP_APB_ROOT 477
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#define IMX8MQ_CLK_DISP_RTRM_ROOT 478
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#define IMX8MQ_CLK_END 479
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#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
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