This device-tree pxa update brings :
- pxa25x support - cpu operating points in preparation for cpufreq-dt - small fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYLyfrAAoJEAP2et0duMsSNDIP/iawhBloix8n9XH0qZWKNX5a Tq/ZIjhMTI3ncp6yKRCju3cNsZ32XwjE8/OkTkdEGp6AGbgc3u0AdBZU21qYUBDt B/qsN7EAiXoJPMvRy/2yfnmO+G4McZQxkhU8rdCBSffn6wayAISMGNp9xJ49s55g bYl3fFT5jHQ1fLS7XxssSThMg1IZ6myCBqWm6efAgxTUqE0gdwIe3/h8+9kNZSF6 GUuHhB1A3RAOOI7pFyM9z4Gq8pXxQ19L7oI8Ka4eIGwATeHU6GTpaaR7tSRM6CkX qFear02/z+9WTIvUjIhzSKhiDyHeB8nTVQUhUTyoQDOLKV0AWrlZ6y8/0dpa+PDp Xn8znF6btxMCHo/lIarRQ2phK64sgoSThrpKWk7WyzQyAbA865vcqYxobQwgjUNX qrS/eB9s6HZjL6jv8RD9AYrVAv4VpiGjY58q3sLdFBVB8Otr5kKrcY8kc47jo0Kc hRDXW2OAuX/IUEbD5KZKdrcfqoa2Qy2K4oGpAUGPhhmpmNh7xlchi/vcAmmHAVDl /Zge+d+pzZ12r0PHrGnyeNZ7oruncRHL2YHN3tPgP3c1kuA53tZFkBxrDGcWdfmf vwDYeNI8KlH9jmRkFAgqEhGk4nDk+B2z6nyFkp+aAGm7ZZriZP/TtR80Mym3PixD XH1qx1FUCoamXS0qe57I =j3ZP -----END PGP SIGNATURE----- Merge tag 'pxa-dt-4.10' of https://github.com/rjarzmik/linux into next/dt Pull "This device-tree pxa update brings" from Robert Jarzmik: - pxa25x support - cpu operating points in preparation for cpufreq-dt - small fixes * tag 'pxa-dt-4.10' of https://github.com/rjarzmik/linux: ARM: dts: pxa: add pxa27x cpu operating points ARM: dts: pxa: add pxa25x cpu operating points ARM: dts: pxa: fix gpio0 and gpio1 interrupts ARM: dts: pxa: fix no. of gpio cells in the pxa gpio binding documentation ARM: dts: pxa: add pxa25x .dtsi file
This commit is contained in:
Arnd Bergmann
commit
2ad5c1a5fc
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@ -17,7 +17,9 @@ Required properties:
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source.
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- gpio-controller : Marks the device node as a gpio controller.
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- #gpio-cells : Should be one. It is the pin number.
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- #gpio-cells : Should be two. The first cell is the pin number and
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the second cell is used to specify flags. See gpio.txt for possible
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values.
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Example for a MMP platform:
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@ -27,7 +29,7 @@ Example for a MMP platform:
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interrupts = <49>;
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interrupt-names = "gpio_mux";
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gpio-controller;
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#gpio-cells = <1>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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117
arch/arm/boot/dts/pxa25x.dtsi
Normal file
117
arch/arm/boot/dts/pxa25x.dtsi
Normal file
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@ -0,0 +1,117 @@
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/*
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* Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "pxa2xx.dtsi"
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#include "dt-bindings/clock/pxa-clock.h"
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/ {
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model = "Marvell PXA25x family SoC";
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compatible = "marvell,pxa250";
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clocks {
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/*
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* The muxing of external clocks/internal dividers for osc* clock
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* sources has been hidden under the carpet by now.
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*/
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clks: pxa2xx_clks@41300004 {
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compatible = "marvell,pxa250-core-clocks";
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#clock-cells = <1>;
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status = "okay";
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};
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/* timer oscillator */
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clktimer: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <3686400>;
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clock-output-names = "ostimer";
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};
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};
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pxabus {
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pdma: dma-controller@40000000 {
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compatible = "marvell,pdma-1.0";
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reg = <0x40000000 0x10000>;
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interrupts = <25>;
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#dma-channels = <16>;
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#dma-cells = <2>;
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#dma-requests = <40>;
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status = "okay";
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};
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pxairq: interrupt-controller@40d00000 {
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marvell,intc-priority;
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marvell,intc-nr-irqs = <32>;
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};
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pinctrl: pinctrl@40e00000 {
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reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
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0x40f00020 0x10>;
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compatible = "marvell,pxa25x-pinctrl";
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};
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gpio: gpio@40e00000 {
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compatible = "intel,pxa25x-gpio";
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gpio-ranges = <&pinctrl 0 0 84>;
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clocks = <&clks CLK_NONE>;
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};
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pwm0: pwm@40b00000 {
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compatible = "marvell,pxa250-pwm";
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reg = <0x40b00000 0x10>;
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#pwm-cells = <1>;
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clocks = <&clks CLK_PWM0>;
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};
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pwm1: pwm@40b00010 {
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compatible = "marvell,pxa250-pwm";
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reg = <0x40b00010 0x10>;
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#pwm-cells = <1>;
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clocks = <&clks CLK_PWM1>;
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};
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};
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timer@40a00000 {
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compatible = "marvell,pxa-timer";
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reg = <0x40a00000 0x20>;
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interrupts = <26>;
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clocks = <&clktimer>;
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status = "okay";
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};
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pxa250_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp@99532800 {
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opp-hz = /bits/ 64 <99532800>;
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opp-microvolt = <1000000 950000 1650000>;
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clock-latency-ns = <20>;
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};
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opp@199065600 {
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opp-hz = /bits/ 64 <199065600>;
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opp-microvolt = <1000000 950000 1650000>;
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clock-latency-ns = <20>;
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};
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opp@298598400 {
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opp-hz = /bits/ 64 <298598400>;
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opp-microvolt = <1100000 1045000 1650000>;
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clock-latency-ns = <20>;
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};
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opp@398131200 {
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opp-hz = /bits/ 64 <398131200>;
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opp-microvolt = <1300000 1235000 1650000>;
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clock-latency-ns = <20>;
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};
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};
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};
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@ -137,4 +137,44 @@
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clocks = <&clks CLK_OSTIMER>;
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status = "okay";
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};
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pxa270_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp@104000000 {
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opp-hz = /bits/ 64 <104000000>;
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opp-microvolt = <900000 900000 1705000>;
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clock-latency-ns = <20>;
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};
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opp@156000000 {
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opp-hz = /bits/ 64 <156000000>;
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opp-microvolt = <1000000 1000000 1705000>;
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clock-latency-ns = <20>;
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};
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opp@208000000 {
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opp-hz = /bits/ 64 <208000000>;
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opp-microvolt = <1180000 1180000 1705000>;
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clock-latency-ns = <20>;
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};
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opp@312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <1250000 1250000 1705000>;
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clock-latency-ns = <20>;
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};
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opp@416000000 {
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opp-hz = /bits/ 64 <416000000>;
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opp-microvolt = <1350000 1350000 1705000>;
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clock-latency-ns = <20>;
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};
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opp@520000000 {
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opp-hz = /bits/ 64 <520000000>;
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opp-microvolt = <1450000 1450000 1705000>;
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clock-latency-ns = <20>;
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};
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opp@624000000 {
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opp-hz = /bits/ 64 <624000000>;
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opp-microvolt = <1550000 1550000 1705000>;
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clock-latency-ns = <20>;
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};
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};
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};
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@ -54,8 +54,8 @@
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reg = <0x40e00000 0x10000>;
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gpio-controller;
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#gpio-cells = <0x2>;
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interrupts = <10>;
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interrupt-names = "gpio_mux";
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interrupts = <8>, <9>, <10>;
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interrupt-names = "gpio0", "gpio1", "gpio_mux";
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interrupt-controller;
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#interrupt-cells = <0x2>;
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ranges;
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