perf, x86: Consolidate some code repetition
Remove some duplicated logic. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -452,14 +452,54 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
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static int intel_pmu_save_and_restart(struct perf_event *event);
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static void __intel_pmu_pebs_event(struct perf_event *event,
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struct pt_regs *iregs, void *__pebs)
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{
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/*
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* We cast to pebs_record_core since that is a subset of
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* both formats and we don't use the other fields in this
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* routine.
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*/
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struct pebs_record_core *pebs = __pebs;
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struct perf_sample_data data;
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struct pt_regs regs;
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if (!intel_pmu_save_and_restart(event))
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return;
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perf_sample_data_init(&data, 0);
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data.period = event->hw.last_period;
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/*
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* We use the interrupt regs as a base because the PEBS record
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* does not contain a full regs set, specifically it seems to
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* lack segment descriptors, which get used by things like
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* user_mode().
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*
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* In the simple case fix up only the IP and BP,SP regs, for
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* PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
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* A possible PERF_SAMPLE_REGS will have to transfer all regs.
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*/
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regs = *iregs;
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regs.ip = pebs->ip;
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regs.bp = pebs->bp;
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regs.sp = pebs->sp;
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if (intel_pmu_pebs_fixup_ip(regs))
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regs.flags |= PERF_EFLAGS_EXACT;
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else
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regs.flags &= ~PERF_EFLAGS_EXACT;
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if (perf_event_overflow(event, 1, &data, ®s))
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x86_pmu_stop(event);
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}
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static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct debug_store *ds = cpuc->ds;
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struct perf_event *event = cpuc->events[0]; /* PMC0 only */
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struct pebs_record_core *at, *top;
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struct perf_sample_data data;
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struct pt_regs regs;
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int n;
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if (!ds || !x86_pmu.pebs)
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@ -485,9 +525,6 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
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if (n <= 0)
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return;
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if (!intel_pmu_save_and_restart(event))
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return;
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/*
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* Should not happen, we program the threshold at 1 and do not
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* set a reset value.
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@ -495,31 +532,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
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WARN_ON_ONCE(n > 1);
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at += n - 1;
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perf_sample_data_init(&data, 0);
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data.period = event->hw.last_period;
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/*
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* We use the interrupt regs as a base because the PEBS record
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* does not contain a full regs set, specifically it seems to
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* lack segment descriptors, which get used by things like
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* user_mode().
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*
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* In the simple case fix up only the IP and BP,SP regs, for
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* PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
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* A possible PERF_SAMPLE_REGS will have to transfer all regs.
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*/
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regs = *iregs;
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regs.ip = at->ip;
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regs.bp = at->bp;
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regs.sp = at->sp;
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if (intel_pmu_pebs_fixup_ip(®s))
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regs.flags |= PERF_EFLAGS_EXACT;
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else
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regs.flags &= ~PERF_EFLAGS_EXACT;
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if (perf_event_overflow(event, 1, &data, ®s))
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x86_pmu_stop(event);
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__intel_pmu_pebs_event(event, iregs, at);
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}
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static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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@ -527,9 +540,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct debug_store *ds = cpuc->ds;
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struct pebs_record_nhm *at, *top;
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struct perf_sample_data data;
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struct perf_event *event = NULL;
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struct pt_regs regs;
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u64 status = 0;
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int bit, n;
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@ -571,27 +582,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
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if (!event || bit >= MAX_PEBS_EVENTS)
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continue;
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if (!intel_pmu_save_and_restart(event))
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continue;
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perf_sample_data_init(&data, 0);
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data.period = event->hw.last_period;
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/*
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* See the comment in intel_pmu_drain_pebs_core()
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*/
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regs = *iregs;
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regs.ip = at->ip;
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regs.bp = at->bp;
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regs.sp = at->sp;
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if (intel_pmu_pebs_fixup_ip(®s))
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regs.flags |= PERF_EFLAGS_EXACT;
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else
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regs.flags &= ~PERF_EFLAGS_EXACT;
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if (perf_event_overflow(event, 1, &data, ®s))
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x86_pmu_stop(event);
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__intel_pmu_pebs_event(event, iregs, at);
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}
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}
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